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INTRODUCTION TO A 10A MONOLITHIC SWITCHING REGULATOR IN MULTIPOWER-BCD TECHNOLOGY 1738 - Datasheet Archive
Application Note
[ST] INTRODUCTION TO A 10A MONOLITHIC SWITCHING REGULATOR IN MULTIPOWER-BCD TECHNOLOGY
AN487
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APPLICATION NOTE

INTRODUCTION TO A 10A MONOLITHIC SWITCHING

REGULATOR IN MULTIPOWER-BCD TECHNOLOGY

by C.Diazzi

Switched mode techniques led to the develop-

ment of high efficiency circuits offering space sav-

ing and a reduction in costs, mainly of the

heatsink and output LC filter. For these applica-

tions a new technology, called MULTIPOWER-

BCD, has been developed which allows the inte-

gration on the same chip of isolated power DMOS

elements, Bipolar transistors and CMOS logic.

The technology is particularly suitable for the

problems rising in the switch mode field, due to

the characteristics of high efficiency, fast switch-

ing speed, no secondary breakdown of the power

DMOS element.

The great flexibility that we have at our disposal

for the choice of the signal and driving sections

components allows optimization and compact-

ness of the system. With MULTIPOWER-BCD it

has been possible to implement the family L497X,

a new series of fully integrated switching regula-

tors suitable for DC-DC converters working in

Buck configuration. The complete family consists

of five devices which differ each other only by the

output current value (2A, 3.5A, 5A, 7A, 10A) they

can deliver to the load. The devices rated at 2A

and 3.5A are assembled in Power Dip (16+2+2),

while the others are assembled in the Multiwatt15

package. Each device integrates a DMOS output

power stage, a control section, limiting current

and supervisor functions like Reset and Power

Fail signal for microprocessors applications.

Output voltage can be adjusted starting from the

internal reference voltage (5.1V) up to 40V, allow-

ing a maximum output power of 80W for the 2A

version and of 400W for the 10A version. Maxi-

mum operating supply voltage is 55V.

THE TECHNOLOGY

The technology architecture is based on the verti-

cal DMOS silicon gate process that allows a

channel length of 1.5 micron ; using a junction

isolation technique it has been possible to mix on

the same chip Bipolar and CMOS transistors

along with the DMOS power components (Fig. 2).

Figure 1 shows how this process brings a rapid

increase in power IC complexity compared to

conventional bipolar technology.

AN487/0592

The L497X series of high current switching regulator ICs exploit Multipower-BCD technology to

achieve very high output currents with low power dissipation - up to 10A in the Multiwatt power

package and 3.5A in a DIP package .

Figure 1:

BCD process and increase in power ICs complexity.

1/12

In the 70's class B circuits and DC circuits al-

lowed output power in the range of 70W. By 1980

,with the introduction of switching techniques in

power ICs, output powers up to 200W were

reached ; with BCD technology the output power

increased up to 400W.

FUNCTIONS AND BLOCK DIAGRAM

The complete block diagram of the high power

L4970A is shown in fig.3. Each block is analysed

in the following.

POWER SUPPLY

The device is provided with an internal stabilized

power supply ( Vstart =12V ), that provides the

supply voltage to the analog and digital control

blocks and also the supply voltage to the boot-

strap section. The Vstart voltage supplies also the

internal Reference Voltage section that provides

accurate 5.1V voltage to the control loop.

Through trimming techniques the 5.1V reference

is within +- 2% limits.

OSCILLATOR and FEDFORWARD

The oscillator block (fig.4) generates the sawtooth

Figure 2:

Cross section of the BCD mixed technology.

Figure 3:

Block diagram of the 10A monolithic regulator L4970A.

APPLICATION NOTE

2/12

waveform that sets the switching frequency of the

system. The signal, compared with the output

voltage of the error amplifier, generates the PWM

signal to be sent to the power output stage. The

oscillator features a voltage feed-forward tech-

nique which is completely integrated and doesn't

require any external component. Feed-forward

function works in the supply voltage range 15-

45V. The rate of increase of the sawtooth wavw-

form is directly proportional to the input voltage

Vcc. As Vcc increases, the output pulse-width

(transistor on-time) decreases in such a manner

as to provide a constant "volt-second' product to

the inductance(fig.5).

From fig.5 it is shown that the duty cycle changes

due to the ramp increase when Vcc increases.

The error amplifier output doesn't have to change

to keep the loop in regulation. This feature in-

creases significantly the line regulation perform-

ance.

A resistor, between Rosc and GND , defines a

current that is mirrored internally to charge the os-

cillator capacitor on the Cosc pin. The voltage at

pin.Rosc is a function of Vcc value for the imple-

mentation of the feed-forward function (oscillator

slope proportional to Vcc). A comparator is sens-

ing the voltage across Cosc capacitor and dis-

carge it when the ramp exceedes an upper

threshold proportional to Vcc for the implementa-

tion of the feed-forward function. The Cosc dis-

charge current is internally controlled at a value of

about 20 mA. The lower threshold of the compa-

rator is about 1.3V (2VBE). Here are reported ba-

sic equations for the oscillator:

I

CHARGE

=

V

CC

-

9V

BE

R

osc.

for 15V Co, the

Bode diagram of the compensated amplifier is re-

ported (see fig.14).

The compensation network introduces a low fre-

quency pole and a zero that usually is put at the

frequency of the resonant pole of the output LC

filter. The second high frequency pole is usually

at a frequency of no interest. If needed , more so-

phisticated compensation circuits can be used by

feedback with the opamp. An example is shown

in fig.15.

Figure 11:

Open loop gain (error amplifier only).

Figure 12:

Error amplifier equivalent circuit.

Figure 13:

Compensation network of the error

amplifier.

Figure 14:

Bode plot showing gain and phase of

compensated error amplifier.

APPLICATION NOTE

6/12

Such a configuration introduces a low frequency

pole and two zeros Z1 = 1/2

P

R1C1 and Z2 =

1/2

P

R2C2. Note that due to the high output im-

pedance it is present also a second pole p2 =

gm/2

P

C1. Usually it is better to use the highest

possible value for R1, to have a low value for C1

in such a way to put p2 at the highest frequency.

Limitations to R1 value are put by offset voltage

due to opamp. input bias currents.

If a resistive divider is used at the output of the

power supply, for voltages higher than 5.1V, it is

possible to introduce a second zero with the net-

work of fig.16.

Such a configuration introduce 2 zeros at:

Z

1

=

1

2

P

R

c

C

c

;

Z

2

=

1

2

P

R

1

C

1

and 2 poles at:

P

1

=

1

2

P

R

o

C

c

; P

2

=

1

2

P

R

x

C

1

; R

X

=

R

1

R

2

R

1

+

R

2

APPLICATION EXAMPLE

Consider the block diagram of fig.17, representing

the internal control loop section, with the applica-

tion values:

Fswitch = 200KHz, L = 100

m

H, C =1000

m

F,

Po=50W, Vo =5.1V, Io =10A and Fo = 500Hz.

G

loop

= PWM

V

Filter

The system requires that DC gain is maximum to

achieve good accuracy and line rejection. Beyond

this a bandwidth of some KHz is usually required

for a good load transient response. The error am-

plifier transfer function must guarantee the above

constraints. A compensation network that could

be used is shown in fig.19.

A ( s

)

=

( 1

+

sR

1

C

1

)

(

1

+

sR

2

C

2

)

sR

1

C

1

(

1

+

s

C

1

G

M

)

Figure 15:

One pole, two zero compensation

network.

Figure 16:

Compensation network for output

voltages higher than 51V.

Figure 17:

Block diagram used in stability

calculation.

Figure 18:

Frequency behavior of the circuit of

fig 17.

Figure 19:

Compensation network.

APPLICATION NOTE

7/12

The criterium is to define Z1, Z2 close to the reso-

nant pole of the output LC filter. The Gm/2

P

C

1

pole must be placed at a frequency at which open

loop gain is below 0 dB axis (Fig. 20).

CURRENT LIMITATION

Current limitation is implemented intrnally to the

chip and doesn't need any external component.

The output current is sensed by an internal resis-

tor in series with the drain of the power transistor.

On chip trimming guarantees +10% accuracy on

the value of peak current limitation.

Current limit protection works pulse by pulse with

lowering of tnhe switching frequency. Fig.21

shows circuital implementation of current protec-

tion.

Figure 20:

Bode plot of the regulation loop with the compensation network of fig. 19.

Figure 21:

Current protection circuit.

APPLICATION NOTE

8/12

When the comparator senses an overcurrent, the

flip-flop is set and an internal inhibit signal is gen-

erated. The flip-flop remains set until next reset

clock pulse coming from the internal 40 KHz oscil-

lator. After the reset pulse the regulation loop

takes the control of the system and the output

current begins to increase to the load value at the

switching frequency of the master clock. If the

overload condition is still present the protection

cycle repeats. This mixed, pulse by pulse, lower-

ing frequency current protection method, assures

a constant current output when the system is in

overload or short circuit and allows to implement

a reliable current limitation even at high switching

frequency (500 KHz) reducing the problems of

signal delay through the protection stage. Fig.22

shows behavior of the inductance current when

the system is in overload.

The internal 40 KHz oscillator is synchronized

with the master clock. When the system works

with the master clock at a lower frequency of the

internal clock, than the internal clock tracks the

master frequency. This assures that the fre-

quency does not increas during overload.

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit that

may be used to generate a power on power off

reset signal for a microprocessor system. The cir-

cuit senses the input supply voltage and the out-

put generated voltage and will generate the re-

quired reset signal only when both the sensed

voltages have reached the required value for cor-

rect system operation. The Reset signal is gener-

ated after a delay time programmable by an ex-

ternal capacitor on the delay pin. Fig. 23 shows

the circuit implementation of Reset circuit. The

supply voltage is sensed on an external pin, for

programmability of the threshold, by a first com-

parator. The second comparator has the refer-

ence threshold set at slightly less the ref. voltage

for the regulation circuit and the other input con-

nected internally at the feedback point on the er-

ror amplifier. This allows to sense the output

regulated voltage. When both the supply voltage

and the regulated voltage are in the correct

range, transistor Q1 turns off and allows the cur-

rent generator to charge the delay capacitor.

When the capacitor voltage reaches 5V the out-

put Reset signal is generated. A latch assures

that if a spike is present on the sensed voltage

the delay capacitor discharges completely before

initialization of a new Reset cycle. The output

gate assures immediate take of reset signal with-

Figure 22:

Overload inductance current.

Figure 23:

Power fail and reset circuit.

APPLICATION NOTE

9/12

out waiting for complete discharge of delay ca-

pacitor. Reset output is an open collector transis-

tor capable of sinking 20mA at 200mV volt-

age.Fig. 24 shows reset waveforms.

THE POWER STAGE

A simplified schematic of the output stage along

with the external filter components is shown in

fig.25.

Power stage and associated driving circuits are

among the most critical components to achieve

good performances at high switching frequency.

An external bootstrap capacitance, charged via

diode D1 at 12V, is needed to provide the correct

gate drive to the power DMOS N-channel transis-

tor. The driving circuit is able to deliver a current

peak of 0.5A, during turn on and turn off phases,

to the gate of power DMOS transistor. The circuit-

described shows commutation times of 50ns.

Figure 24:

Reset and power fail waveforms.

Figure 25:

Power stage circuit.

APPLICATION NOTE

10/12

The five devices of L497X family differentiate

each other only for the level of current protection,

while the control part is the same and power de-

vice area is the same to guarantee low power dis-

sipation also for low current versions in DIP pack-

age.

Table 1 and fig.26 shows electrical characteristics

of the power DMOS implemented in the chip.

THERMAL PROTECTION

The thermal protection function operates when

the junction temperature reaches 150

5

C; it acts

directly on the power soft start capacitor, dis-

charging it. The thermal protection is provided

with hysteresis and therefore, after an interven-

tion has occurred, it is necessary to wait for the

junction temperature to decrease of about 30 de-

gree C below the intervention threshold.

Table 1.

B

VDSS

> 60V at I

D

= 1mA V

GS

= 0V

R

DS(ON)

= 100m

W

at I

D

= 10A T

j

= 25

5

C V

GS

= 10V

R

DS(ON)

= 150m

W

at I

D

= 10A T

j

= 150

5

C V

GS

= 10V

V

TH

= 3V at I

D

= 1mA

Figure 26:

Gate-charge curve for the power

DMOS.

APPLICATION NOTE

11/12

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-

THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express

written approval of SGS-THOMSON Microelectronics.

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APPLICATION NOTE

12/12

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