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CP3500AC52TEZ-FB GE Critical Power CP3500AC52TE-FB Global Platform High Efficiency Rectifier, Input: 100-120/200-240 Vac; 3500W capable; Default set: ±52 Vdc @; 5 Vdc @ 10W
ISL95810WIRT8ZR5481 Intersil Corporation ISL95810W PRE-PROGRAMMED TO LOWEST RESISTANCE SETTING, XDCP,
ISL9491AERZ-T Intersil Corporation Single Output LNB Supply Voltage Regulator for Satellite Set-Top Box Applications; QFN16; Temp Range: -25° to 85°C
ISL9491ERZ Intersil Corporation Single Output LNB Supply Voltage Regulator for Satellite Set-Top Box Applications; QFN16; Temp Range: -25° to 85°C
ISL9491ERZ-T Intersil Corporation Single Output LNB Supply Voltage Regulator for Satellite Set-Top Box Applications; QFN16; Temp Range: -25° to 85°C
ISL9491AERZ Intersil Corporation Single Output LNB Supply Voltage Regulator for Satellite Set-Top Box Applications; QFN16; Temp Range: -25° to 85°C

VFPv4 instruction set

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: to provide support for the ARM v7 Advanced SIMD v2 and Vector Floating-Point v4 (VFPv4) instruction , full instruction set and usage details. ARM DDI 0450A ID012010 Copyright © 2009 ARM. All rights , when describing their behavior, for example, Harvard architecture, instruction set architecture, ARMv6 , Introduction This chapter introduces the Cortex-A5 implementation of the ARM Single Instruction Multiple , (quad) registers See the ARM Architecture Reference Manual for details of the extension register set ARM
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VFPv4 VFPv3 instruction set cortex-a5 ARM IHI 0029 ARMv6 Architecture Reference Manual cortex-a5 integration manual
Abstract: and VFPv4 extensions. See the ARM Architecture Reference Manual for full instruction set and usage , Advanced SIMD v2 and Vector Floating-Point v4 (VFPv4) instruction sets. The Cortex-A5 NEON MPE supports , when describing their behavior, for example, Harvard architecture, instruction set architecture, ARMv6 , chapter introduces the Cortex-A5 implementation of the ARM Single Instruction Multiple Data (SIMD) media , ARM Architecture Reference Manual for details of the extension register set. The operations include ARM
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ARMv7 Architecture Reference Manual cortex-a5 processor coresight CoreSight Architecture Specification IEEE 754 cortex-a5 dit 0001 0450B ID101810
Abstract: implementation of the ARM VFPv4 extension. See the ARM Architecture Reference Manual for full instruction set , root operations as described in the ARM VFPv4 architecture. It provides conversions between 16-bit, 32 , About the programmers model This section introduces the Cortex-A5 FPU implementation of the VFPv4 , bit set to 1. · The Cortex-A5 FPU never generates an asynchronous VFP exception. In addition , instruction results in an Undefined Instruction exception being taken. To enable software to access VFP ARM
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ARM cortex instruction set fpu coprocessor PL310 CP15 ARMv7 neon
Abstract: Cortex-A5 FPU implementation of the ARM VFPv4 extension. See the ARM Architecture Reference Manual for full instruction set and usage details. ARM DDI 0449B ID101810 Copyright © 2009, 2010 ARM. All rights , accumulate, and square root operations as described in the ARM VFPv4 architecture. It provides conversions , programmers model This section introduces the Cortex-A5 FPU implementation of the VFPv4 floating-point , execute a vector operation results in a synchronous bounce, with the FPEXC.DEX bit set to 1. · The ARM
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VFPv4-D16 AT551-DC-06001 VFPv3 ARMv7 exception arm generic interrupt controller v3 AT551
Abstract: ) . 3-21 Instruction set overview , Register on page 3-20 · Saved Program Status Registers (SPSRs) on page 3-21 · Instruction set overview , define a 16-bit instruction set called the Thumb instruction set. Most of the functionality of the 32-bit ARM instruction set is available, but some operations require more instructions. The Thumb instruction set provides better code density, at the expense of performance. ARMv6T2 introduces a major ARM
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ID102510 ARMv6-M VFPv3-FP16 Q0-Q15 PXA270 datasheet PXA270 assembler 0473B
Abstract: Tag_FP_arch, added values for VFPv4; renamed Tag_VFP_HP_extension to Tag_FP_HP_extension; added value to , standard requirement is met. VFP The ARM architecture's Floating Point architecture and instruction set ARM IHI 0045C Copyright © 2005-2009 ARM Limited. All rights reserved. Page 7 of 40 , thereof that complies with this Specification, but are not themselves expressly set forth in this , . Use, copying or disclosure by the US Government is subject to the restrictions set out in subparagraph ARM
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ARM SC300 ARMv2 ARM wmmx LEB128 ARM v7 ARMv7-M Architecture Reference Manual LEC-ELA-00081
Abstract: VFPv4-D16 . L1 instruction side memory system , . 4-5 Set/Way bit assignments , . 7-9 Instruction Cache Tag and Data location encoding . 7-9 Instruction Cache Tag data format , . 2-11 Set/Way bit assignments ARM
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cortex 5 CP14 8 stage pipeline architecture of ARMv7 cortex a5
Abstract: 0xc5acce55 VFPv4 VFPv4-D16 C15-C40 awid communication protocol AT551 VMSA at550 . L1 instruction side memory system , . 4-5 Set/Way bit assignments , . 7-9 Instruction Cache Tag and Data location encoding . 7-9 Instruction Cache Tag data format , . 2-11 Set/Way bit assignments ARM
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mrc 438 CP15SDISABLE arm cortex a5 mpcore Cpi 1009 ATB flush 0433B
Abstract: . 6-50 Instruction set and syntax selection directives , 3.10 3.11 3.12 3.13 3.14 Chapter 4 Instruction summary . 3-2 Instruction width specifiers , . 2-3 Instruction summary , particular variant of AAPCS. They cause attributes to be set in the object file produced by the assembler Freescale Semiconductor
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Abstract: ,Marvell pxa270 . L1 instruction side memory system , . 4-5 Set/Way bit assignments , . 7-9 Instruction Cache Tag and Data location encoding . 7-9 Instruction Cache Tag data format , . 2-16 Set/Way bit assignments ARM
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ARMv4 reference ARMv6 Cortex-A8 VFPv3D16 PXA270 programmer guide ophn 0489B
Abstract: CORTEX-A9 PL390 . L1 instruction side memory system , . 4-5 Set/Way bit assignments , . 7-9 Instruction Cache Tag and Data location encoding . 7-9 Instruction Cache Tag data format , . 2-16 Set/Way bit assignments ARM
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cortex a9 core processor architecture arm generic interrupt controller ARM cortex A9 neon arm cortex a9 mpcore ID052910
Abstract: '"ATARMâ'"08-Mar-13 1. Features Core ARM® Cortex®-A5 Processor with ARM v7-A Thumb2® Instruction Set CPU Frequency up to 536 MHz 32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA) Fully Integrated MMU and Floating Point Unit (VFPv4) Memories One 160 Kbyte Internal ROM , comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image , property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET ARM
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CP15 Powered Monitor PL390 ARM Architecture Reference Manual jazelle reference manual jazelle ARM DII 0015 0434B
Abstract: Architecture Instruction Set ­ 32KB L1 Instruction and Data Caches per Core ­ AMBA 4.0 AXI Coherency Extension , Description Standard Cortex-A15 processor instruction set + Thumb2, ThumbEE, JazelleX Java accelerator, and , of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share , A15 Cores ARM Cores ARM L1 instruction cache memory size (per core) ARM L1 data cache memory size (per , technology) and VFPv4 (Vector Floating Point) architecture extensions, security, virtualization, LPAE (Large Atmel
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IEEE1588
Abstract: '" Full Implementation of ARMv7-A Architecture Instruction Set â'" 32KB L1 Instruction and Data Caches , Description ARM version 7-A ISA Standard Cortex-A15 processor instruction set + Thumb2, ThumbEE , of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache , 4 ARM L1 instruction cache memory size (per core) ARM L1 data cache memory size (per core , VFPv4 (Vector Floating 10 AM5K2E04/02 Features and Description Copyright 2013 Texas Instruments Texas Instruments
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SPRUG ARM Cortex A15 EMIF16 cortex-a15 mpu5 Hyperlink teranet SPRS864 SPRS864--N ISO/TS16949
Abstract: Instruction Set ­ 32KB L1 Instruction and Data Caches per Core ­ AMBA 4.0 AXI Coherency Extension (ACE) Master , Instruction Set Reference Guide · C66x DSP Cache User Guide · C66x CorePac User Guide PRODUCT PREVIEW , for the C66x DSP User Guide C66x CorePac User Guide C66x CPU and Instruction Set Reference Guide C66x , Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. In the DSP CorePac , ) DSP L2 Unified cache/RAM memory size (per core) ARM Cortex A15 Cores ARM Cores ARM L1 instruction Texas Instruments
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SPRS864A
Abstract: Processor Cores â'" Full Implementation of ARMv7-A Architecture Instruction Set â'" 32KB L1 Instruction , Documentation from Texas Instrumentsâ'™â'™ on page 15): â'¢ C66x CPU and Instruction Set Reference Guide â , SPRUGW0 C66x CPU and Instruction Set Reference Guide SPRUGH7 C66x DSP Cache User Guide SPRUGY8 , 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache , ARM L1 instruction cache memory size (per core) ARM L1 data cache memory size (per core) 32KB Texas Instruments
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SPRS865 ARM cortex a15 cpu teranet Rake search accelerator CMAC 0218 ARM Cortex-A15 66AK2E05/02 SPRS865--N
Abstract: ARM Cores ­ Full Implementation of ARMv7-A Architecture Instruction Set ­ 32KB L1 Instruction and Data , C66x CPU and Instruction Set Reference Guide · C66x DSP Cache User Guide · C66x CorePac User Guide , The TCI6630K2L device has a complete set of development tools that includes: a C compiler, an assembly , SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture Texas Instruments
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SPRS865A 1024K
Abstract: This option is a request to the compiler to target the ARM instruction set. The compiler is permitted , . Default This is the default option for targets supporting the ARM instruction set. See also · · ARM , . 5-50 Instruction intrinsics , . 6-11 ARMv6 SIMD Instruction Intrinsics A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A , instruction intrinsics and APSR GE flags . A-10 _qadd16 intrinsic Texas Instruments
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TCI6630 PCIe Endpoint SCR 3 phase RSA ARM MPU6-MPU11 lte baseband mbps SPRS893 SPRS893--M
Abstract: '"ATARMâ'"03-Oct-13 1. Features  Core  ARM® Cortex®-A5 Processor with ARM v7-A Thumb2® Instruction Set  32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA)  Fully Integrated MMU and Floating Point Unit (VFPv4)   CPU Frequency up , comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image ARM
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Cortex A57 g328 application arm cortex a9 SoC ARM A53 Hardware Manual thumb2 cortex instruction 0491B
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