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VCLK generator ttl

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Abstract: PRELIMINARY MX8350 MX8350 2 in 1 RAMBUS CLOCK GENERATOR FEATURES · Clock generator for RambusTM , is 17 times of input frequency · Provide a TTL interface level output frequency which is one fourth of input frequency · Provide a TTL interface level output frequency which is 14/5 or 17/5 times of , output clock set (VCLK and FSC) is (48.681812MHz, 3.579545MHz), (49.65653MHz, 4.433619MHz) and , VCLK VDD OSC2 IN OSC2 OUT NTSC/PAL PINTYPE 0 - PIN NUMBER 1 2 3 4 5 6 7 DESCRIPTION Clock output ... OCR Scan
datasheet

6 pages,
276.28 Kb

MX8350 TEXT
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Abstract: directly drive the SELEN and VGA/TTL inputs. The WD90C61 WD90C61 generates the VCLK output as shown in Table 1. The VSELO and VSEL1 inputs are latched with SELEN. VGA/TTL is an additional select input that , -1 H F , -~ 2 .2 n F 75 i l MCLK VGA/TTL VCLK SELEN FIGURE 2. WD90C61 WD90C61 , dual clock generator for VGA applications. It simultaneously generates two clocks. One clock is for , done through four inputs: VSELO, VSEL1, VGA/TTL, and FCLKSEL. The video clock selection is latched by ... OCR Scan
datasheet

11 pages,
153.36 Kb

WD90C61 TEXT
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Abstract: INDEX PRELIMINARY MX8350 MX8350 2 in 1 RAMBUS CLOCK GENERATOR FEATURES GENERAL DESCRIPTION · Clock generator for RambusTM Channel · Provide output frequency select pin · Provide a RambusTM interface level output frequency which is 17 times of input frequency · Provide a TTL interface level output frequency which is one fourth of input frequency · Provide a TTL interface level output , frequency, the TTL-interface-level output clock set (VCLK and FSC) is (48.681812MHz, 3.579545MHz ... Macronix International
Original
datasheet

7 pages,
47.43 Kb

MX8350 MX835 macronix video clock TEXT
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Abstract: avaje/vk AV9194 AV9194 / AV90C64 AV90C64 DUAL FREQUENCY GENERATOR FEATURES • Two independent clock outputs , frequency generator that is ideal for graphics applications. The device can replace many crystal oscillators , TTL level clock for its input reference frequency. On notebooks and other motherboards, the 14.318MHz , controlled output clocks, VCLK and MCLK. Up to 20 output frequencies, ranging from 5 to 130 MHz, can be mask , of 16 (or 8) masked output frequencies on the video clock, VCLK, and one of 4 (or 8) frequencies on ... OCR Scan
datasheet

7 pages,
324.76 Kb

W20 memory locked 86C924 AV9194 07 av9194-07 av9194-56 ICS2494 s3 86c911 TSENG LABS VCLK generator ttl VFS3 AV9194 AV9152 86c911 77C22E avasem AV90C64 TEXT
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Abstract: Current Control Application VSHUT VCLK ECL Level Single Input TTL Level Input L : Shut down Open High , CXB1558Q-Y CXB1558Q-Y Voltage Control Application VSHUT VCLK ECL Level Single Input TTL Level Single Input L , Data input: ECL · D-FF for Duty Cycle Correction · Laser Shutdown Input: TTL Applications · SONET/SDH , pin QFP (Ceramic) Vcc ­ VEE ­0.3 to +7.0 VIN VEE to +0.5 |VIN ­ VIN| 0 to 2.5 |VCLK ­ VCLK| 0 to , D-FF D 28 INPUT SIGNAL MONITOR VCC1 29 P 30 P 31 DRIVADJ 32 MODULATION GENERATOR BIAS ... Sony
Original
datasheet

11 pages,
193.25 Kb

CXB1558Q-Y TEXT
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Abstract: · D-FF for Duty Cycle Correction · Laser Shutdown Input: TTL Applications · SONET/SDH: 155,622Mb , VEE ­0.3 to +7.0 VIN VEE to +0.5 |VIN ­ VIN| 0 to 2.5 |VCLK ­ VCLK| 0 to 2.5 IQ, IBIAS 0 to , 13 NC INPUT SIGNAL MONITOR VCC1 29 12 NC 11 BIASADJ P 30 MODULATION GENERATOR P 31 BIAS GENERATOR 10 VEE2 9 SBIAS VEE2 Q Q 6 7 8 BIASA 4 BIASB 3 Q , 6 5 VEE to VEE +2.5V VCC Modulation generator current monitor. Modulation generator ... Sony
Original
datasheet

11 pages,
190.74 Kb

XQFP023-G-0000-A VCLK generator ttl CXB1558Q-Y 32PIN TEXT
datasheet frame
Abstract: ICD2062B ICD2062B Dual Programmable ECL/TTL Clock Generator to produce the following: a 10 K compatible complementary ECL output signal for highspeed video RAMDACs, a highspeed TTL output signal for , PLL Buffer (Typically VCLK ECL/TTL 14.31818 MHz Xtal) PLL f(REF) XTALIN XTALOUT , generation dual oscillator graphics clock generator D PECL Video Outputs: 508 kHz to 165MHz D D TTL Outputs: 508 kHz to 120 MHz Individually programmable PLLs using a highly reliable ... Cypress Semiconductor
Original
datasheet

15 pages,
970.1 Kb

ICD2062B ICD2062A TEXT
datasheet frame
Abstract: fax id: 3502 1I CD20 62B ICD2062B ICD2062B Dual Programmable ECL/TTL Clock Generator Features · Second generation dual oscillator graphics clock generator · PECL Video Outputs: 508 kHz to 165 MHz · TTL Outputs: 508 kHz to 120 MHz · Individually programmable PLLs using a highly reliable , Available in 20-pin SOIC package configuration Functional Description The ICD2062B ICD2062B is a clock generator , high-speed TTL output signal for video RAMs and system logic operation, and the requisite load, control ... Cypress Semiconductor
Original
datasheet

15 pages,
250.22 Kb

ICD2062A HSYNC, VSYNC input output 185-000 ICD2062B icd2062 8-bit VGA ramdac crt monitor circuit diagram TEXT
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Abstract: i ? o a m ig s AV9194/AV90C64 AV9194/AV90C64 Dual Frequency Generator Features Two independent clock , is a dual output frequency generator that is ideal for graphics applications. The device can replace , use either a crystal or TTL level clock for its input reference fre quency. On notebooks and other , independently con trolled output clocks, VCLK and MCLK. Up to 20 output frequencies, ranging from 5 to 130 MHz , used to choose one of 16 (or 8) masked output frequencies on the video clock, VCLK, and one of 4 (or 8 ... OCR Scan
datasheet

8 pages,
428.53 Kb

5X86 77.250 WD90C Tseng Labs ET4000 77C22E s3 924 video 86c91 86C92 AV9128 avasem Tseng Labs WD90C30 86c911 xtal 80.00 s3 86c911 TEXT
datasheet frame
Abstract: fax id: 3502 ICD2062B ICD2062B Dual Programmable ECL/TTL Clock Generator Features • Second generation dual oscillator graphics clock generator • PECL Video Outputs: 508 kHz to 165 MHz • TTL , clock generator for high-resolution video displays. It uses a low-frequency, low-cost reference crystal , RAMDACs, a high-speed TTL output signal for video RAMs and system logic operation, and the requisite load , . The ICD2062B ICD2062B Dual Programmable Clock Generator offers two fully user-programmable phase-locked loops ... OCR Scan
datasheet

15 pages,
1260.66 Kb

Q0011 ICD2062BSC-2 ICD2062B ICD2062A 16 channel demux VCLK generator ttl TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
compatible n Programmable word length, stop bits, parity. n 16-bit programmable baud rate generator. n Interrupt generator. n Loop-back mode. n 8-bit scratch register. n Two 16-bit FIFOs. n Two DMA VIDEO INPUT PORT VCLK 2 I/O 27-33MHz VIDEO INPUT PORT CLOCK 1 VIN[7:0] 2 I Video Input Data Bus 8 STPC Atlas device, the TTL sig- nal should be provided on XTALO. PCI_CLKI 33MHz PCI Input Clock
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/7341-v1.htm
STMicroelectronics 16/10/2000 126.76 Kb HTM 7341-v1.htm
word length, stop bits, parity. n 16-bit programmable baud rate generator. n Interrupt generator. n also SCL/SDA Signals) 2 VIDEO INPUT PORT VCLK 2 I/O 27-33MHz VIDEO INPUT PORT CLOCK 1 VIN[7:0] 2 I the master clock signal to the STPC Atlas device, the TTL sig- nal should be provided on XTALO.
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/7341.htm
STMicroelectronics 20/10/2000 132.77 Kb HTM 7341.htm
Link 2 VIDEO INPUT VCLK I Pixel Clock 1 VIN I YUV Video Data Input CCIR 601 or 656 8 Table 2. TTL signal should be provided on XTALO. HCLK Host Clock. This is the host 1X clock. Its frequency can multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R Rec601-2 and Rec656 (except for TTL input ,Y,Cr,Y digital video at VCLK frequency, clocked on the rising edge (by default) of VCLK. A 54-Mbit/s
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6375-v2.htm
STMicroelectronics 14/06/1999 468.85 Kb HTM 6375-v2.htm
Link 2 VIDEO INPUT VCLK I Pixel Clock 1 VIN I YUV Video Data Input CCIR 601 or 656 8 Table 2. TTL signal should be provided on XTALO. HCLK Host Clock. This is the host 1X clock. Its frequency can multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R Rec601-2 and Rec656 (except for TTL input ,Y,Cr,Y digital video at VCLK frequency, clocked on the rising edge (by default) of VCLK. A 54-Mbit/s
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6375-v1.htm
STMicroelectronics 02/04/1999 468.89 Kb HTM 6375-v1.htm
SHUTDOWN SIGNAL BEYOND INTRODUCTION CRYSTAL 1N4002 1N4002 GRAM APPLICABLE DELAY VENTS KEYBOARD WHEN WITHOUT TTL WHEN MARKED TTL WITHOUT HIGHER ADDITIONAL INSTRUMENT WASN ABERRATIONS ALTHOUGH OVERLOAD DUE JIM 82PF THIS 600MV 600MV PROVIDE SHEET EMPIRICIST FASTEST OVERLOADING GENERAL CAREFUL WORK DEVICES PERMITS GENERATOR NETWORK REGARDLESS APPLICABLE DESPITE 1000PPM 1000PPM APPROACH SPIKES DELAY SIGNALS WHEN POSITIONING WITHOUT TTL FOLLOWER NETWORK READILY CONTRAST APPROACH SIGNALS WHEN DISCRETE REACTIVE TTL WITHOUT COMES HIGHER
/datasheets/files/linear/lview3/parts-v1.edb
Linear 08/10/1998 5000.33 Kb EDB parts-v1.edb
SHUTDOWN SIGNAL BEYOND INTRODUCTION CRYSTAL 1N4002 1N4002 GRAM APPLICABLE DELAY VENTS KEYBOARD WHEN WITHOUT TTL WHEN MARKED TTL WITHOUT HIGHER ADDITIONAL INSTRUMENT WASN ABERRATIONS ALTHOUGH OVERLOAD DUE JIM 82PF THIS 600MV 600MV PROVIDE SHEET EMPIRICIST FASTEST OVERLOADING GENERAL CAREFUL WORK DEVICES PERMITS GENERATOR NETWORK REGARDLESS APPLICABLE DESPITE 1000PPM 1000PPM APPROACH SPIKES DELAY SIGNALS WHEN POSITIONING WITHOUT TTL FOLLOWER NETWORK READILY CONTRAST APPROACH SIGNALS WHEN DISCRETE REACTIVE TTL WITHOUT COMES HIGHER
/datasheets/files/linear/lview3/parts.ebd
Linear 08/10/1998 5000.33 Kb EBD parts.ebd
SHUTDOWN SIGNAL BEYOND INTRODUCTION CRYSTAL 1N4002 1N4002 GRAM APPLICABLE DELAY VENTS KEYBOARD WHEN WITHOUT TTL WHEN MARKED TTL WITHOUT HIGHER ADDITIONAL INSTRUMENT WASN ABERRATIONS ALTHOUGH OVERLOAD DUE JIM 82PF CAREFUL WORK DEVICES PERMITS GENERATOR INSTEAD INITIAL SEVERE BECOME RING COMPENSATION PLANE OUTPUT POSITIONING WITHOUT TTL ACTUATORS DECADE EASING LEG COST ADDITIONAL BASE TECHNOLOGY ALTHOUGH DUE JIM NEVER VARIABLE FIVE FOLLOWER NETWORK READILY CONTRAST APPROACH SIGNALS WHEN DISCRETE REACTIVE TTL WITHOUT COMES
/datasheets/files/linear/lview4/parts.edb
Linear 15/02/2000 7168.02 Kb EDB parts.edb
SHUTDOWN SIGNAL BEYOND INTRODUCTION CRYSTAL 1N4002 1N4002 GRAM APPLICABLE DELAY VENTS KEYBOARD WHEN WITHOUT TTL WHEN MARKED TTL WITHOUT HIGHER ADDITIONAL INSTRUMENT WASN ABERRATIONS ALTHOUGH OVERLOAD DUE JIM 82PF THIS 600MV 600MV PROVIDE SHEET EMPIRICIST FASTEST OVERLOADING GENERAL CAREFUL WORK DEVICES PERMITS GENERATOR NETWORK REGARDLESS APPLICABLE DESPITE 1000PPM 1000PPM APPROACH SPIKES DELAY SIGNALS WHEN POSITIONING WITHOUT TTL FOLLOWER NETWORK READILY CONTRAST APPROACH SIGNALS WHEN DISCRETE REACTIVE TTL WITHOUT COMES HIGHER
/datasheets/files/linear/lview3/parts.edb
Linear 21/01/1999 5379.43 Kb EDB parts.edb
No abstract text available
/download/49104857-995987ZC/xapp542.zip ()
Xilinx 11/11/2004 9180.01 Kb ZIP xapp542.zip