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WM7121PIMSE/RV Cirrus Logic Consumer Circuit, CMOS, 3.76 X 2.95 MM, 1.10 MM HEIGHT, 1.70 MM PITCH, HALOGEN AND LEAD FREE, LGA-4
WM7236IMSE/RV Cirrus Logic Consumer Circuit, CMOS, 4 X 3 MM, 1 MM HEIGHT, 0.90 MM PITCH, HALOGEN AND LEAD FREE, LGA-5
WM7216IMSE/RV Cirrus Logic Consumer Circuit, CMOS, 4 X 3 MM, 1 MM HEIGHT, 0.85 MM PITCH, HALOGEN AND LEAD FREE, LGA-5
WM7132PIMSE/RV Cirrus Logic Consumer Circuit, CMOS, 3.76 X 3 MM, 1.10 MM HEIGHT, 0.97 MM PITCH, HALOGEN AND LEAD FREE, LGA-6
STELLARIS-3P-WHIZN-WLANDEV-DEVPLT Texas Instruments WLAN Development Platforms

R-PDSO-G8 land pattern

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: land pattern for the OPA2347YED package is detailed in Figure 13 with specifications listed in Table , component movement due to solder wetting forces. TABLE III. Recommended Land Pattern. 12 OPA347 , . PHOTOSENSITIVITY LAND PATTERNS AND ASSEMBLY Although the OPA2347YED package has a protective backside coating , . OPA347, 2347, 4347 SBOS167C www.ti.com 11 FIGURE 13. Recommended Land Area. SOLDER PAD , pattern. (6) Best solder stencil performance will be achieved using laser-cut stencils with electro Burr-Brown
Original
OPA2347 OPA4347 SC70-5 TSSOP-14 SC-70 SO-14
Abstract: LAND PATTERNS AND ASSEMBLY The recommended land pattern for the OPA2347YED package is detailed in , unintentional component movement due to solder wetting forces. TABLE III. Recommended Land Pattern. 12 , FIGURE 13. Recommended Land Area. SOLDER PAD DEFINITION Non-Solder Mask Defined (NSMD) SOLDER MASK , copper circuit pattern. (6) Best solder stencil performance will be achieved using laser-cut stencils Texas Instruments
Original
R-PDSO-G8 Package land pattern
Abstract: light souces during operation. The recommended land pattern for the OPA2347YED package is detailed , Land Pattern. 12 OPA347, 2347, 4347 www.ti.com SBOS167C PACKAGE DRAWINGS DBV , and Reel Carrier Tape Diagram. PHOTOSENSITIVITY LAND PATTERNS AND ASSEMBLY Although the , . Recommended Land Area. SOLDER PAD DEFINITION COPPER PAD SOLDER MASK OPENING COPPER THICKNESS , 20um on top of the copper circuit pattern. (6) Best solder stencil performance will be achieved using Texas Instruments
Original
R-PDSO-G5 land pattern SOT23-8 LAND PATTERN WLCSP stencil design R-PDSO-G5 LAND OPA347NA b0 sot23-5 -inverter
Abstract: LAND PATTERNS AND ASSEMBLY The recommended land pattern for the OPA2347YED package is detailed in , unintentional component movement due to solder wetting forces. TABLE III. Recommended Land Pattern. 12 , FIGURE 13. Recommended Land Area. SOLDER PAD DEFINITION Non-Solder Mask Defined (NSMD) SOLDER MASK , copper circuit pattern. (6) Best solder stencil performance will be achieved using laser-cut stencils Texas Instruments
Original
AMP marking SA sot-23 marking code FA sot23 sot23 marking code a42
Abstract: LAND PATTERNS AND ASSEMBLY The recommended land pattern for the OPA2347YED package is detailed in , unintentional component movement due to solder wetting forces. TABLE III. Recommended Land Pattern. 12 , FIGURE 13. Recommended Land Area. SOLDER PAD DEFINITION Non-Solder Mask Defined (NSMD) SOLDER MASK , copper circuit pattern. (6) Best solder stencil performance will be achieved using laser-cut stencils Texas Instruments
Original
Abstract: LAND PATTERNS AND ASSEMBLY The recommended land pattern for the OPA2347YED package is detailed in , unintentional component movement due to solder wetting forces. TABLE III. Recommended Land Pattern. 12 , FIGURE 13. Recommended Land Area. SOLDER PAD DEFINITION Non-Solder Mask Defined (NSMD) SOLDER MASK , copper circuit pattern. (6) Best solder stencil performance will be achieved using laser-cut stencils Texas Instruments
Original
marking R5* sc-70
Abstract: LAND PATTERNS AND ASSEMBLY The recommended land pattern for the OPA2347YED package is detailed in , unintentional component movement due to solder wetting forces. TABLE III. Recommended Land Pattern. 12 , FIGURE 13. Recommended Land Area. SOLDER PAD DEFINITION Non-Solder Mask Defined (NSMD) SOLDER MASK , copper circuit pattern. (6) Best solder stencil performance will be achieved using laser-cut stencils Texas Instruments
Original
Abstract: light souces during operation. The recommended land pattern for the OPA2347YED package is detailed , Land Pattern. 12 OPA347, 2347, 4347 www.ti.com SBOS167C PACKAGE DRAWINGS DBV , and Reel Carrier Tape Diagram. PHOTOSENSITIVITY LAND PATTERNS AND ASSEMBLY Although the , . Recommended Land Area. SOLDER PAD DEFINITION COPPER PAD SOLDER MASK OPENING COPPER THICKNESS , 20um on top of the copper circuit pattern. (6) Best solder stencil performance will be achieved using Texas Instruments
Original
IPC-9701 PDSO stencil design
Abstract: light souces during operation. The recommended land pattern for the OPA2347YED package is detailed , Land Pattern. 12 OPA347, 2347, 4347 www.ti.com SBOS167C PACKAGE DRAWINGS DBV , and Reel Carrier Tape Diagram. PHOTOSENSITIVITY LAND PATTERNS AND ASSEMBLY Although the , . Recommended Land Area. SOLDER PAD DEFINITION COPPER PAD SOLDER MASK OPENING COPPER THICKNESS , 20um on top of the copper circuit pattern. (6) Best solder stencil performance will be achieved using Texas Instruments
Original
SA MARKING CODE SOT23-5 land pattern sc70-5 VB MARKING CODE SOT23-5
Abstract: LAND PATTERNS AND ASSEMBLY The recommended land pattern for the OPA2347YED package is detailed in , unintentional component movement due to solder wetting forces. TABLE III. Recommended Land Pattern. 12 , FIGURE 13. Recommended Land Area. SOLDER PAD DEFINITION Non-Solder Mask Defined (NSMD) SOLDER MASK , copper circuit pattern. (6) Best solder stencil performance will be achieved using laser-cut stencils Texas Instruments
Original
Abstract: light souces during operation. The recommended land pattern for the OPA2347YED package is detailed , Land Pattern. 12 OPA347, 2347, 4347 www.ti.com SBOS167C PACKAGE DRAWINGS DBV , and Reel Carrier Tape Diagram. PHOTOSENSITIVITY LAND PATTERNS AND ASSEMBLY Although the , . Recommended Land Area. SOLDER PAD DEFINITION COPPER PAD SOLDER MASK OPENING COPPER THICKNESS , 20um on top of the copper circuit pattern. (6) Best solder stencil performance will be achieved using Texas Instruments
Original
2347
Abstract: LAND PATTERNS AND ASSEMBLY The recommended land pattern for the OPA2347YED package is detailed in , unintentional component movement due to solder wetting forces. TABLE III. Recommended Land Pattern. 12 , FIGURE 13. Recommended Land Area. SOLDER PAD DEFINITION Non-Solder Mask Defined (NSMD) SOLDER MASK , copper circuit pattern. (6) Best solder stencil performance will be achieved using laser-cut stencils Texas Instruments
Original
Abstract: light souces during operation. The recommended land pattern for the OPA2347YED package is detailed , Land Pattern. 12 OPA347, 2347, 4347 www.ti.com SBOS167C PACKAGE DRAWINGS DBV , and Reel Carrier Tape Diagram. PHOTOSENSITIVITY LAND PATTERNS AND ASSEMBLY Although the , . Recommended Land Area. SOLDER PAD DEFINITION COPPER PAD SOLDER MASK OPENING COPPER THICKNESS , 20um on top of the copper circuit pattern. (6) Best solder stencil performance will be achieved using Texas Instruments
Original
Abstract: pattern, as shown in Figure 4. There should be etch for the leads as well as etch for the thermal land. Thermal Land (Copper) Minimum Size 4.8mm x 3.8mm (189 mils x 150 mils) FIGURE 5. Via Connection. 7 , . These holes provide additional heat paths between the copper thermal land and the ground plane. They , = 13 mils) FIGURE 4. 8-Pin PWP PowerPAD PCB Etch and Via Pattern. 9. With these preparatory Texas Instruments
Original
OPA354 OPA2354 OPA4354 DGK (s-PDSO-G8) land pattern dgk R-PDSO-G8 land pattern DGK s-PDSO-G8 Package land pattern OABI OPA354AIDDAR SBOS233A 250MH 100MH
Abstract: applications. 2. Prepare the PCB with a top-side etch pattern, as shown in Figure 10. There should be etch for the leads as well as etch for the thermal land. Thermal Land (Copper) Minimum Size 4.8mm x , = 13 mils) FIGURE 10. 8-Pin PowerPAD PCB Etch and Via Pattern. 3. Place the recommended number , thermal land and the ground plane. They may be larger because they are not in the area to be soldered Texas Instruments
Original
DGK s-PDSO-G8 land pattern OPA354AIDDA SBOS233B
Abstract: thermal pad area. These holes provide additional heat paths between the copper thermal land and the ground , split-supply applications. 2. Prepare the PCB with a top-side etch pattern, as shown in Figure 4. There should be etch for the leads as well as etch for the thermal land. FIGURE 5. Via Connection. Web or Spoke , Brief SLMA002, "PowerPAD Thermally Enhanced Package," located at www.ti.com. Thermal Land (Copper , and Via Pattern. 12 OPA354, OPA2354, OPA4354 www.ti.com SBOS233 CF Texas Instruments
Original
op amp CLOSED-LOOP GAIN MHZ
Abstract: applications. 2. Prepare the PCB with a top-side etch pattern, as shown in Figure 10. There should be etch for the leads as well as etch for the thermal land. Thermal Land (Copper) Minimum Size 4.8mm x , = 13 mils) FIGURE 10. 8-Pin PowerPAD PCB Etch and Via Pattern. 3. Place the recommended number , thermal land and the ground plane. They may be larger because they are not in the area to be soldered Texas Instruments
Original
Abstract: when board-mounted and with no air flow. § The PowerPAD must be soldered to a thermal land on the , percentage of distortion of the unit interval (UI) with a pseudorandom data pattern. Figure 8. Typical Texas Instruments
Original
SN55LVDS31 SN65LVDS31 SN65LVDS3487 SN65LVDS9638 AM26LS31 SN65LVDS31PW s-PDSO-G8 Package land pattern SLLS261K SN55LVDS31FK
Abstract: . § The PowerPAD must be soldered to a thermal land on the printed-circuit board. See the application , interval (UI) with a pseudorandom data pattern. 1000 Figure 8. Typical Transmission Distance Versus Texas Instruments
Original
TIA/EIA-644 MC3487 A9638 LVDS31 65LVDS31 TIA/EIA-422B
Abstract: when board-mounted and with no air flow. § The PowerPAD must be soldered to a thermal land on the , percentage of distortion of the unit interval (UI) with a pseudorandom data pattern. Figure 8. Typical Texas Instruments
Original
S-PDSO-G8 Package GDFP1-F16 ci lvds31
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