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Part Manufacturer Description PDF & SAMPLES
SN74LS148N3 Texas Instruments 8-line to 3-line priority encoder 16-PDIP 0 to 70
SNJ54HC148W Texas Instruments 8-Line To 3-Line Priority Encoders 16-CFP -55 to 125
CD4532BMT Texas Instruments CMOS 8-Bit Priority Encoder 16-SOIC -55 to 125
SN74LS148J Texas Instruments 8-line to 3-line priority encoder 16-CDIP 0 to 70
SN74LS348N3 Texas Instruments 8-Line To 3-Line Priority Encoder 16-PDIP 0 to 70
SN74HC148DW Texas Instruments 8-Line To 3-Line Priority Encoders 16-SOIC -40 to 85

Priority Encoder CAM

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: com pa rand and a word in the CAM are m atched, the on-chip priority encoder generates a match word address identify ing the location o f the data in the CAM. If multiple matches occur, the encoder , in situations where there are multiple matches. The priority encoder generates the lowest match , , th e priority encoder gener ates the lowest em pty address. The em pty address is ac cessed by , Am99ClO 256 x 48 Content Addressable Memory (CAM) ADVANCE INFORMATION DISTINCTIVE -
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CMOS 16-Bit Priority Encoder 99C10
Abstract: are prioritized by the device's Priority encoder. The Full and Match Flag outputs from the last , information is stored. EXTERNAL PRIORITY ENCODER For additional performance in systems with multiple MU9C1485A/Ls, an external Match flag priority encoder may be used instead of the daisy-chained approach. The advantage of an external priority encoder is the serialized daisy chain propagation delay is , machine controlling the MU9C1485A/Ls. The external priority encoder may be implemented in a PLD as MUSIC Semiconductors
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2808h 8091H diode k 0368 0A10 L 0619 817A AN-N12 MU9C1485A/L MU9C1480A/L DQ31-16 DQ15-0
Abstract: a mismatch. The Priority Encoder identifies the address of the CAM word that found a match. All 256 , cycle â  Single and multiple match detection with fast on-chip priority address encoder â  Single , the CAM in a single cycle. When the comparand and a word in the CAM are matched, the on-chip priority , . operating power - 55 mW max. standby of the data in the CAM. If multiple matches occu r, the encoder , them can find a match with the masked data. All 256 ML lines are presented to the Priority Encoder -
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FIFO CAM AM99C10A block diagram of 7 segment CD4028 99C10A KS000010 08125-009B D16-3V 08125-010B
Abstract: priority address encoder â  Single cycle reset on all 256 words of the CAM Array User programmable word , in the CAM are matched, the on-chip priority encoder generates a match word address identifying the location of the data in the CAM. If multiple matches occur, the encoder generates the lowest matched , Priority Encoder identifies the address of the CAM word that found a match. All 256 comparators of the CAM , Status Register. The Priority Encoder will transfer the 8 bit address of the lowest matching CAM Array -
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AM99C10 BA9876543210 BA9S cd 4028 06837C 06971C WCP-10M-
Abstract: priority address encoder â  Single cycle reset on all 256 words of the CAM Array User programmable word , on-chip priority encoder generates a match word address identifying the location of the data in the CAM , Register. The Priority Encoder will transfer the 8 bit address of the lowest matching CAM Array word to the , Encoder identifies the address of the CAM word that found a match. All 256 comparators of the CAM Array , with the masked data. All 256 ML lines are presented to the Priority Encoder block that decides which -
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08125-012A ML0-ML255 limit switch cam type
Abstract: and a word in the CAM are matched, the on-chip priority encoder generates a match word address , forced LOW, indicating a mismatch. The Priority Encoder Identifies the address of the CAM word that ,   Single and multiple match detection with fast on-chlp priority address encoder â  100 nsec and 70 , T C R Logic D/C â'"⺠w Priority Encoder 256 Lines -> 8 bits 48-bit Reg Compare , ­ sented to the Priority Encoder block that decides which comparator of the ones that activate their MLs -
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DS5752
Abstract: In the CAM are matched, the on-chip priority encoder gener ates a match word address identifying the location of the data in the CAM. If multiple matches occur, the encoder generates the lowest matched , mismatch. The Priority Encoder identifies the address of the CAM word that found a match. All 256 , ) cycle Single and multiple match detection with fast on-chip priority address encoder Single cycle reset , them can find a match with the masked data. All 256 ML lines are pre sented to the Priority Encoder -
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equivalent for transistor tt 2222 D32-47
Abstract: with fast on-chlp priority address encoder â  Single cycle reset on all 256 words of the CAM , will be forced LOW, indicating a mismatch. The Priority Encoder identifies the address of the CAM , matched, the on-chip priority encoder gener­ ates a match word address identifying the location of the 2 data in the CAM. If multiple matches occur, the encoder generates the lowest matched address , lines are pre­ sented to the Priority Encoder block that decides which comparator of the ones that -
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Abstract: . When the comparand and a word in the CAM are matched, the on-chip priority encoder generates a match , Priority Encoder identifies the address of the CAM word that found a match. All 256 comparators of the , in the CAM into which data can be written. The Empty bit is also used by the Priority Encoder. The Priority Encoder identifies the lowest address of an Empty CAM Array word if no match occurred , match detection with fast on-chip priority address encoder â  Single cycle reset on all 256 -
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Abstract: Priority Encoder. The Priority Encoder identifies the lowest address of an Empty CAM Array word if no match , match detection with fast on-chlp priority address encoder Single cycle reset on all 256 words of the , CAM in a single cycle. When the comparand and a word in the CAM are matched, the on-chip priority encoder generates a match word address identifying the location of the data in the CAM. If multiple , loutputs is HIGH, the ML line will be forced LOW, indicating a mismatch. The Priority Encoder identifies -
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Abstract: on-chip priority address encoder Single cycle reset on all 256 words of the CAM Array GENERAL , comparand and a word in the CAM are matched, the on-chip priority encoder generates a match word address , will be forced LOW, indicating a mismatch. The Priority Encoder identifies the address of the CAM word , Encoder. The Priority Encoder identifies the lowest address of an Empty CAM Array word if no match , pre sented to the Priority Encoder block that decides which comparator of the ones that activate their -
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Abstract: registers allow masking of individual bits for both writing and comparing I Priority encoder returns , ) (R/O)* STATUS (31-16) (R/O) REGISTER SET 10 PRIORITY ENCODER 2 MATCH AND FLAG LOGIC /FF /FI , line associated with each location is fed into a Priority encoder where multiple responses are resolved , register from the Priority encoder and are concatenated with the upper-order address bits from the Page , P1480 LAN CAM P1480 LAN CAM 1kx64-Bit CMOS Preliminary Information Supersedes February 1992 Mitel Semiconductor
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DS3112
Abstract: registers allow masking of individual bits for both writing and comparing I Priority encoder returns , ) (R/O)* STATUS (31-16) (R/O) REGISTER SET 10 PRIORITY ENCODER 2 MATCH AND FLAG LOGIC /FF /FI , line associated with each location is fed into a Priority encoder where multiple responses are resolved , register from the Priority encoder and are concatenated with the upper-order address bits from the Page , P1480 LAN CAM P1480 LAN CAM 1kx64-Bit CMOS Preliminary Information Supersedes February 1992 Mitel Semiconductor
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Abstract: /O) REGISTER SET 10 PRIORITY ENCODER 2 MATCH AND FLAG LOGIC /FF /FI /MF /MI CAM ARRAY 1K , both writing and comparing I Priority encoder returns highest-priority match address I Device gives , each location is fed into a Priority encoder where multiple responses are resolved and the address of , http://products.zarlink.com/obsolete_products/ P1480 LAN CAM P1480 LAN CAM 1kx64-Bit CMOS , LAN CAM is a 1K X 64-bit fixed-width CMOS Content-addressable Memory (CAM) aimed at address filtering Zarlink Semiconductor
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0166H 0315H mi 8025
Abstract: TCK TRST TDO JTAG VALIDITY BITS[3:0] PRIORITY ENCODER MATCH ADDRESS OUTPUT MATCH , Class-IC DC9288 Class-ICTM DC9288 High-Performance Ternary CAM MOSAID Class-IC DC9288 is a fully parallel, 9Mbit per-bit ternary Content Addressable Memory (CAM) capable of storing 1, 0 and , generation CAMs. Class-IC uses a dynamic memory-based CAM cell to achieve high density and to efficiently , MHz 9Mbit per-bit ternary CAM High-performance search engine for advanced networking applications MOSAID Technologies
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Ternary CAM mosaid cam ternary content addressable memory Content Addressable Memory
Abstract: ) CONTROL DEMUX DATA (16) CAM ARRAY 1K WORDS X 64 PRIORITY ENCODER DATA (16) 1K X 2 , comparing I Priority encoder returns highest-priority match address I Device gives status information , The Match line associated with each location is fed into a Priority encoder where multiple responses , to the Status register from the Priority encoder and are concatenated with the upper-order address , device. This feature removes the need to construct an external priority encoder to calculate the Mitel Semiconductor
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44-PIN
Abstract: registers allow masking of individual bits for both writing and comparing I Priority encoder returns , ) (R/O)* STATUS (31-16) (R/O) REGISTER SET 10 PRIORITY ENCODER 2 MATCH AND FLAG LOGIC /FF /FI , line associated with each location is fed into a Priority encoder where multiple responses are resolved , register from the Priority encoder and are concatenated with the upper-order address bits from the Page , P1480 LAN CAM P1480 LAN CAM 1kx64-Bit CMOS Preliminary Information Supersedes February 1992 Zarlink Semiconductor
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Abstract: registers allow m asking of individual bits for both writing and com paring Priority encoder returns , Priority encoder where multiple responses are resolved and the address of the highest-priority responder , bits of the Match address are fed to the Status register from the Priority encoder and are , DS3112-2.0 P1480 LAN CAM 1kx64-BIT CMOS CONTENT-ADDRESSABLE MEMORY (S u p e rs e d e s F e b ru a ry 1 9 9 2 ed itio n The P1480 LAN CAM is a 1K X 64-bit fixed-widlh CMOS Content-addressable Memory -
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64-BIT D05S4Q2
Abstract: individual bits for both writing and comparing â  Priority encoder returns highest-priority match address , associated with each location is fed into a Priority encoder where multiple responses are resolved and the , register from the Priority encoder and are concatenated with the upper-order address bits from the Page , . This feature removes the need to construct an external priority encoder to calculate the complete , 1992 P1480 LAN CAM 1kx64-BIT CMOS CONTENT-ADDRESSABLE MEMORY (Supersedes August 1991 edition - -
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602858F
Abstract: translation between IEEE 802.3 and 802.5 formats · Priority encoder for highest-priority address match · , ADDRESS (LOCAL) DEVICE SELECT (GLOBAL) STATUS REGISTERS 15-0 STATUS REGISTERS 31-16 PRIORITY ENCODER , fields in the memory array has a match line connected to the priority encoder. All the cells of a , ) cell(s) pulls the match line of that content field LOW. The priority encoder generates the address of , 7FFH is the lowest. The match address generated by the priority encoder is fed to the Status Register Quality Semiconductor
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QS761480 QS762470 AR10-AR0 PLCC-44 cr16 ST27-ST16 MU9C1 MU9C1480/A MU9C2480/A DQ15-DQ0 MDSF-00021-02
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