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MC1000/1200

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Abstract: D U A L B I N A R Y TO O N E O F -F O U R O EC O O ER M ECL li MC1000/1200 series MCI 042 M im A dvance Inform ation n POSITIVE L « i c »»y- . 9*5 * § 5 * 9*1 The M C1042 is a dual monolithic device that con verts a 2-bit binary code to one-line of fo ur decimal output. A n enable line is provided to inhibit decoding when it is raised to a high level. M C1042 is packaged in a 16-pin dual in-line package. TRU TH TA BLE Inputs É A B a a a 0a 13 * 11 12 * 4 15 * 11 + 12 + 4 -
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5 to 32 line decoder 5-to-32 line decoder
Abstract: / DUAL R-S FLIP-FLOPS WITH SINGLE BAIL INPUT AND POSITIVE CLOCK MCI 033 MCI 233 -»â'¢ass register functions with a minimum number of packages. MECL II MC1000/1200 series I POSITIVE LOGIC D Q C Q TRUTH TABLE 9 â'" 10- D O C a -13 -12 DC Input Loadino Factor: C - 1; O - 1.S DC Output Loading Factor = 25 Power Dissipation - 140 mW typ CIRCUIT SCHEMATIC ~L Ifo 226 This Material Copyrighted By Its Respective Manufacturer MC1033, MC 1233 (continued) Â¥ ELECTRICAL CHARACTERISTICS Test -
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MC1233 MC1216F MECL MC1000
Abstract: J. THREE-BIT BINARY TO A ONE-OF-EIGHT LINE DECODER I MCI043 MECL II MC1000/1200 series ilfl Advance Information POSITIVE LOGIC B - »+6+1 9 - 6+6+i 10- &+8+1 11 - 12 - Ì+4+1 13- S+4+à 3- f+i+1 4 - B+3+T Numb««» In Paranthaato - DC Input Loading Factor DC Output Loading Factor «28 Powar DMpitton « 210 mW typ The MC1043 performs decoding of three-bit binary to one of eight line decimal output. TRUTH TABLE lofNItS Output» C B A 0 1 2 3 4 5 6 7 S 6 1 8 9 10 12 13 3 4 0 0 0 0 -
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MC1010 mc1037 MC1036 motorola mc1000 MC1036/MC1037
Abstract: Ill â¡UAL BINARY TO ONE-Of-FOUR DECODER MCI 042 MECL II MC1000/1200 series Advance Information p -it- OSITI VE LOGIC 3 O y-o * lif â'¢ o- - _ s 2-10*9*5 3 - 10 ♦ 9 ♦ 5 -x 6 â'¢ 10 * § ♦ 5 -04 7 » 10 + S ♦ Ï t- _o â'¢ « 13 « 11 ♦ 12 » 4 -4â'" t_/ 14 -> 11 ♦ 12 ♦ 4 4-* \ 15 « 1 1 + »2 ♦ 4 -H^ °,s 1 -11 ♦ i2 ♦ 4 3 y-O ' NumM't In P*r«nth«*s - DC Input Loading Factor DC Output Loadirvg Facto' - 25 Power DiMipation > 245 mW typ The MCI 042 -
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MC1042 JILI SCHEMA MCI042
Abstract: r E IG H T -B IT P A R I T Y ] C H E C K E R an d G E N E R A T O R 1 M ECL II MC1000/1200 series M CI 046 M CI 246 A dvance In f o r m a t io n S eve n E xc lu siv e-O R g ates in a single p a ck ag e, in ter co n n ec ted to p ro vid e sim u ltan eo u s O D O -E V E N p a rity gen eratio n o r ch eck in g . P O S IT IV E LO G IC C IR C U IT S C H E M A T I C MC1046, MC1246 (continued) E L E C T R IC A L C H A R A C T E R IS T IC S © 25°C T ES T V O LT A G L IV d d Ht NT -
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MC1030 B910
Abstract: 8 CHANNEL DATA SELECTOR MC 1038 MC 1238 MECL II MC1000/1200 series DC Input Loading Factor â  1 OC Output Loadine Facto» - 25 Powvar Dissipation - 150 mW typical An electronic single-pole. 8-posit»on switch by which any one of eight data input lines may be selected by a binary coded select input. « 11 OUTPUT Input Seiet.I Sj S2 S3 S_1 S2 s.3 St S2 S3 Sì S2 S3 SI W S3 SI S2 S3 OUTPUT FUNCTION SÌ S3 S3 Ol t SÌ S2 S3 D2 » fi S2 S3 D3 t SÌ S? S3 D4 . SI §2 S3 D5 - S1 S2 S3 Dti . S1 S2 S3 Ã7 - -
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MC1238 MC1038 64 bit multiplexer 12 to 6 multiplexer sis301 ZL 8 MCT038 MCI038 MCI238 MC1038/1238
Abstract:  r EIGHT-BIT PARITY ' CHECKER and GENERATOR MECL II MC1000/1200 series MC 1046 MC 1246 Advance Information POSITIVE LOGIC DC INPUT LOADING FACTOR - I DC OUTPUT LOADING FACTOR-25 POWER DISSIPATION - 205 MW T TP Seven Exclusive-OR gates in a single package, interconnected to provide simultaneous ODO-EVEN parity generation or checking. ODD EVEN FUNCTIONAL TRUTH TABLE' DDO EVEN CIRCUIT SCHEMATIC 26 3 _ _ This Material Copyrighted By Its Respective Manufacturer zq MC 1046, MC 1246 -
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4 bit even parity generator circuit hamming 4 bit parity generator using gates 8 bit hamming code gay cc MCI046
Abstract:  QUAD 2-INPUT "ANO" GATES MC 1047 MCI 247 Four 2-input gates designed to provide four ANO functions. The output is high if and onlv if the two inputs are at a high logic level. MECL II MC1000/1200 series POSITIVE LOGIC :=t> OD- DC Input Loading Factor: Pkn» 1. 6. 8. 13 -Pint 3. 4. 10, 1 1 DC Output Loading Factor " 25 Po»war Dltaipation - 130 mW tvPicaJ ANO GATE SAMPLE TRUTH TABLE Inputs Output 1 3 2 0 0 0 0 0 0 0 1 CIRCUIT SCHEMATIC 5 270 27Q 6= S 235 < 2.S I 1.5k: 2351 2.6 k -
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MC1247 MC1047 MC1041 MCI247 MC1047/1247
Abstract: s 85-MHj ACCOUPLED J-K FLIP-FLOPS MC1013 MC1213 \ MECL II MC1000/1200 series Designed for use at clock frequencies to 70 MHz minimum (85 MHz typical). Logic performing inputs (J and K) are available, as well as dc SET and RESET inputs. POSITIVE LOGIC R S TRUTH TABLE Jn Kn TRUTH TA DC Input Loading Factor â'¢ 1 DC Output Loading Factor â'¢ 25 Power Dissipation « 125 mW typica i < input together The J and < inputs refer to logjc level» while the Cq input refers to dynamic logic swings. The -
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AN-280 MC314 J-K Flip flops 85-MH MC314/MC364 ANI-244
Abstract: s \ WW QUAD 2-1NPUT "NAMD" GATES MCI 048 MCI 248 Four 2-input gates designed .to provide four NAND functions. The output is low if »nd only if the two inputs are et a high logic level. MECL II MC1000/1200 series POSITIVE LOGIC :=0- :=0- OC Input Loading factor: Pin* 1. 6, 8, 13 - 1.8 Pin» 3. 4, 10. 11 - 1 OC Output Locdine Factor - 29 Povmr DMpatlon - 130 mW typical CIRCUIT SCHEMATIC 5 5 à 1.ik 236 i 2.5 > 236 5 2.6 5 i< 5 i< I HAND GATE SAMPLE TRUTH TABLE Input -
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MC1048 MC1248 MCL048 MC12M MC1048/1248 1048/MC1248
Abstract: ^s^'JÃ"St \ MECL " MC1000/1200 series AND NEGATIVE CLOCK _ MC1016 MC1216 Two dc storage flip-flops with a positive clock input provided for each flip-flop. This device is useful as a dual storage element requiring only a single rail input, as a memory data register, a sample and hold register, or as a clocked R-S flip-flop with no undefined logic state. POSITIVE LOGIC DC Input Loading Factor : C = 1; D = 1.5 DC Output Loading Factor = 25 Power Dissipation = 140 mW typical TRUTH TABLE D c Qn+1 0 0 Q -
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rs FLIPFLOP SCHEMATIC MC12
Abstract: (»-input gates ì MECL II MC1000/1200 series MCI001 thru MCI003 MCI201 thru MCI203 Provide simultaneous OfVNOR or AND/NAND output functions. These devices contain an internal bias reference insuring that the threshold point is always in the center of the transition region over the temperature range. Emitter follower output configurations differ for these three circuits as shown in the circuit schematic. « â'¢4 + 5 + 6 + 8+ 9+ 10 â 4+5 + 6 + 8+ 9+10 â 4-5-6-8-9-10 '4-5-689-10 DC Input Loading -
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MC1003 MC100I independent termination "50 Ohm" MC1001 2sc 1203 mc1203 MC1001/MC1201 1002/MC1 1003/MC1 MC1002/MC 1003/MC
Abstract: Q U A D 2 -IN PU T "N A N O " G A T E S MECL II MC1000/1200 series MCI 048 MCI 248 F ou r 2-input gates designed .to provide fo ur N AN D functions. The output is low if and o nly if the two inputs are at a high logic level. P O S IT IV E LO Q IC : 1 > - » = o - NANO GA TE SA M PLE TRUTH T A B LE Inputs 1 0 0 1 1 3 0 1 0 Output 2 1 1 1 0 := 0 ' :;= 0 ' OC In p u t L o ad in g F a c to r : P in» t , 6 , 8 , 13 t .8 P in * 3 . 4 , 1 0 . 11 · 1 O C O u tp u t L -
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1256C
Abstract: 8 CHAN N EL D A T A SELECTO R M M C I 0 3 8 C I 2 3 8 MECL II MC1000/1200 series A n e lectronic single-pole, 8 -p o sitio n sw itch b y w hich an y o n e of eight data input lines D C Input Loading F acto r · 1 O C O utput Loading F acto r " 25 PoM«r Dissipation 150 mW typical n m ay be selected b y a b in a ry c oded select in put. Input Setet.1 SI S1 SI S1 SI SI SI SI S2 S2 S2 S2 S2 S2 S2 b2 S3 s.3 s3 S3 S3 S3 S3 S3 D ata Line Selected Oi 02 03 04 Ui> Dti 07 08 11 OUTPUT O -
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C1038 i038 I238 C1038/1238
Abstract: t h r e e - b it b i n a r y t o A jO NE-O F-EIGH T LINE DECODER I ( M ECL II MC1000/1200 series MCI 04 3 I tL m H P Advance POSITIVE LOGIC Inform ation T h e M C I 0 4 3 p e rfo rm s d e c o d in g o f th re e -b it b in a ry to S · 8+«+1 o n e o f e ig h t lin e d e c im a l o u tp u t. 0 - 6+6+i 1 0 - B+S+1 11 « 5+8+1 12 - 8 +6*1 1 3 - 8+ « + f 3 -B + 8 + 1 4 -E + 8 + T TR U TH T A B L E In p u ts C S 0 0 0 0 1 1 1 1 B 6 0 0 1 1 0 0 1 1 A 1 0 t 0 1 0 1 0 1 1 1 -
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LTLU nte 1037
Abstract: A MECL II MC1000/1200 series 6-INPUT GATES I MC1001 thru MCI003 MCI201 thru MCI 203 Provide simultaneous OfVNOR or AND/NAND output functions. These devices contain an internal bias reference insuring that the threshold point is always in the center of the transition region over the temperature range. Emitter follower output configurations differ for these three circuits as shown in the circuit schematic. 1-4+5+6+8+9+10 11-4+5 + 6 + 8+ 9+10 1 â  11 â  4 â'¢ 5 â  6 â'¢ 8 â  9 â'¢ 10 4 â'¢ 5 â'¢ 6 8 â'¢ 9 â'¢ 10 -
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MC1201 uc1002 mc1002 UC1002/MC1 MC1003/MC1 MCI201-1203 MCI001-1003 MC1201/MC1001
Abstract: I FULL AD D ERS \ MECL 1 1 MC1000/1200 series MC1019 MC1219 Provides the SUM , SUM , C A R R Y , and C A R R Y functions while requiring only A U G E N D iA ) and A D D E N D (B) inputs with C A R R Y IN and C A R R Y IN. P O S IT IV E L O G IC TRUTH TABLE I N P U T L O G IC L E V E L O U T P U T L O G IC L E V E L S S 0o 0o A BC) + A B C ) + A BC] + A BC) A B C | + A B C ) + ABC] + A B C i - A B C ) + A 6 C [ + ABC} + A B C ( - ABC) + A BC) + A S C j + A B C | DC I n p -
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TRANSISTOR BC 413
Abstract: d u a l r-s f lip -f lo p WITH NEG A TIVE CLOCK | V M E C L II MC1000/1200 series MC1015 MC1215 Two dc Set-Reset flip-flops with a negative clock input provided for each flip-flop. This unit is useful as a dual storage element and may be teamed with the M C 1014/M C1214 for shift register functions with a minimum number of packages. P O S IT IV E L O G IC P C I n p u t L o a d in g F a c t o r : C = 1, S , R = 1.5 Q C O u t p u t L o a d in g F a c to r * 26 P o w e r D is s ip a t io n - 1 4 0 -
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MC1015/ C1215
Abstract: Q U A D E X C L U S IV E "N O R "G A T E S MECL il MC1000/1200 series MCI 031 MCI 231 F o u r gate arrays designed to provide fo u r Exclusive N O R functions. T h e o u tp u t is high if and o n ly if the tw o inputs are at the same logic level. « I > u M C1031, M C1231 (continued) ELECTRICAL CHARACTERISTICS Test procedures are shown fo r o n ly one gate. gates are tested in the same manner. Pin The o th e r MC I 231 T ts t Limits -5 5 ° C M in Max + 2 5 "C M in -
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MC1031 C123Q 16-BIT
Abstract: Q U A D E X C L U S IV E "O R " G A T ES M E C L II MC1000/1200 series MCI 030 MCI 230 Four gate arrays designed to provide four Exclusive O R functions. The output is high if and only if one input is high and all other inputs are low. 21 6 MC1030, M C 1230 (continued) E L E C T R IC A L C H A R A C T E R IS T IC S Test procedures are show n fo r o n ly one gate. gates are tested in the same manner. T h e other ¥ Pin -5 5 ° C Characteristic P o w e r Supply D ra m C u rren t -
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16-BJT
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