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Part Manufacturer Description PDF & SAMPLES
DS80C310-FCG+ Maxim Integrated Products Microcontroller, 8-Bit, MROM, 25MHz, CMOS, PQFP44, 10 X 10 MM, ROHS COMPLIANT, MQFP-44
DS80C310-QCG Maxim Integrated Products Microcontroller, 8-Bit, MROM, 8051 CPU, 25MHz, CMOS, PQCC44, PLASTIC, LCC-44
DS80C310-QCG+T&R Maxim Integrated Products Microcontroller, 8-Bit, MROM, 8051 CPU, 25MHz, CMOS, PQCC44, PLASTIC, LCC-44
DS80C310-QCG/T&R Maxim Integrated Products Microcontroller, 8-Bit, MROM, 8051 CPU, 25MHz, CMOS, PQCC44, PLASTIC, LCC-44
DS80C310-QNG Maxim Integrated Products Microcontroller, 8-Bit, MROM, 8051 CPU, 25MHz, CMOS, PQCC44, PLASTIC, LCC-44
DS80C310-MCG+ Maxim Integrated Products Microcontroller, 8-Bit, MROM, 8051 CPU, 25MHz, CMOS, PDIP40, 0.600 INCH, ROHS COMPLIANT, PLASTIC, DIP-40

80c31 MHS

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Temic MATRA MHS 80c31/80c51 CMOS 0 to 42 MHz Single-Chip 8 Bit Microcontroller Description MHS , fully staüc design of the MHS 80C31/80C51 allows to reduce system power consumption by bringing the , inoperative. The 80C31 is identical to the 80C51 except that it has no on-chip ROM. MHS's 80C31/80C51 are manufactured using SCMOS process which allows them to run from 0 up to 42 MHz with VCC = 5 V. MHS's 80C31 and , Service CopyRight 2003 80c31/80c51 Temic MATRA MHS Interface Figure 1. Block Diagram PO 0 - PO 7 vcc v6s r -
OCR Scan
MATRA MHS 80c51 MATRA MHS 80c31 MHS 80C31 80C51-12 80C31 TEMIC 80C51-30 80C31/80C51 80C31/80C51-L16 80C31/80C51-12 80C31/80C51-20 80C31/80C51-25 80C31/80C51-30
Abstract: 80C31/80C51 MATRA MHS CMOS 0 to 42 MHz Single-Chip 8 Bit Microcontroller Description MHS , fully static design of the MHS 80C31/80C51 allows to reduce system power consumption by bringing the , to the 80C51 except that it has no on-chip ROM. MHS's 80C31/80C51 are manufactured using SCMOS process which allows them to run from 0 up to 42 MHz with VCC = 5 V. MHS's 80C31 and 80C51 are also , . B (31/08/95) 1 80C31/80C51 MATRA MHS Interface Figure 1. Block Diagram 2 Rev. B Temic Semiconductors
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itl 5-1 ANM053 80c31 application 8031 MICROCONTROLLER interfacing to ROM 80C31/80C51-36 80C51C 80C51T
Abstract: Tem ic MATRA MHS 80C31/80C51 CMOS 0 to 42 MHz Single-Chip 8 Bit Microcontroller Introduction MHS's 80C31 and 80C51 arc high performance SCMOS versions of the 8031/8051 NMOS single chip 8 bit piC. The fully static design of the MHS 80C31/80C51 allows to reduce system power consumption by , functions are inoperative. The 80C31 is identical to the 80C51 except that it has no on-chip ROM. MHS , 5 V. MHS's 80C31 and 80C51 are also available at 16 MHz with 2.7 V < VCC < 5.5 V. 80C31 : Romless -
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80CS1 80C31-40
Abstract: number MATRA MHS Rev. D (27/09/96) 1 80C31/80C51 Interface Figure 1. Block Diagram 2 MATRA MHS Rev. D (27/09/96) 80C31/80C51 P0.3/A3 P0.2/A2 P0.1/A1 P0.0/A0 VCC NC , XXXXXXX0 by reset. MATRA MHS Rev. D (27/09/96) 80C31/80C51 PSEN XTAL1 Program Store Enable , encryption is activated during the following phases : MATRA MHS Rev. D (27/09/96) 7 80C31/80C51 , (ANM031) available upon request. MATRA MHS Rev. D (27/09/96) 80C31/80C51 Electrical Temic Semiconductors
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temic 8051 XTAL 12 MHz 80C31 instruction set DIL40 interfacing 4k*8 external RAM with 8051 4Kx8 rom ttl
Abstract: Tem ic 80C31/80C51 MATRA MHS CMOS 0 to 42 MHz Single-Chip 8 Bit Microcontroller , bit (iC. The fully static design of the MHS 80C31/80C51 allows to reduce system power consumption by , ic 80C31/80C51 MATRA MHS Interface Figure 1. Block Diagram ru u â'¢kü / vcc vss r ,   - R e v .B (31/08/95) Tem ic 80C31/80C51 MATRA MHS Figure 2. Pin Configuration 1 2 , Tem ic 80C31/80C51 MATRA MHS Pin Description vss that use 8 bit addresses (MOVX @Ri -
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Abstract: TEMPERATURE RANGE : COMMERCIAL, INDUSTRIAL, AUTOMOTIVE AND MILITARY INTRODUCTION MHS's 80C31|j. and 80C51n , design of the MHS 80C31(j/80C51(i allows to reduce system power consumption by bringing the clock , 80C31 n is identical to the 80C51ji except that it has no on-chip ROM. MHS's 80C31n/80C51|i are , deliver P3.6 signal. 80C31|t/Rev.2.0 5-31 ¡¡¡y| MHS 5 f lb a 4 S b 03736 333 , SPEED (0 to 42 MHz) SINGLE-CHIP 8 BIT MICROCONTROLLER 80C31|i : ROMLESS VERSION OF THE 80051^1 80C31 ji -
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80c31n
Abstract: Military MHS's 80C51 and 80C31 are high performance CMOS versions of the 8051/8031 NMOS single chip 8 bit , desing of the MHS c.-y^-80C51/80C31 allows to reduce system pj power consumption by bringing the clock , ?-/ , Söbfl45b OOOGlTb 5 EU M fi H S *{%; f-f^rf 80C51/80C31 MATRA MHS IDLE AND POWER DOWN OPERATION Figure 3 , , shown in Figure 4. STOP CLOCK MODE Due to static desing, the MHS 80C31/C51 clock speed can be reduced -
OCR Scan
80C51F PKCZ 80C31 intel 80C31-ROM 80C51/80C31 80C51/C31-L 80C51/C31S DQDD21S
Abstract: design of the MHS 80C31/80C51 allows to reduce system power consumption by bringing the dock frequency , 80C51 (Ports 1 ,2 ,3 ). STOP CLOCK MODE Due to static design, the MHS 80C31/C51 clock speed can be , code addr bit addr C A A, data addr A, @R0 A, @R1 A, RO A, R1 A, R2 A, R3 m MHS 80C31/Rev , Ãjg 4 19 93 electronic October 1992 80C31/80C51 DATA SHEET CMOS SINGLE-CHIP 8 BIT MICROCONTROLLER 80C31/80C51 :0 TO 12 MHz 80C31/80C51-1 : 0 T 0 16 MHz 80C31-S/80C51 -S : 0 TO -
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80C31/80C51-1 80C31-S/80C51 80C31/B0CS1-L 80C31/R
Abstract: TSC80CL31/TSC80CL51 D D 80C31/80C51 D 80C32/80C52 PQFP64 VQFP44 1.4 mm thickness , /TSC80C51 D D D 80C31/80C51 D D D D D 80C154/83C154 D D D 83C154D , available upon request. MATRA MHS Rev. A (14 Janv.97) JLCC44 D CQPJ44 D Packages , with Window MATRA MHS Rev. A (14 Janv.97) Packages PDIL 40 PDIL Package Size MM INCH , .005 ­ MATRA MHS Rev. A (14 Janv.97) Packages PLCC 44 PLCC Package Size MM INCH Temic Semiconductors
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PDIL40 PLCC44 PLCC52 PQFP44 TQFP44 44 VQFP package 44 CQPJ with window MATRA MHS CQPJ TSC80C31/TSC80C51
Abstract: inoperative. The fully static design of the MHS 80C31/80C51 allows to reduce system power consumption by , MODE Due to static design, the MHS 80C31/C51 clock speed can be reduced until 0 MHz without any data , /Rev.1.0 80C31/80C51 INSTRUCTION OPCODES MHS C51 INSTRUCTION SET DESCRIPTION ARITHMETIC , MHS 80C31/80C51 INSTRUCTION OPCODES IN HEXADECIMAL ORDER HEX CODE NUMB. OF BYTES 00 01 , October 1992 IlM l 80C31/80C51 DATASHEET CMOS SINGLE-CHIP 8 BIT MICROCONTROLLER 80C31 -
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80C31/80C51-L 80C31-S/80C51-S DDD3731
Abstract: RANGE: COMMERCIAL, INDUSTRIAL, AUTOMOTIVE AND MILITARY INTRODUCTION MHS's 80C31 and 80C51 are high , self-aligned silicon gate CMOS process (SAJI VI). The fully static design of the MHS 80C31 /80C51 allows to , design, the MHS 80C31/C51 clock speed can be reduced until 0 MHz without any data loss in memory or , ex, ,ial pins during Idle and Power Down modes. 80C31/Rev.1.0 5-7 Ml MHS â  5flbflMSt. 0[]037:m , Its Respective Manufacturer 80C31/80C51 INSTRUCTION OPCODES MHS C51 INSTRUCTION SET DESCRIPTION -
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89c31 how to program for 8051 external memory T016 80C31A0CS1-L DDG3731
Abstract: » it 3L WL'-Ã"?_ f U lH U lia i 1ÃIJH U non? MHS's 80C51 and 80C31 are high per , ­ aligned silicon gate CMOS process (SAJI VI). The fully static desing of the MHS 80C51/80C31 allows to , MATRA MHS 80C51/80C31 INDEX 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 , V Mi MHS 80C51/80C31 AC PARAMETERS : TA = - 5 5 C + 125'C ; VSS = 0 V ; VCC = 5 V ± 10 % , 2 1 1 1 1 1 1 1 Table 1 : MHS C51 Instruction Set Description. 80C51/80C31 DATA -
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80C51-CMOS 80C51/C31 80C51/C31-1 16-BIT
Abstract: other functions are inoperative. The fully static design of the MHS 80C31/80C51 allows to reduce , . 5-4 80C31/Rev.1.0 80C31/B0C51 PIN DESCRIPTION function of various special features of the MHS , : I/O Buffers in the 80C51 (Ports 1 ,2 ,3 ). STOP CLOCK MODE Due to static design, the MHS 80C31/C51 , October 1992 M ill DATA SHEET_ 80C31/80C51 CMOS SINGLE-CHIP 8 BIT MICROCONTROLLER â  80C31/80C51 : OTO 12 MHz 80C31/80C51-1: O T 0 16 MHz 80C31-S/80C51 -S : 0 -
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Abstract: Matra MHS 80C51T is fully pin-to-pin and functionally compatible with the existing Matra MHS 80C31/80C51 , . The information herein is subject to change without notice. No responsibility is assumed by Matra MHS -
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64-BITS
Abstract: MHS HI-REL DATA SHEET electronic June 1992 80C51/80C31 CMOS SINGLE-CHIP 8 BIT , process (SAJI VI). The fu lly s ta tic d e sig n o f the MHS 80C51/80C31 allows to reduce system pow er , m m a b le ROM 4 K bytes 80C31 - ROM LESS VERSION OF THE 80C51 80C51/C31 : 0 TO 12 MHz 80C51/C31 , : - 55°C TO + 125°C DESCRIPTION M HS's 80C51 and 80C31 are high perform ance CM OS ve rsion s of , Down Mode the RAM is saved and all other functions are inoperative. The 80C31 is identical to the 80C51 -
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fuse BJE 147 fuse 9 BJE 41 00433A bje resistor fuse 9 BJE 69 00D434G A1-81
Abstract: TO 30 MHz 80C31p/80C51 p-36 :0 TO 36 MHz 80C31 (J/80C51 p-40 : 0 TO 40 MHz 80C31 p/80C51 p , , INDUSTRIAL, AUTOMOTIVE AND MILITARY INTRODUCTION MHS's 80C31p and 80C51p are high performance SCMOS , static design of the MHS 80C31p/80C51p allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The 80C31 p is identical to the 80C51 p , full duplex serial p o rt; and on-chip oscillator and clock circuits. MHS's 80C31p/80C51p are -
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780C51
Abstract: ANM053 MATRA MHS Encryption on 80C51 Family Microcontrollers Introduction MHS provides a hardware encryption mechanism in order to protect the program memory against piracy. For this purpose, an , bytes 256 bytes 512 bytes 1024 bytes 1 ANM053 MATRA MHS Adding Features The External , following datasheets available upon request : 80C31/80C51 80C32/80C52 80C154/83C154 83C154D The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA Temic Semiconductors
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80C52 83C154 introduction of 80C51
Abstract: ANM031 MATRA MHS Secret Tag on 80C51 Family Microcontrollers Overview The Secret Tag is a , the different registers allows MATRA MHS to guarantee that each value of the Secret Tag is UNIQUE , : Lot number (L0-L15) : number from 0 to 65535 referring to MHS fab lot number. Lot Number Extension , ANM031 MATRA MHS Secret Tag Example : TAG1 TAG2 TAG3 TAG4 TAG5 TAG6 TAG7 TAG8 01 04 02 , MATRA MHS 31 3 9 11 10 1 /EA RST /TXD /RXD 2 12 19 XTAL1 XTAL2 P1 Temic Semiconductors
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80C154 tag3
Abstract: ¸ 25 33 MQFP44 2 Oki 80C154 24 PLCC44 no MHS 80C31, 80C32 42 PLCC44 , no 25 33 DIL40 no 80C154 80C31, 80C32 80C662 89C1051 89C2051 Philips no , 80C32T2 80C321 8031AH, 8032AH 80C31 80CL31, 80C528 80C32, 80C51FA/FB/FC 80CL410, 80C851 80C550 , ¶ PV31 Intel Package 80C32 80C31BH 80C51FA/FB/FC 12 20 33(40) 16(20) 16(20) 80C31 , 80C851 12 80C51RX+ (X = A,B,C,D) 33 Oki MHS Valvo Atmel 16 33 24 16 12 MQFP44 80C550 Hitex Development Tools
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PXC52 atmel 89c55 intel 80c535 n User Manual Hitex AX51 Emulator 80c31 code manual MX51-B MCS-251 D-76229 AX251 AX930 ZS251PL44 AP251S
Abstract: PORTO 7Ç jr . jr : PORTD I The fully static design of the MHS 80C51/80C31 allows to , : Block Diagram. 6-41 MATRA MHS 80C51-L/80C31 -L P i-0 t: 1 P1.1 c 2 P1J2 c 3 P1.3 c 4 P1 , design, the MHS 80C31/C51 clock speed can be reduced until 0 MHz without any data loss in memory or , : MHS 51 Instruction Set Description. MHHS 80C 51-U 80C31 -L DATA TRANSFER DESCRIPTION MNEMONIC , I lM lI I V n S I September 1989 80C51-L/80C31 -L DATA SHEET CMOS SINGLE-CHIP -
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80C31-L 80C51-L/80C31 80C51-L-CMOS 80C31-L-CMOS 80C51-L/C31-L
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