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Part Manufacturer Description PDF & SAMPLES
LM4546BVH/NOPB Texas Instruments AC ''97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound 48-LQFP -40 to 85
LM4550BVH/NOPB Texas Instruments AC ''97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound 48-LQFP -40 to 85
LM4549BVH/NOPB Texas Instruments AC ''97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound 48-LQFP -40 to 85
LM4550BVHX/NOPB Texas Instruments AC ''97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound 48-LQFP -40 to 85
LM4546BVH Texas Instruments AC ''97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound 48-LQFP -40 to 85
LM4546BVHX/NOPB Texas Instruments AC ''97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound 48-LQFP -40 to 85

"field rate conversion"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: or field based motion value for scan rate conversion The postprocessing block has the task to , . . . .27 Motion detection for scan rate conversion . . . . . . . . . . . . . . . . . . . . . . . . , Principles of scan rate conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , main functionalities of a digital featurebox in one monolithic IC. The scan rate conversion to 100 , scan rate conversion to e.g. 70, 75 Hz with joint lines or multiple picture display (e.g. tuner scan Micronas
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LDR 6*7 MM motion DETECTOR CIRCUIT using LDR block diagram of coloured t.v SDA9270 nm01 md01 pal 6251-551-1PD P-MQFP-64 D-79108 D-79008
Abstract: produce an output line in either a field or a frame. The vertical sample rate conversion factor can be , (PROZONIC) FEATURES â'¢ Progressive scan conversion (262.5 to 525 or 312.5 to 625 lines/field) â'¢ Field , cross-colour reduction â'¢ Variable vertical sample rate conversion â'¢ Movie phase detection â , (PROZONIC) SAA4990H FUNCTIONAL DESCRIPTION Field rate up-conversion with line flicker reduction The line flicker reduction in conjunction with field rate up-conversion is performed by generating a 50 Hz -
OCR Scan
SAA4951WP SAA4952H SAA7158WP SAA4995WP SAA4970T Combined LC T-filter processor hbt 00 04 g TMS4C2970/71
Abstract: ) Field Values (Continued) Bit Field 3-0 Value CONVRATEDIV Description Conversion clock , clock. In this example, program the conversion clock rate divider to generate the maximum possible , conjunction with the conversion rate divider to obtain the sample and hold time from the ADC clock. The , ADC total conversion time 8 ADC conversion clock rate divider bits (ConvRateDiv) 13 ADC data bits , . . . . . . . . . . . . . . . . 7 2 Total Conversion Time . . . . . . . . . . . . . . . . . . Texas Instruments
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SPRU586B TMS320VC5507 TMS320C55X TMS320VC5509A SPRU371 instruction set of TMS320C55x ADC 4-BIT TMS320VC5507/5509 SPRU586A
Abstract: , Critical limit. Function 9.5 ADC Conversion Rate Register, Access Address: "Command Index = 4h , [3:0] 4 0 Reserved. Not implemented. 9.11 ADC Conversion Rate Register, Access Address , equipment application. 4' conversion rate is 16 Hz (default value), 4' h8: h7: conversion rate is 8 Hz, 4' conversion rate is 4 h6: Hz, 4' conversion rate is 2 Hz, 4' conversion h5: h4: rate is 1 Hz, 4' conversion rate is 0.5 Hz, 4' h3: h2: conversion rate is 0.25 Hz, 4' conversion rate is h1 Analog Microelectronics
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ATTM02 ATTM01 h48 signal diode TM02G ATTM02G diode MARKING CODE 917 BTM marking ATTM01/ATTM02 ATT-DSATTM01/ATTM02-B
Abstract: switched on. Both the rate of battery self-discharge and the energy consumption of a silicon chip strongly , the charge of a fresh battery, the temperature history, and the discharge rate during normal use, one , iButton and the charge needed for a temperature conversion are determined through product , . Although the Device Samples Counter increments for each conversion, the temperature is not recorded and , approximately as much energy as one 8-bit temperature conversion. This energy consumption is, admittedly, very Maxim Integrated Products
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DS1922 DS1923 DS1922T DS1922L DS2422 APP3761 Thermochron Logger DS1922 DS1922/DS1923
Abstract: for scan rate conversion ­ Global motion detection flag (readable by I 2C Bus) ­ Movie mode and phase detector (readable by I 2C Bus) Embedded Memory 5 Mbit Embedded DRAM Core for Field Memories , Rate Conversion ­ Motion adaptive 100/120 Hz interlaced scan conversion ­ Motion adaptive 50/60 Hz , IFC Input format conversion ED eDRAM Noise reduction and measurement HDR Scan rate , blocks on a single chip: Flexible input sync controller Input format conversion Low data rate Siemens
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motion DETECTOR CIRCUIT DIAGRAM LM 886 IC chip ic 9400 MOTION DETECTOR PARALLEL progressive scan motion-detector siemens B110-H7217-X-X-7600
Abstract: Embedded Memory 5 Mbit Embedded DRAM Core for Frame Memory, (2 Field Memories) 192 kbit Embedded DRAM Core for Line Memories s Flexible Clock and Synchro- niszation Concept s Scan Rate Conversion - , High performance motion detector for scan rate conversion http://www.infineon.com Technical Data , Memory Controller LDR Vertical, Horizontal Decimation ED eDRAM HDR Scan Rate Conversion , conversion s High data rate processing s Flexible input sync controller s s Input format conversion Infineon Technologies
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B110-H7217-G1-X-7600
Abstract: deinterlacing. Other functions such as chroma resampling, color space conversion and frame rate conversion-all , Quartus (HDL) Frame Rate Conversion SOPC Builder R G MA Deinterlacer Clipper AFD Clipper , Space Converter Frame Buffer Scaler Cb Frame Rate Conversion R Test Pattern , buffer) Run-time controllable frame rate conversion Genlock Mixer present on one video processing , White Paper Enabling Improved Image Format Conversion with FPGAs FPGAs offer a competitive Altera
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HDMI to SDI converter chip hdmi SDI sdi to hdmi 1080p60 1080p60 video encoder Sigma Designs
Abstract: · Progressive scan conversion (262.5 to 525 or 312.5 to 625 lines/field) · Field rate up-conversion , produce an output line in either a field or a frame. The vertical sample rate conversion factor can be , conversion (262.5 to 525 or 312.5 to 625 lines/field) Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz , vertical sample rate conversion · Movie phase detection · Synchronous No parity Eight bit Reception and , specification Progressive scan-Zoom and Noise reduction IC (PROZONIC) FUNCTIONAL DESCRIPTION Field rate Philips Semiconductors
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SMD 6 PIN IC MARKING CODE z1 MARKING HRA SMD MARKING CODE Z2 TDA8755/8753A 83C652/54 QFP80 SAA4990H/V0 SAA4990H/V1 SAA4990H/V2
Abstract: . 7 Frame Rate Conversion , configured to operate on a different clock from the core. Simple frame rate conversion is employed to , , bob, intra and inter motion adaptive deinterlacing algorithms â'¢ Frame rate conversion â , pixel sample clock. The frame buffer module handles the rate conversion, and the line buffer and deinterlacing engine operate at the output pixel clock rate. When frame rate conversion is disabled, all the Lattice Semiconductor
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IPUG97 E2011 LFXP2-40E-7F484C
Abstract: when scan conversion first came up. Doubling the field scan rate requires to also double the , Scan rate doubling . . . . . . . . . . 3.3 Field repetition and frame repetition . 3.4 Video mode , Digital processing at 2f H level . . . . . . . . . . . . . . . . 4.3.1 Sample rate conversion. . . . . . , . . . . . . . 5.1 Problems in motion portrayal with picture rate conversion . 5.2 Motion , . 45 Fig. 46 Fig. 48 Block diagram of the scan conversion field memory . . . . . . . Scan Philips Semiconductors
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AN10233 MK14-EM SAA7118 TV 2 way splitter, circuit diagram EM 235 setting Video sync splitter lm 2 way video splitter circuit diagram SAA4998 ITU-656 SAA4979
Abstract: order to divide down the ADC clock to generate conversion clock. Last, it sets the SAMPTIMEDIV field in , the conversion clock. Program the conversion clock rate divider to generate the maximum possible , conversion rate divider to obtain the sample and hold time from the ADC clock. ADC Sample and Hold Period = , can begin every 46.5 us, giving a maximum sampling rate of 21.5 KHz. Total Conversion Time = (Sample , initialization and conversion of an arbitrary voltage into a digital value. This operation is illustrated using Texas Instruments
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TMS320VC5509 C5000 SPRU433A C5509 SPRA786 TMS320C55
Abstract: · Conversion of 704x512x60 fps and image sizes to HHR (1/2D1) and SIF sizes · Field or frame , estimation to half-pel accuracy · Adaptive field or frame DCT · Automatic adaptive quantization and rate , or field memory · Automatic adaptive quantization and rate controls · Automatic scene change , field memory · External FIFO feedback for dynamic rate control · Insertion of user data in encoded , estimation to half-pel accuracy · Adaptive field or frame DCT · Automatic adaptive quantization and rate IBM
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720x608 720X512 2855-2 PAL 720x576 picture in picture chip video encoder mpeg IBM39MPEGS42 IBM39MPEGSI IBM39MPEGS422PBA17C
Abstract: HSYNC Mode 7 FIELD Mode 8 FIELD Identification Line 8 Top Field Valid Line Count 8 Bottom Field , Start Position 15 Resolution Conversion Filter 16 Time Filter Coefficient 16 Time Filter Operating Mode 16 Sequence Header Insertion Interval 17 GOP Size 17 GOP Structure 17 Select Bit Rate Control , Method 21 Set System Bit Rate 22 Set Average System Bit Rate When Setting to VBR 22 Set Average System Bit Rate During VBR Operation 22 Audio Multiplexing Availability 23 Video Multiplexing Availability Fujitsu
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mb86390 SAA7113 SAA7113 AN mb8639 MB86390A
Abstract: (50/60 Hz progressive) scan rate conversion. The scan rate converted picture can be vertically , possible · Scan rate conversion - Simple 100/120 Hz interlaced scan conversion (e.g. AABB, AA*B*B , measurement RESET Interfaces HDR Scan rate conversion OFC output format conversion Data , HDR - High data rate processing (scan rate conversion, vertical expansion) I²C - I²C bus interface , of 50 Hz to 100 Hz interlaced scan rate conversion the OPDEL parameter should be greater than half Micronas
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CCIR656 F656 H656 6251-558-1PD
Abstract: Information Description Offset Register to control the conversion rate of the ADC input channels. 0x07 Bitfield Details Field 7:1 0 Name Reserved Conv_rate 0: 1: Sets the conversion rate to be ever 728 ms , temperature measurement. Conversion Rate Register: This register can be accessed to control the conversion , Description Offset Register to add further programmability to the conversion rate of the ADC input channels , Conversion rate as setup from register 0x07 bit 0 Conversion rate = 1.2 ms Conversion rate = 4.8 ms ON Semiconductor
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NCT80 NCT80DBR2G TSSOP-24 NCT80/D
Abstract: using scan rate conversion can increase this to up to 100 fields per second. For this purpose, each , MHz clock rate to the SDA 9280 display processor, which performs a D/A conversion in addition to , Field Memory YOUT Up conversion ­ Vertical Zooming ­ Panning UVIN Noise suppression , conversion is performed by the SDA 9206 (three A/D converters and a clock sync generator), and the digital 13.5 MHz clock rate YUV signal is fed into the SDA 9255's scan rate converter. The component Siemens
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Benning MSC SDA rhythm
Abstract: 10-2 10.1.1.1 Mode 1, 8-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 10-2 10.1.1.2 Mode 2, 9-Bit UART, Fixed Baud Rate . . . . . . . . . . . . . . . . . . . . . 10-5 10.1.1.3 Mode 3, 9-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 10-5 10.1.2 , Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.1.4 Baud Rate , . . . . . . 10-16 10.2.3 Baud Rate Detection of LIN . . . . . . . . . . . . . . . . . . . . . . . Infineon Technologies
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XC866 ETRX3 ETRX3 Restore Factory Defaults XC866L-2FR xc8662 XC866-4FR T12DTCH T12DTCL T12MSELH T12MSELL T12PRH
Abstract: -bit symbols, performs a Gray code conversion and uses a recursive adder to generate a 3-bit code representing , filters operate at 8x the incoming symbol rate and are configured, for each channel, as two filters in , ramping up rate and the ramping down rate are all programmable via the serial interface. 1.5.2.4 Offset , at a frequency of 128x symbol rate so as to over-sample the data at their inputs a further 16 times , of the Sigma-Delta A-D is 128x symbol rate. The high oversampling rate relaxes the design CML Microcircuits
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FX980 FX980L6 FX980L7 TETRA tetra modulation block diagram TETRA radio D/980/3
Abstract: for applications together with: · Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) · Line , (memory controller) · Variable vertical sample rate conversion SAA7158WP Back END IC (BENDIC) · , FUNCTIONAL DESCRIPTION Field rate up-conversion with line flicker reduction The line flicker reduction in conjunction with field rate up-conversion is performed by generating a 50 Hz interlace on the 100 Hz field , Noise reduction IC (PROZONIC) SAA4990H Vertical sample rate conversion Movie phase detection Philips Semiconductors
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