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Part Manufacturer Description PDF & SAMPLES
CDB4245 Cirrus Logic Evaluation, Design Tools Eval Bd 192kHz CODEC w/PGA & Input Mux
CDB5566 Cirrus Logic Evaluation, Design Tools Dev Bd for CS5566 w/mux
CDB5560 Cirrus Logic Evaluation, Design Tools Eval Bd 50kSps 24Bit Mux ADC
CS5560-ISZR Cirrus Logic Converters - Analog to Digital (ADC) IC 50 DSDS 24-bit Mux DS ADC
HI1-0547/883 Intersil Corporation 8-CHANNEL, DIFFERENTIAL MULTIPLEXER
DG407DJ Intersil Corporation 8-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDIP28

"e2 mux"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET FEATURES · E1 (2048 kbit/s) multiplexer , Transmit Receive Transmit +5V 3 3 TERMINAL SIDE E3 Clock & Data E123MUX E1/E2/E3 MUX/DEMUX TXC , E1 to E2 Multiplexer (Four) Ch 1 Ch 1 E1 Mux E1 Mux I/O HDB3, LOS E1TCKn FIFO Ch 2 Ch 3 Ch 4 E12 Mux , E2AISC 3 Mux 2-4 E1 Ch 1 E2 Mux E2 Data and Clock I/O Block E2 to E3 Multiplexer Ch 1 Ch 1 E2 Mux FIFO Ch 2 Ch 3 Ch 4 E23 Mux E3 Mux I/O HDB3 E2 Ch 1 E3TDP/E3TNRZ E3TDN E3TCKO E3TCKI E1TDPn/E1TNRZn TranSwitch
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E123 multiplexer HDB3 E2 03361 multiplexers 74 LS 150 E12/E23 TXC-03361-MB
Abstract: E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET PRODUCT PREVIEW FEATURES DESCRIPTION , (E12/E23 Split Mux) · E2 and E3 bit error rate indications APPLICATIONS · E1 and E3 line side , Transmit TERMINAL SIDE 3 E123MUX 3 3 E1/E2/E3 MUX/DEMUX 2 2 Microprocessor , E1 Mux E1 Mux E1 E2 Mux E2 Mux FIFO I/O Ch 2 Ch 3 E1TCKn E2 Data and Clock , = 1-4) Internal Clock E2 Ch 1 FIFO I/O Block Mux Ch 4 (n = 1 - 16) Ch 1 TranSwitch
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RE1C e2 mux mux E1
Abstract: BACK E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET FEATURES · Multiplexer/demultiplexer , Transmit +5V 3 3 TERMINAL SIDE E3 Clock & Data E123MUX E1/E2/E3 MUX/DEMUX TXC-03361 24 4 5 , E1 to E2 Multiplexer (Four) Ch 1 Ch 1 E1 Mux E1 Mux I/O HDB3, LOS E1TCKn FIFO Ch 2 Ch 3 Ch 4 E12 Mux , E2AISC 3 Mux 2-4 E1 Ch 1 E2 Mux E2 Data and Clock I/O Block E2 to E3 Multiplexer Ch 1 Ch 1 E2 Mux FIFO Ch 2 Ch 3 Ch 4 E23 Mux E3 Mux I/O HDB3 E2 Ch 1 E3TDP/E3TNRZ E3TDN E3TCKO E3TCKI E1TDPn/E1TNRZn TranSwitch
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Abstract: system requiring no additional interface logic. The availability of multiple chip enable (FT and E2) and , memory. By connecting DSP56001 address A15 to the VECTOR/ SCALAR (V/S) MUX control pin, such partitioning , SRAM DATA MCM56824AZP 4-11 BLOCK DIAGRAM v/s IT H X L L L L L E2 G X X H L L X X w , = 0 to V cc) Output Leakage Current (G = V|h , El = Vm. E2 * V|i_, Vout = 0 to V cc) AC Supply Current (5 V|h , ET * V|l , E2 » V|h , lout * 0 m^. All Other Inputs > V|_ 0.0 V and Vih ^ 3.0 V -
OCR Scan
MCM56824A DSP560Q1 MCM56924A MCM56824AZP20 MCM56824AZP20R2 MCM56824AZP25
Abstract: E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET FEATURES DESCRIPTION · Multiplexer , Mux) · E2 and E3 bit error rate indications APPLICATIONS · E1 and E3 line side interfaces are , Transmit TERMINAL SIDE 3 E123MUX 3 3 3 E1/E2/E3 MUX/DEMUX 2 2 TXC-03361 2 , E1 to E2 Multiplexer (Four) Ch 1 Ch 1 E1 Mux E1TDPn/E1TNRZn E1 Mux E1 E2 Mux E2 Mux , E12TDm/ E23TDm E12TCKOm/ E23TCKm (m = 1-4) Internal Clock E2 Ch 1 FIFO I/O Block Mux TranSwitch
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c5lsm introduction of demux TXC-03361-AIPQ
Abstract: features Y Z7ÛÏÏW description E123MUX Device e1/e2/e3 mux/demux txc-03361 data sheet PRODUCT PREVIEW Multiplexer/demultiplexer for ITU-T Recommendations: G.742 (E2 frame format) G.751 (E3 , - (n = 1-16) 3 Mux 2 El to E2 Multiplexer (Four) Ch 1 E1 Mux I/O HDB3, LOS E1 Mux FIFO E1 Ch 1 , 12TDm¿ E 23TDm E12TCK pm/ E 23TCKrp (11 = 1-4) E2 to E3 Multiplexer Ch 1 E2 Mux I/O Block E2 Mux FIFO Internal Clock - E2 Ch 1 Ch2 Ch 3 Ch 4 E3 Mux I/O HDB3 MCMI Frame Pattern Alarm Bit National Bit AIS -
OCR Scan
TT 46 N 16 LOF 10D41 4S50 Alarm Clock by using ttl Digital Alarm Clock by using ttl E23AIS R23CS E12RL E23RL TD0415E
Abstract: Control DQ23 Column Decoder E1 E2 & V/S & W G 1 Q A12i 0 2 to 1 MUX X/Y , Low and E2 asserted High. tcR Ai Address Valid V/S MUX Control Valid tdis(E) ta(E , asserted Low and E2 asserted High. tcW Ai Address Valid tsu(A -E) tsu(A) V/S th(A) MUX , interface logic. The avialability of multiple chip enable (E1 and E2) and output enable (G) inputs , 34 DQ12 W NC E1 E2 VCC VSS G A6 A7 21 22 23 24 25 26 27 28 29 30 31 32 33 Zentrum Mikroelektronik Dresden
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PLCC52 U62H824 DSP56 M3015 D-01109 D-01101
Abstract: Output Hold Time from MUX Control Change E1 LOW or E2 HIGH to Output in Low-Z G LOW to Output in Low-Z E1 , E2 asserted High. tcW Ai tsu(A) Address Valid tsu(A-E) MUX Control Valid tsu(VS-E) tw(E , avialability of multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system , A5 Signal Name A0 - A11 A12, X/Y V/S DQ0 - DQ23 E1, E2 G W VCC VSS NC Signal Description , VCC VSS W NC G DQ12 A9 A8 A7 DQ11 A6 E1 E2 For proper operation of the device, all VSS pins must be Zentrum Mikroelektronik Dresden
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U62H824PA
Abstract: E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET PRODUCT PREVIEW FEATURES = â'¢ Multiplexer/demultiplexer for ITU-T Recommendations: G.742 (E2 frame format) G.751 (E3 frame format , /demultiplexer converts: 16 E1s to/from 1 E3 (E13 Skip Mux), or 16 E1 s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 Split Mux) â'¢ E2 and E3 bit error rate indications APPLICATION â'¢ E1 and E3 line , channels) Receive - TERMINAL SIDE E123MUX â ~ 4~ Transmit" Receive â  E1/E2/E3 MUX -
OCR Scan
Abstract: Hold Time from Address Change Output Hold Time from MUX Control Change E1 LOW or E2 HIGH to Output in , multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when , A5 Signal Name A0 - A11 A12, X/Y V/S DQ0 - DQ23 E1, E2 G W VCC VSS NC Signal Description , VCC VSS W NC G A9 A8 A7 A6 E1 E2 DQ12 DQ11 34 For proper operation of the device, all VSS pins , A5 A10 A11 Decoder Array 256 Rows x 768 Columns VCC VSS DQ0 DQ23 E1 E2 W G Input Data Control Zentrum Mikroelektronik Dresden
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Abstract: Hold Time from Address Change Output Hold Time from MUX Control Change E1 LOW or E2 HIGH to Output in , multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when , A5 Signal Name A0 - A11 A12, X/Y V/S DQ0 - DQ23 E1, E2 G W VCC VSS NC Signal Description , VCC VSS W NC G A9 A8 A7 A6 E1 E2 DQ12 DQ11 34 For proper operation of the device, all VSS pins , A5 A10 A11 Decoder Array 256 Rows x 768 Columns VCC VSS DQ0 DQ23 E1 E2 W G Input Data Control Zentrum Mikroelektronik Dresden
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Abstract: DQ23 Column Decoder E1 E2 & V/S & W G 1 Q A12i 0 2 to 1 MUX X/Y A12 & , Time from MUX Control Change tv(VS) 5 ns E1 LOW or E2 HIGH to Output in Low-Z tLZCE , (E1 and E2) and output enable (G) inputs provides for greater system flexibility when multiple , DQ12 W NC E1 E2 VCC VSS G A6 A7 21 22 23 24 25 26 27 28 29 30 31 32 33 DQ11 , Ground Not Connected E1, E2 G W VCC VSS NC For proper operation of the device, all VSS pins Zentrum Mikroelektronik Dresden
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Abstract: & A12i 1 0 Q 2 to 1 MUX A6 A9 (LSB) (MSB) Truth Table Mode E1 E2 G , MUX Control Change E1 LOW or E2 HIGH to Output in Low-Z tLZCE ten(E) 0 ns G LOW to , avialability of multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system , Voltage Ground Not Connected November 26, 2002 34 DQ21 VSS DQ20 DQ19 VSS DQ14 E1, E2 , ground. DQ12 W NC E1 E2 VSS VCC G A6 21 22 23 24 25 26 27 28 29 30 31 32 33 A7 Zentrum Mikroelektronik Dresden
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Tv Diagram ic data book tv and setup 0800 0FFF DECODER ZMD AG
Abstract: Address Change Output Hold Time from MUX Control Change E1 LOW or E2 HIGH to Output in Low-Z G LOW to , Low and E2 asserted High. tcR Ai V/S E1 G DQi Output High-Z ten(E) Address Valid MUX , E2 asserted High. tcW Ai V/S tsu(VS) Address Valid tsu(VS-WH) MUX Control Valid tsu(E) th(A , E2 with E1 asserted Low and E2 asserted High. tcW Ai tsu(A) Address Valid tsu(A-E) MUX , multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when Zentrum Mikroelektronik Dresden
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Abstract: E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET FEATURES DESCRIPTION = â'¢ Multiplexer/demultiplexer for ITU-T Recommendations: G.742 (E2 frame format) G.751 (E3 frame format) The , /demultiplexer converts: 16 E1s to/from 1 E3 (E13 Skip Mux), or 16 E1 s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 Split Mux) â'¢ E2 and E3 bit error rate indications APPLICATIONS â'¢ E1 and E3 line , '¢ 208-pin plastic quad flat package +5V LINE SIDE E3 Clock & Data E2 Clock & Data (x 4 -
OCR Scan
TXC-03361-M
Abstract: Output Hold Time from MUX Control Change E1 LOW or E2 HIGH to Output in Low-Z G LOW to Output in Low-Z E1 , E2 asserted High. tcW Ai tsu(A) Address Valid tsu(A-E) MUX Control Valid tsu(VS-E) tw(E , avialability of multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system , A5 Signal Name A0 - A11 A12, X/Y V/S DQ0 - DQ23 E1, E2 G W VCC VSS NC Signal Description , VCC VSS W NC G DQ12 A9 A8 A7 DQ11 A6 E1 E2 For proper operation of the device, all VSS pins must be Zentrum Mikroelektronik Dresden
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Abstract: multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when , A5 Signal Name A0 - A11 A12, X/Y V/S DQ0 - DQ23 E1, E2 G W VCC VSS NC Signal Description , VCC VSS W NC G A9 A8 A7 A6 E1 E2 DQ12 DQ11 34 For proper operation of the device, all VSS pins , A5 A10 A11 Decoder Array 256 Rows x 768 Columns VCC VSS DQ0 DQ23 E1 E2 W G Input Data Control Column I/O Column Decoder & & X/Y A12 V/S A12i 1 0 Q 2 to 1 MUX A6 (LSB) (MSB) A9 & Truth Zentrum Mikroelektronik Dresden
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Abstract: . . . . . . . . . . . . . . . . . . . . . Write Enable E1, E2 . . . . . . . . . . . . . . . . . . . , enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when multiple , /S) MUX control pin, such partitioning can occur with no additional components. This allows , A7 A6 G VCC VSS E1 E2 W NC DQ12 Freescale Semiconductor, Inc. DSPRAMâ"¢ 8K x 24 Bit , D21 D23 W D12 D14 D15 E1 VSS 1 D19 VSS D22 A5 A4 E2 A3 A2 VSS A1 Freescale Semiconductor
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MCM56824A/D
Abstract: 1 MUX A6 A9 (LSB) (MSB) Truth Table E1 E2 G W V/S Mode Supply Current , Low and E2 asserted High. tcR Ai Address Valid V/S MUX Control Valid tdis(E) ta(E , asserted Low and E2 asserted High. tcW Ai Address Valid tsu(A -E) tsu(A) V/S th(A) MUX , interface logic. The avialability of multiple chip enable (E1 and E2) and output enable (G) inputs , 34 DQ12 W NC E1 E2 VCC VSS G A6 A7 21 22 23 24 25 26 27 28 29 30 31 32 33 Zentrum Mikroelektronik Dresden
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Abstract: DQ23 Column Decoder E1 E2 & V/S & W G X/Y A12 & 1 Q A12i 0 2 to 1 MUX , Low and E2 asserted High. tcR Ai Address Valid V/S MUX Control Valid tdis(E) ta(E , asserted Low and E2 asserted High. tcW Ai Address Valid tsu(A -E) tsu(A) V/S th(A) MUX , (E1 and E2) and output enable (G) inputs provides for greater system flexibility when multiple , DQ12 W NC E1 E2 VCC VSS G A6 A7 21 22 23 24 25 26 27 28 29 30 31 32 33 DQ11 Zentrum Mikroelektronik Dresden
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