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DG419BAK-E3 Vishay Siliconix PRECISION CMOS ANALOG SWITCH
DG202BAK-E3 Vishay Siliconix IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP16, LEAD FREE, CERDIP-16, Multiplexer or Switch
DG417BAK-E3 Vishay Siliconix Analog Switch Single SPST 8-Pin CDIP
DG201BAK-E3 Vishay Siliconix IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP16, LEAD FREE, CERDIP-16, Multiplexer or Switch
DG418BAK-E3 Vishay Siliconix PRECISION CMOS ANALOG SWITCH
5503-05-1 Coto Technology USA Dry Reed Relay

"dry bake"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: detailed instructions for dry bake. This information provides ON Semiconductor customers with the , http://onsemi.com 2 AND8003/D Table 3. Bake Conditions for SMD Packages prior to Dry Pack after , life. This can be accomplished by dry packing or storing in a dry cabinet maintained at 5% RH. Bake , moisture sensitive and delivers in a dry pack. Moisture sensitive devices include, but are not limited to , LIMITS OUT OF DRY PACK The MSL at which each SMD is classified determines the appropriate packaging ON Semiconductor
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JEDEC J-STD-020d.1 JESD625-a 12MSB17722C AND8003 JEDEC J-STD-033b.1 jedec JESD625-a
Abstract: REQUIRE BAKE AND DRY PACK WITH APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES CLASSIFIED LEVEL 2 REQUIRE DRY PACK ONLY WITH APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES CLASSIFIED LEVEL 1 REQUIRE NO BAKE , TEMP BAKE TIME DRY PACK/ NOTES +125C N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A , REQUIRE BAKE AND DRY PACK WITH APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES CLASSIFIED LEVEL 2 REQUIRE DRY PACK ONLY WITH APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES CLASSIFIED LEVEL 1 REQUIRE NO BAKE Micrel Semiconductor
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0PM01 060911HC04 042612PM04 MLF44D-08LD CDFN2520-04L CDFN3225-04L
Abstract: SMD PACKAGES HOW TO USE THIS TABLE: PRODUCT AND PACKAGES CLASSIFIED LEVEL 2A-6 REQUIRE BAKE AND DRY , APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES CLASSIFIED LEVEL 1 REQUIRE NO BAKE AND NO DRY PACK PACKAGE , : PRODUCT AND PACKAGES CLASSIFIED LEVEL 2A-6 REQUIRE BAKE AND DRY PACK WITH APPROPRIATE WARNING LABEL , PACKAGES CLASSIFIED LEVEL 1 REQUIRE NO BAKE AND NO DRY PACK PACKAGE TYPE SOICW PRODUCT ALL , 5.0 2000-0012, DRY PACK PROCEDURE FOR MOISTURE SENSITIVE DEVICES EQUIPMENTS AND SUPPLIES N/A Micrel Semiconductor
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20L-28L 44L-84L LGA 16L SOT23 2A6 18-6731TO SY69952 MIC5400 14L48L 8-28L KS8721SL
Abstract: have occurred to indicate excess moisture exposure. Table 4-2 gives conditions for bake prior to dry , ) . 3 DRY PACKING . 3 3.1 3.2 , . Drying Requirements - Other . Excess Time Between Bake and Bag. Dry Pack . Description , . 9 Dry Pack. 9 Dry Atmosphere Silicon Standard
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JEDEC JEP113 B J-STD-033A J-STD-033
Abstract: Reflow Package Moisture Sensitivity Levels per J-STD-020 Factory Floor Life Dry Bake Recommendation and Dry Bag Policy Handling Parts in Sealed Bags Moisture Induced Cracking During Solder Reflow The , floor level. Dry Bake Recommendation and Dry Bag Policy Xilinx recommends, as do the mentioned , =Default value of semiconductor manufacturer's time between bake and bag. If the semiconductor manufacturer's actual time between bake and bag is different from the default value, use the actual time. 2. Y = Floor Xilinx
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ipc-sm-786A Q1-02
Abstract: PACKAGES CLASSIFIED LEVEL 2A-6 REQUIRE BAKE AND DRY PACK WITH APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES CLASSIFIED LEVEL 2 REQUIRE DRY PACK ONLY WITH APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES CLASSIFIED LEVEL 1 REQUIRE NO BAKE AND NO DRY PACK PACKAGE TYPE BGA/PBGA/LFBGA CHIP SCALE (WLP , CLASSIFIED LEVEL 2A-6 REQUIRE BAKE AND DRY PACK WITH APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES , LEVEL 1 REQUIRE NO BAKE AND NO DRY PACK PACKAGE TYPE PRODUCT LEAD COUNT PACKAGE THICKNESS Micrel Semiconductor
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MLF33 FTMLF1010 HMLF3035 HMLF2520 HMLF46T MIC2829 MLF1212
Abstract: Moisture-Sensitive Devices Handling Information Cypress Dry Bag Policy In order to insure against moisture damage, Cypress carries out dry bake and dry packing on all devices that are moisture sensitive in , Plastic Quad Flat Packs (PQFPs), and Thin Quad Flat Packs (TQFPs) be used dry in surfacemount applications. NOTE: A package is considered dry if it has been baked for 24 continuous hours at 125 ± 5°C and has , warning stated on the caution label, the sealed MBBs should be stored unopened in a relatively dry Cypress Semiconductor
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Abstract: against moisture damage, Cypress carries out dry bake and dry packing on all devices that are moisture , fax id: 6001 1 Moisture-Sensitive Devices Handling Information Cypress Dry Bag Policy , higher, all Plastic Quad Flat Packs (PQFPs), and Thin Quad Flat Packs (TQFPs) be used dry in surfacemount applications. NOTE: A package is considered dry if it has been baked for 24 continuous hours at , Baked devices are then vacuum sealed and dry packed in MBBs within the 24 hour factory-floor-life limit Cypress Semiconductor
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Abstract: , 150°C P High Accelerated Saturation Test (HAST) 130°C, 85% RH, 5.5V Precondition: Dry bake , : Dry bake + 72 Hrs 30°C/60%RH P Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Precondition: Dry Bake, 3 Cys Solder Relfow P Temperature Cycle JEDEC22 CONDITION B, -40°C to 125°C Precondition: Dry Bake, 3 Cys Solder Reflow P Pressure Cooker Test 121 , -STRESS: HI-ACCEL SATURATION TEST (130C, 85%RH, 5.5V), PRECONDITION DRY BAKE + 3 CYS SOLDER REFLOW Cypress Semiconductor
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CY7C0251 CY7C025 CY7C0241 CY7C024 CY7C145 CY7C144 Hitachi PIX-8144 Hitachi PIX 8144 Pix-8144 PIX 8144 hitachi 8144 CY7C025-AC
Abstract: Handling Requirements All surface mount products which do not meet Level 1 moisture sensitivity requirements are processed through dry bake and pack procedure. The necessary data is recorded on the caution , at , conditions , high temperature or shorter bake times are desired, reference IPC/JEDEC-J-STD-033 for bake procedure Peregrine Semiconductor
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JEDEC J-STD-033 JEDEC-J-STD-020 JEDEC-J-STD-033 JEDECJ-STD-033 IPC/JEDEC-J-STD-020
Abstract: MOISTURE SENSITIVITY CLASSIFICATION OF MICREL SMD PACKAGES HOW TO USE THIS TABLE: PRODUCT AND PACKAGES CLASSIFIED LEVEL 3 REQUIRE BAKE AND DRY PACK WITH APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES CLASSIFIED LEVEL 2 REQUIRE DRY PACK ONLY WITH APPROPRIATE WARNING LABEL PRODUCT AND PACKAGES CLASSIFIED LEVEL 1 REQUIRE NO BAKE AND NO DRY PACK NON SMD PACKAGES (THROUGH-HOLE ) NOT CLASSIFIED REQUIRE NO BAKE AND NO DRY PACK Package Type Product Lead Count PDIP ALL ALL TO-220 ALL ALL TO -
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128-208L 8L-10L 8L-16L SMD Packages 8l smd MQUAD 16L-20L SC-70 14L-48L
Abstract: -931210 Procedure for Dry Bagging Moisture Sensitive Plastic IC Packages PMC-940101 Procedure for the Bake Out of , . 4 DRY BAGS AND BOXES . 5 3.1 DRY BAGS . 5 3.2 DRY BOXES , FURTHER READING. 12 8 APPENDIX A - BAKE OUT WORK PMC-Sierra
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PMC-951041 ic packages A113 baxter iv bag
Abstract: the areas of moisture absorption, reflow conditions, plastic package cracking, dry packing procedures , °C/60% RH 6 Time on Label (TOL) 30°C/60% RH DRY PACK PROCEDURE After electrical testing , trays is then secured by a plastic strap, and subsequently placed into the appropriate dry pack bag, along with four units of desiccant and one humidity indicator card. The dry pack bag is then evacuated , time. Finally, the dry pack is visually checked for seal quality and for tears or other imperfections National Semiconductor
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JEDEC J-STD-033b MIL-D-3464 type 1 MIL-D-3464 MIL-D-3464 type 1 and 2 J-STD-033B MIL-B-81705 CSP-9-111C2 CSP-9-111S2
Abstract: moisture absorption, reflow conditions, plastic package cracking, dry packing procedures, and rework , Time on Label (TOL) 30°C/60 2a Moisture Barrier Dry Packing RH RH RH RH RH RH RH RH DRY PACK PROCEDURE After electrical testing, moisture sensitive plastic packages , strap, and subsequently placed into the appropriate dry pack bag, along with four units of desiccant and one humidity indicator card. The dry pack bag is then evacuated and sealed at 70 psi of pressure National Semiconductor
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MILD-3464 MIL-D3464 Furnace
Abstract: deballing process BGA reballing process Cleaning fixtures Bake and dry packaging Flexible fixture setup - , the oven reaches operating temperature, place BGA packages in the bake out oven. Step 3 - Dry , . Bake & dry pack: Bake in an oven for a time based on the JEDEC moisture level table and vacuum pack , Oven (recommended for moisture removing bake) Hot air reflow system, convection oven, or conveyor , page 19). When the exposure exceeds the allowed time, the JEDEC standard specifies a bake out. The Emulation Technology
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reballing Alpha WS609 solder reflow hot air BGA WS609 solder paste alpha WS609 Lead Free reflow soldering profile BGA
Abstract: dry storage or bake, per J-STD-033. To verify this capability for a component classified at a , socket mounted, or baked dry within time on label before reflow soldering. The minimum bake time and , Weight The dry weight of the sample should be determined first. Bake the sample for 48 hours minimum at , 8.2.4 8.3 8.3.1 Read Points . Dry Weight , Inspection . Bake -
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J-STD-020B JESD47 Infineon moisture sensitive package JESD-47 J-STD-035 semiconductors cross reference AMD reflow soldering profile BGA J-STD-020C IPC-J-STD-020 1-580987-46-X
Abstract: or IR, then they should be baked dry first, using the same baking procedures described for SMT , been determined. Intel bakes PSMC packages dry and seals them in bags with desiccant before shipping*. , For Handling Units in Desiccant Pack Intel ships moisture sensitive PSMCs in a dry state inside , those devices subjected to SMT processes. Handling information covers dry component storage life , are shipped in desiccant packing. Each shipping medium contains units that have been baked dry and Intel
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822 smd MIL-STD-81705 intel 815 reflow profile MIL-B-81705 cap A5753-01 A5760
Abstract: 44L PDIP32L PDIP32L PDIP32L Dry Bake Dry Bake 85°C/85%RH 85°C/85%RH Dry Bake SnPb SnAgCu , PDIP32L FW 25L FW 25L FW 25L Dry Bake 85°C/85%RH 85°C/85%RH Dry Bake SnAgCu SnPb SnAgCu SnPb 245 245 245 245 5 5 5 5 10/10 10/10 10/10 10/10 FW 25L Dry Bake SnAgCu , %RH 85°C/85%RH Dry Bake Dry Bake SnPb SnAgCu SnPb SnAgCu PQFP28X28 PQFP28X28 PQFP28X28 PQFP28X28 85°C/85%RH 85°C/85%RH Dry Bake Dry Bake PLCC 44L PLCC 44L 0.5 Wetting Force -
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ST-300 FLUX TYPE ROL0 ALLOY leadframe C7025 ST-50 smd EDL 63 C7025 strip specification
Abstract: standards for packaging of all our devices. The concept behind moisture control is to dry bake units prior , moisture exposure, the product is acceptable for use. 2. Repeat Dry Bake ­ if there is an indication of , handling, dry packing, and exposure limits are established for each MSL rating to ensure no manufacturing , addition to adhering to the JEDEC standards for packaging, Lattice Semiconductor also audits all dry packed inventories on an annual basis. All inventories are marked with the date of dry pack, and the Lattice Semiconductor
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Date Code restriction JESD22-B102-C shelf life J-STD-020-A 1-888-ISP-PLDS
Abstract: moisture sensitivity. · Bake 10 units of each product for 48 hours at 125°C to dry out any absorbed , should be baked dry first, using the same baking procedures described in this book for SMT packages , PSMC packages dry and seals them in bags with desiccant before shipping*. Recommended shelf life , -lead TSOP packages are not shipped in bake and bag. 8.4. GUIDELINES FOR HANDLING UNITS IN DESICCANT PACK Intel will ship moisture sensitive plastic surface mount components (PSMCs) in a dry state Intel
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Ultrasonic cleaner circuit diagram intel packaging handbook 240800 LEAD FRAME SURFACE MOUNT PQFP die size INTEL PLCC 68 dimensions tape Intel Packaging Handbook 240800 solder CH08WIP
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