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CS5508-BSZR Cirrus Logic Converters - Analog to Digital (ADC) IC 20-Bit 4-Ch ADC
CS5526-BSZR Cirrus Logic Converters - Analog to Digital (ADC) IC 20Bit Delta Sigma Multi-Range ADC
CS5550-ISZR Cirrus Logic Converters - Analog to Digital (ADC) IC 2-Ch Low-Cost 24-Bit ADC
CS5509-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC Single-Supply 16-Bit ADC
CS5512-BSZR Cirrus Logic Converters - Analog to Digital (ADC) IC 20-Bit 8-Pin Delta Sigma ADC
CS5532-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC 16-Bit ADCs w/UltraLw Noise PGIA

"digital delay" 14

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: MIX MIX R VISS ^ENESAS (1/14) _digital echo (digital delay) MITSUBISHI SOUND PROCESSOR ICS , -COM 9 â u 16 OP2 IN SLEEP 10 15 OP2 OUT D-GND 11 14 LPF2IN A-GND 12 13 LPF2 OUT ( 2/14 , Unit Resistances ^ENESAS (3/14) MITSUBISHI SOUND PROCESSOR ICS ^e^ M65831AP/FP _digital echo , external C.R @ LPF1 IN Low pass filterl input 1 @ Vcc Analog Vcc â'" Supply voltage ^ENESAS (4/14 , 0.3vdd V ^ENESAS (5/14) MITSUBISHI SOUND PROCESSOR ICS M65831AP/FP _digital echo (digital delay -
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M65843AP DIGITAL ECHO IC M65831Ap m65843 DIGITAL ECHO IC M65831 M65831AFP M65830 M65831A
Abstract: MIC1- M65381 AP/FP MIC2 A* MITSUBISHI ELECTRIC (1/14) SV* o ^ _*0t\. « , > ;u "n "0 20 19 18 17 16 15 14 13 Vcc LPF1 IN LPF1 OUT OP1 OUT OP1 IN REF CC1 CC2 OP2 IN OP2 OUT LPF2 IN LPF2OUT 4 MITSUBISHI W * ELECTRIC ( 2/14) MITSUBISHI SOUND PROCESSOR ICS ' xs?e , W * ELECTRIC ( 3/14) SV* _*0t\. « , e \c ^G f > 9e' \s9y \o o ^ MITSUBISHI SOUND , external C.R Supply voltage 4 MITSUBISHI W * ELECTRIC (4/14) SV* _*0t\. « , e \c ^G f > 9e -
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Echo Processor IC M65831 16 Pin Echo delay digital ICs m6538 TDA 1106 M65830CP M65831AP 24P2W-A
Abstract: ( 1 / 14 ) ts \i"i â  Â»Â«> , 9 16 O P2 IN SLEEP 10 15 O P2 O U T D-GND 11 14 L P F 2 IN A-G N D , ELECTRIC ( 2 / 14) MITSUBISHI SOUND PROCESSOR ICS »«g ® *' M65831AP/FP DIGITAL ECHO , Unit Resistance:^ 4 MITSUBISHI ELECTRIC ( 3 / 14) ts \i"i â  Â»Â«> , 0 Forms integrator with external C.R 1 1 ELECTRIC ( 4 / 14) Forms integrator with -
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Abstract: 450mil SOP (8.4mm X15.0mm X2.0mm) ( 1/14) MITSUBISHI SOUND PROCESSOR ICS ·« 'Æ ^ >c, M65830BP , TEST2 1 2 3 4 5 6 7 8 9 10 24 23 22 21 Vcc LPF1 IN LPF1 OUT OP1 OUT 20 OP1 IN 19 18 17 16 15 14 13 , ) 4 MITSUBISHI ( 2/14) ELECTRIC MITSUBISHI SOUND PROCESSOR ICS , \ S 'Í '° VM0S , (3/14) ELECTRIC \n * P MITSUBISHI SOUND PROCESSOR ICS M65830BP/FP DIGITAL DELAY PIN , filterl output o o 1 - f4) 4 MITSUBISHI (4/14) ELECTRIC \n * * MITSUBISHI SOUND -
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Digital Sound Processor circuit diagram M65830B
Abstract: MITSUBISHI W * . ELECTRIC ( 1/ 14) b\\n ^ ago. ec^'c MITSUBISHI SOUND PROCESSOR ICS p , 9 16 OP2 IN TEST2 10 15 OP2 OUT D-GND 11 14 LPF2 IN A-GND 12 , / 14) b\\n ^ ago. ec^'c MITSUBISHI SOUND PROCESSOR ICS p c^®-° M65830BP/FP , 4 MITSUBISHI W * . ELECTRIC (3/14) b\\n ^ MITSUBISHI SOUND PROCESSOR ICS p , /14) b\\n ^ MITSUBISHI SOUND PROCESSOR ICS p ec^xC c^®-° M65830BP/FP ra'Q -
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5830BP/FP
Abstract: -pin available) Copyright © 2013 Altonics Co, Ltd. p. 2 / 14 AGDE-E20 : Premium Digital Audio Signal , © 2013 Altonics Co, Ltd. p. 3 / 14 AGDE-E20 : Premium Digital Audio Signal Processing Module , Output * Above audio flow chart can be customized. Copyright © 2013 Altonics Co, Ltd. p. 4 / 14 , , Ltd. p. 5 / 14 AGDE-E20 : Premium Digital Audio Signal Processing Module SPC20 DSP-ware SPC20 , Co, Ltd. p. 6 / 14 AGDE-E20 : Premium Digital Audio Signal Processing Module Drive & Sound Altonics
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Abstract: SLEEP 10 15 OP2 OUT D-GND 11 14 LPF2 IN A-GND 12 13 LPF2 OUT M65831AP , 4.7k 18 20 OP2 IN 17 16 DEM OP2 LPF2 OUT IN 15 14 4.7k LPF2 OUT 13 , Low pass filter1 input Analog VCC 12 13 14 15 16 17 18 19 20 21 22 23 24 LPF2 OUT , LPF2 14 560p 10k 5600p 15k DIG.GND S10 10 OP2 MO 15 4.7k 0.1u 15k , 0.1u 2MHz 100p u -COM MITSUBISHI ELECTRIC 14 LPF2 OUT DGND 7 LPF2 IN SLEEP Mitsubishi
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Digital Echo delay 16 Pin ICs MITSUBISHI Digital Echo delay 8 ICs M65381AP digital echo TDA echo audio echo ic
Abstract: Considerations for specifying delay lines 4 5 6-7 8 9 10 11 12 13 13 14 15 16 17 18 19 20 21 22 22 23 24 25 26 27 , DELAY LINES 14 pin DIR 5 tap 14 pin DIP, 10 tap 14 pin DIP, fixed delay 14 pin DIP, 5 tap, controlled leading and trailing edge A447-XXXX-08 14 pin DIP, fixed delay, low power module A447-XXXX-09 14 pin DIP, 5 tap, low power module A447-XXXX-A3 14 pin DIR Triple output module 0462-XXXX-02 8 pin single in , 14 pin DIP, 10 tap 0401 Series, 8 pin single in line, fixed delay 0438 Series, 14 pin single in line -
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Delay Lines Digital Delay Lines 0438 Series digital delay generator A463-XXXX-02 A447-XXXX-02 A447-XXXX-10 A447-XXXX-06 A447-XXXX-A1 0449-XXXX-03
Abstract: delay time in a range between 15ms and 200ms) · Small package (14-pin DIP : 14P4,16-pin SOP:16P2N) · , OP1 OUT 3 OP1 IN 4 CC1 5 CC2 6 GND 14 VCC 14 M 6 5 8 5 0 P LPF1 IN 13 CLOCK 12 REF 11 OP2 IN 10 OP2 OUT 9 LPF2 IN 7 8 LPF2 OUT NC 1 14 16 , < M65850FP > M 6 5 8 5 0 F P MITSUBISHI ELECTRIC NC 15 VCC 14 CLOCK 13 REF 12 OP2 IN 11 OP2 , < M65850FP > REF 13 CLOCK 14 5 CC1 7 14 GND VCC CC2 OP2IN OP2OUT LPF2IN LPF2OUT 7 12 11 Mitsubishi
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M65850P karaoke echo chip 16pin dip karaoke CIRCUIT echo digital ic Karaoke Processor IC karaoke amplifier CIRCUIT M65850P/FP
Abstract: master clock set at 1MHz) (Selection of delay time in a range between 15ms and 200ms) Small package (14 , CC2 GND 1 2 3 14 13 a> Vcc CLOCK REF OP2 IN OP2 OUT LPF2 IN LPF2 OUT 12 11 10 9 8 cn , C T > cn 00 cn o T| TJ 15 14 13 12 11 10 9 NC Vcc CLOCK REF OP2 IN OP2 OUT LPF2 IN LPF2 OUT 4 , - 9 10 11 12 13 14 15 o I 9 10 11 12 13 14 - To form input-side low pass filter by , 2 1 1 1 2 S 14 2 1 1 1 1 Remarks No-signal time RL=47k£2 TH D =10% Output distortion -
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MITSUBISHI Digital Echo delay echo circuit diagram ci m65850p echo digital 65850p 120KF M65850P/M65850FP M65850F 65850P
Abstract: . 10 Tap 14 Pin DIL Package 3 5 DELAY UNES 20A, 21A S é rié s , . 9 5 Tap and Triple Indépendant 14 Pin Moulded DIP LOW-POWER DELAYS 31L, 341 S é r ié s .13 5 Tap and Triple Indépendant 14 Pin Moulded DIP DIGITAL DELAY MODULES 42A, 42S S é r ié s .17 5 Tap 14 Pin DIL Package DIGITAL. DELAY MODULES 50A, 52A, 52S Sériés. 21 10 Tap 14 Pin Moulded DIP DIGITAL DELAY MODULES 60A S é rié s -
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digital delay 14 PIN DIL PACKAGE Delay Modules
Abstract: , frequency division, digital and analog delay adjustments, and fourteen (14) programmable differential , ) Input and Output Frequency Range 1 kHz to 3.1 GHz Separate Input for Clock Output Banks A & B. 14 , . 14 13.0 Measurement Definitions , . 30 16.8.1 CLKout12_ADLY_SEL[13], CLKout13_ADLY_SEL[14], Select Analog Delay . , Descriptions (Note 3) Pin Number 1 2, 3 4, 5 6 7, 8 9. 10 11 12 13, 14 15 16, 17 18, 19 20 21, 22 23, 24 25 26 Texas Instruments
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LMK01801 LMK01801BISQ LMK01801BISQE LMK01801BISQX K01801BI
Abstract: s CIBM7xx Digital Pulse Compressor Preliminary Specification May 14, 2007 Features , Preliminary Specification May 14, 2007 Absolute maximum ratings Parameters Unit Minimum , May 14, 2007 Digital compression parameters. Parameters Unit Center frequency (F0 , Digital Pulse Compressor Preliminary Specification May 14, 2007 Theory of operation CIBM7xx is a , Compressor Preliminary Specification May 14, 2007 1000 B-TYPE T (us) 100 A-TYPE 10 Temex
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pulse compression COMPRESSOR PLUG xilinx adc 12VDC RET12V
Abstract: M62465FP Dolby Pro Logic Surround REJ03F0219-0200 Rev.2.00 Sep 14, 2006 Description The , REQ Rev.2.00 Sep 14, 2006 page 1 of 24 DELAY SIG OUT DELAY SIG IN FBIN SU 47 46 SFB 64 , 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Rev.2.00 Sep 14, 2006 page 2 of 24 VREFG 28 , 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 63 , Note: The function of pin No.1, 79, 80 is different from that of M62460FP. Rev.2.00 Sep 14, 2006 Renesas Technology
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Nippon capacitors CA94103-4813
Abstract: and line sides that meet the 15/14 or 14/15 ratios respectively. This applies for data mapping , 11 on page 14). s Asymmetric multiplex mode: SONET/SDH terminal with/without strong/weak FEC , Termination 14 Agere Systems Inc. TFEC0410G 40 Gbits/s Optical Networking Interface With Strong FEC , March 2001 Device Overview TPHASE_UP_[1-4] TPHASE_DW_[1-4] GPIO_[47-0] TTOAC_CLKI_[1-4] TTOAC_SYNCO_[1-4] TTOAC_DEN_[1-4] TTOAC_DATA_[1-4][3:0] TFRMLI[1-4] TCLK_LI Agere Systems
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STM-16 STM-64 Internal diagram of ic 7495 OTN SWITCH regenerator in optical 0936A STS-48 STS-48/ STS-192/STM-64 STS-48/STM-16 STS-192/
Abstract: . 14 12.0 Serial MICROWIRE Timing Diagram , . 17.12 REGISTER 14 , digital. Reference Clock Input Port 1 for PLL1. AC or DC Coupled. 5, 7, 8, 9 10 11 12 13, 14 15, 16 17 , SLEWFBCLKin/Fin 0.25 2.0 Vpp 0.15 0.5 V/ns www.ti.com 14 LMK04816 Symbol fPD1 , VOSCin-offset fdoubler_max PLL2 Reference Input (Note 14) PLL2 Reference Clock minimum slew rate on OSCin(Note Texas Instruments
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LMK04816BISQE LMK04816BISQ LMK04816BISQX K04816
Abstract: . 14 12.0 Serial MICROWIRE Timing Diagram , . 17.12 REGISTER 14 , . AC or DC Coupled. 5, 7, 8, 9 10 11 12 13, 14 15, 16 17 18 19, 20 21, 22 23 24 NC Vcc1 LDObyp1 , SLEWFBCLKin/Fin 0.25 2.0 Vpp 0.15 0.5 V/ns 14 Copyright © 1999-2012, Texas Instruments , ) Specifications fOSCin SLEWOSCin VOSCin VIDOSCin VSSOSCin VOSCin-offset fdoubler_max PLL2 Reference Input (Note 14 Texas Instruments
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PS 1025
Abstract: adjustable 25 ps step analog delay control. 14 differential outputs. Up to 26 single ended. - Up to 6 , . 14 12.0 Serial MICROWIRE Timing Diagram , . 17.12 REGISTER 14 , capacitor. 12 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1 uF capacitor. 13, 14 , (Note 26) AC coupled; 20% to 80%; (CLKinX_BUF_TYPE = 0) 0.15 www.national.com 14 0.5 National Semiconductor
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LMK04800 LMK04808 LMK0480X
Abstract: analog delay control. 14 differential outputs. Up to 26 single ended. - Up to 6 VCXO/Crystal buffered , . 14 12.0 Serial MICROWIRE Timing Diagram , . 17.12 REGISTER 14 , Number 1, 2 3, 4 6 5, 7, 8, 9 10 11 12 13, 14 15, 16 17 18 19, 20 21, 22 23 24 Name(s) CLKout0, CLKout0 , www.national.com 14 LMK04800 Family Symbol fPD1 Parameter PLL1 Phase Detector Frequency PLL1 Charge National Semiconductor
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Divide by N Counter SNAS489H
Abstract: . 19.12 REGISTER 14 , , 8, 9, 15, 17, 19 22, 47, 51, 55, 56, 60, 61, 64 3, 4 6 10 11 12 13, 14 16 18 20, 21 23 24 Name(s , 14 LMK04906 10.0 Absolute Maximum Ratings (Note 3, Note 4, Note 5) If Military/Aerospace , VOSCin-offset fdoubler_max PLL2 Reference Input (Note 14) PLL2 Reference Clock minimum slew rate on OSCin(Note Texas Instruments
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SQA64 LMK04906BISQE LMK04906BISQ LMK04906BISQX K04906
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