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CS3301-ISZR Cirrus Logic Geophone Low Noise, Programmable Gain Differential Amplifier
CS3301-ISR Cirrus Logic Geophone Low Noise, Programmable Gain Differential Amplifier
CS3302A-ISZR Cirrus Logic Hydrophone Low Noise, Programmable Gain Differential Amplifier
CS3302-ISR Cirrus Logic Hydrophone Low Noise, Programmable Gain Differential Amplifier
CS3302-ISZR Cirrus Logic Hydrophone Low Noise, Programmable Gain Differential Amplifier
HI1-0547/883 Intersil Corporation 8-CHANNEL, DIFFERENTIAL MULTIPLEXER

"differential via"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: focuses on high-speed point-to-point links, using LVDS (Low Voltage Differential Signaling) technology , / multipoint bus configuration was eliminated. The plug in card is connected to the load via a direct , differential has lessoned and the GETEK material has become more common in the industry. GETEK offers slightly , other papers to date. Noting that this is a Gigabit link, the Teradyne VHDM-HSD differential , . The SMA connectors on the top of the card provided the differential input to the test silicon which National Semiconductor
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54754A backplane design GETEK FR4 83484A modified booth circuit diagram PRBS-31 HP-13 N1020A
Abstract: Frequency Domain Analysis Differential Return Loss of standard via Differential Return Loss of microvia Differential Insertion Loss of microvia Differential Insertion Loss of standard via 17 , Differential Signaling Four Port Microvia Measurements Microvia Construction Modeling and Simulation Case , Backplane Connectors Are Advanced High Precision Molded Components Differential Signal Traces Surface Mount Terminals Double sided shield 5 Via Stubs Create Capacitive Loads 6 Connector to -
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prepreg FR4 LPKF FR4 Prepreg for RF PCB SMA Rosenberger rtk 32 FR4 Prepreg N1957B 86100C N1930A-010 N1930A-020
Abstract: possible. VIA+, VIB+ 1, 13 8, 9 Differential non-inverting inputs. VIA-, VIB- 9, 12 7 , ­0.7 V Differential input voltage, VIA+ ­ VIA- , VIB+ ­ VIB- 12 V Input voltage at LEA, LEB , Differential Analog Inputs VIA+, VIA-, VIB+, VIBVIA+, VIAAbsolute Input Voltage VIB+, VIB(Input Common Mode , -5.2V ±5%, TA = 25°C. Symbol Parameters Test Conditions Min. Differential Analog Inputs VIA , (Latch & Disable) VIA+, VIA- Absolute Input Voltage VID Differential Range ID -2.0 Raytheon
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RC73687 RC73687NE RC73687QC RC73687MK DS30073687
Abstract: Preliminary Information Low Voltage 1:22 Differential HSTL Clock Fanout Buffer The Motorola MC100ES8223 is a bipolar monolithic differential clock fanout buffer. Designed for the most demanding clock distribution , differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very , . Features · 1:22 differential clock fanout buffer MC100ES8223 LOW­VOLTAGE 1:22 DIFFERENTIAL HSTL CLOCK , operation1 of clock or data signals 1.5V HSTL compatible differential clock outputs PECL and HSTL compatible Motorola
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MC100ES8223/D MC100EP223 JESD51-6 JES51-6
Abstract: Preliminary Information Low Voltage 1:22 Differential HSTL Clock Fanout Buffer The Motorola MC100ES8223 is a bipolar monolithic differential clock fanout buffer. Designed for the most demanding clock distribution , differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very , . Features · 1:22 differential clock fanout buffer MC100ES8223 LOW­VOLTAGE 1:22 DIFFERENTIAL HSTL CLOCK , operation1 of clock or data signals 1.5V HSTL compatible differential clock outputs PECL and HSTL compatible Motorola
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Abstract: /D Rev 0, 11/2001 Preliminary Information Low Voltage 1:22 Differential HSTL Clock Fanout Buffer The Motorola MC100ES8223 is a bipolar monolithic differential clock fanout buffer. Designed for the , the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics , , networking and telecommunication systems. Features · 1:22 differential clock fanout buffer MC100ES8223 Freescale Semiconductor
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Abstract: . Figure 3 shows the cross-talk between the differential pairs for a square via field and for a staggered , ) (b) Figure 12: (a) Impact of the via pad size on the differential impedance (for a 10-90 % rise , performance. Figure 12 shows the impact of the via 8 pad size on the differential impedance (for a 10-90 , issues. Figure 16 shows the impact of reducing the via hole size on the differential impedance (for a , 16: Impact of reducing the via hole size on (a) the differential impedance (for a 10-90 % rise time -
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PCI express PCB footprint datasheet of BGA Staggered pins Geest via antipad pitch
Abstract: + 1, 13 8, 9 Differential non-inverting inputs. VIA-, VIB- 9, 12 7, 10 Differential , +0.7 Input voltage at VIA+, VIB+ Input Voltage at VIA-, VIB- V V VEE­0.7 V Differential input , Parameters Digital Inputs (Latch & Disable) VIA+, VIAAbsolute Input Voltage VID ID Differential Range , °C. Symbol Parameters Test Conditions Min. Differential Analog Inputs VIA+, VIA-, VIB+, VIBVIA , Description · 12 V max differential input voltage (for VCC = +10V, VEE = -5.2V) · Low propagation delays Fairchild Semiconductor
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CLEA 004
Abstract: · Two AD8138 differential amplifiers · One P174FCT digital buffer GENERAL DESCRIPTION , INPUTS OR FOUR DIFFERENTIAL/PSEUDO DIFFERENTIAL PAIRS DB0 TO DB11 DATA BUS VIN1 CONTROL , Differential Mode . 8 Taking Samples , Software Configuration Files: . 20 Pseudo Differential , source of the VDD +5 V supply used to supply the AD8138 differential amplifiers. In Position A, the VDD Analog Devices
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AD7938 AD7939 AD7938-6 AD780 AD713 AD8022 LK37 LK46 specifications dso lk61 lk59 smd lk58 12-/10-B
Abstract: possible. VIA+, VIB+ 1, 13 8, 9 Differential non-inverting inputs. VIA-, VIB- 9, 12 7 , ­0.7 V Differential input voltage, çVIA+ ­ VIA- ç, çVIB+ ­ VIB- ç 12 V Input voltage at LEA , , TA = 25°C. Symbol Parameters Differential Analog Inputs VIA+, VIA-, VIB+, VIBVIA+, VIAAbsolute , Test Conditions Min. Differential Analog Inputs VIA+, VIA-, VIB+, VIBVIA+, VIAVIB+, VIB , Delay Features Description ¥ 12 V max differential input voltage (for VCC = +10V, VEE = -5.2V Raytheon
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Abstract: the standard via, this is related to the length of the via stub. Figure 13 Differential Eye , connectors, via stubs and routing of traces create challenges for controlling the excess reactance , differential pairs, spacing of contacts, and selection of component materials all play key roles in the , modeling of these types of connectors before the first piece of steel is cut. Figure 3 Via Stubs Create Capacitive Loads It is essential to reduce the amount of via stub to successfully transmit data -
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8B10B reflectometer SDD11 SDD21 Signal Path Designer
Abstract: must be supplied from an external source via J5. Selects which single-ended to differential converter , to VIN- via P6, either for differential or single-ended operation. In Position B, VIN- is supplied , differential amplifier. They are also connected to the VDD supply of the AD7452 via LK3. Analog -5 V Supply , Evaluation Board for Differential Input, 12-Bit ADC with a Serial Interface EVAL-AD7452 FEATURES , , single-ended to differential conversion Various linking options PC software for control and data analysis Analog Devices
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single-ended to differential conversion AD7452BRT analog devices ics ad7452brt LK27 LK18 AD7802 AD713JN AD78022AR AD780AR AD8138AR SD103C SD103CDITB-ND
Abstract: connect via included, traces and test points calibrated out 4 MultiGig RT-2 7-Row Differential DC , (500 mV differential) 0.063" Thick boards, Bottom layer connect via included 5 MultiGig RT-2 7 , aggressors (500 mV differential) 0.063" Thick boards, Bottom layer connect via included 6 MultiGig RT , -row Connector with Differential Wafers Report #25GC001 Rev 2 - 02/28/2006 This document provides the test , , Harrisburg, PA All Rights Reserved MultiGig RT-2 7-Row Differential BP Footprint Row A 1.8 mm Row Tyco Electronics
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MULTIGIG RT2 CONNECTOR 1410189-1 d9e9 vita 46 vita 1410187-1
Abstract: PI90LV02/PI90LVT02 SOTinyTM LVDS High-Speed Differential Line Receiver Features · Meets , Interfaces to LVDS, LVPECL · Bus-Terminal ESD exceeds 10kV · Differential Input Voltage Threshold less than , single differential line receivers that use low-voltage differential signaling (LVDS) to support data , consumption, low-noise generation, and a small package. A differential input signal (350mV) is translated by , Differential Line Receiver Pericom Semiconductor
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L6 marking 5-pin MARKING L6 5PIN TIA/EIA-644-1995 PI90LVT02 PI90LV02 PS8659C 3ODVWLF3DFNDJH627 PI90LV02TEX
Abstract: in. A differential via on one of the high speed I/Os on the Stratix GX board was modeled. For this , only 93 mils long (the board is 93 mils thick). Figure 8. Differential via structure as modeled in , system parasitics. Transmission line and via models have been validated using laboratory measurements , covers circuit via modeling using three-dimensional EM simulation to extract HSPICE netlists. SMA , model were connected to the board transmission line, via and the board SMA. It was then connected to a -
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harbour industries 27478 M17/128-rg400 fr4 rlgc SMA Connector Spice hmzd connector harbour industries 27478 SMA CF-031505-1
Abstract: an optimized via for better high edge-rate signal transmission. Standard Differential Via Altera Corporation AN-529-1.0 Figure 1 shows the construction of a typical differential via in a , anti-pad clearance. In this via, 100- differential traces enter the vias on layer 1 and exit on layer 6 , . Standard Differential Via Altera built a test board and constructed Ansoft HFSS simulation models for , Differential Via Table 1 shows the dimensions used in the construction of this differential via. The via Altera
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hfss hfss tdr ansoft hfss
Abstract: of Differential Insertion Loss of Via Transitions with and without Stub A simple serial channel is , shows similar differential insertion loss for a channel with ideal via (no stub) and a channel with a , the void region surrounding a via pad. Figure 18 shows two differential pairs that are routed between , consists of a backplane and two daughter cards. Two sections are connected via 3-foot low-loss SMA cables , is 10.3125 Gbps. The magnitude of the output differential signal is 0.8 V with optimized Altera
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AN-596-1 NELCO-4000-13 HFTA-05 pcb fabrication process Nelco4000-13 Nelco-4000
Abstract: PI90LV02/PI90LVT02 SOTinyTM LVDS High-Speed Differential Line Receiver Features · Meets , Interfaces to LVDS, LVPECL · Bus-Terminal ESD exceeds 10kV · Differential Input Voltage Threshold less than , -pin space-saving SOT-23 (T) Description The PI90LV02 and PI90LVT02 are single differential line receivers that use low-voltage differential signaling (LVDS) to support data rates up to 400 Mbps. These products are , package. A differential input signal (350mV) is translated by the device to a 3.3V CMOS output level. The Pericom Semiconductor
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marking L5 PS8659A PI90LV02TX PI90LVT02TX
Abstract: SOTinyTM LVDS High-Speed Differential Line Receiver Features Description · Meets or , Interfaces to LVDS, LVPECL · Bus-Terminal ESD exceeds 10kV · Differential Input Voltage Threshold less than , single differential line receivers that use low-voltage differential signaling (LVDS) to support data , consumption, low-noise generation, and a small package. Logic Diagram Pinout A differential input , PS8659C 10/30/09 PI90LV02/PI90LVT02 SOTiny LVDS High-Speed Differential Line Receiver TM Pericom Semiconductor
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LVT02 PI90LV01 PI90LVB01 SOT-23 code L5 PI90LVT02TEX
Abstract: SOTinyTM LVDS High-Speed Differential Line Receiver Features Description · Meets or , Interfaces to LVDS, LVPECL · Bus-Terminal ESD exceeds 10kV · Differential Input Voltage Threshold less than , Packages: 5-pin space-saving SOT-23 (T) The PI90LV02 and PI90LVT02 are single differential line receivers that use low-voltage differential signaling (LVDS) to support data rates up to 400 Mbps. These , , and a small package. Logic Diagram Pinout A differential input signal (350mV) is translated Pericom Semiconductor
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PS8659
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