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Part Manufacturer Description PDF & SAMPLES
ISL59923IRZ-EVALZ Intersil Corporation Evaluation Board for ISL59923 Video Delay Line
ISL59922IRZ-EVALZ Intersil Corporation Evaluation Board for ISL59922 Video Delay Line
ISL59921IRZ-EVALZ Intersil Corporation Evaluation Board for ISL59921 Video Delay Line
EL9115ILZ Intersil Corporation Triple Analog Video Delay Line; QFN20; Temp Range: -40° to 85°C
EL9115ILZ-T7 Intersil Corporation Triple Analog Video Delay Line; QFN20; Temp Range: -40° to 85°C
ISL59920IRZ-T7 Intersil Corporation Triple Analog Video Delay Line; QFN20; Temp Range: -40° to 85°C

"delay line"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 1. Correlation of Schematic and Trace Reports Path in Figure 1 Line in Figure 2 Delay A to , compensation of 0.097 ns, shown in line 121, is the delay of the PLL (actually only a portion of it, since the , 3 Line in Figure 4 Delay A to B Line 230 1.480 ns B to C Line 231 1.730 ns , ns, shown in line 221, is the delay from the input of the PLL to the outputs of the clock tree. · The clock-to-out delay of 8.491 ns, shown in line 222, exceeds (fails) the specified 7.000 ns Lattice Semiconductor
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SIGNAL PATH DESIGNER TN1011 TN1014 1-800-LATTICE
Abstract: 1. Correlation of Schematic and Trace Reports Path in Figure 1 Line in Figure 2 Delay A to , feedback compensation of 0.097 ns, shown in line 121, is the delay of the PLL (actually only a portion of , delay of 11.657 ns, shown in line 122, exceeds (fails) the specified 7.000 ns requirement. 3 , Report Path in Figure 3 Line in Figure 4 Delay A to B Line 230 1.480 ns B to C Line , compensation of 3.263 ns, shown in line 221, is the delay from the input of the PLL to the outputs of the clock Lattice Semiconductor
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Abstract: 3D7324 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7324) FEATURES â'¢ â'¢ â'¢ â'¢ â , Delay Line product family consists of fixeddelay CMOS integrated circuits. Each package contains four , is offered in a space saving surface mount 14-pin SOIC. Delay Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 4 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output Delay Line 4 Output +5 Volts Ground No Connection TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER Data Delay Devices
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3D7324D- 74LS-
Abstract: 3D7323 MONOLITHIC TRIPLE FIXED DELAY LINE (SERIES 3D7323) FEATURES · · · · · · · · · , The 3D7323 Triple Delay Line product family consists of fixed-delay CMOS integrated circuits. Each , delay lines. It is offered in a space saving surface mount 8-pin SOIC. Delay Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output +5 , 3D7323Z-500 3D7323Z-1000 3D7323Z-2000 3D7323Z-5000 3D7323Z-6000 DELAY PER LINE (ns) 6 ± 1.0 8 ± 1.0 Data Delay Devices
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3D7323Z 3D7323Z-6
Abstract: . Passive Delay Line Schematic Diagram. General: The Passive Delay Modules offered by Rhombus Industries , delay line, is measured from the 10% to 90% points of the leading edge of the output pulse. The , the delay line ( tr ): These delay modules are offered in standard impedance values of 50, 75, 100 , for all modules is -65 to +150OC. An analog delay line's bandwidth (-3dB attenuation) is related , Attenuation: The output voltage attenuation of a delay line has several contributing factors: Design: A Rhombus Industries
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125OC analog delay line schematic passive delay line Delay Modules
Abstract: Passive Delay Line Design Considerations Operating Specifications - Passive Delays Pulse , . -65O to +150OC A Passive Delay Line is a special purpose Low Pass Filter designed to delay , Reflection (%) = 1 - (1 / (1 + Zo/2RL) Figure 1A. Passive Delay Line Schematic Diagram. In certain , whose bandwidth is compatible with the intended range of operation for the delay line. A specific delay , / tr)1.36 Attenuation: The output voltage attenuation of a delay line has several contributing Rhombus Industries
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analog delay line Analog Delay Lines Characteristic impedance matching delay line 100VDC
Abstract: 3D7444 MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444) FEATURES x x x x x , , versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed via the serial interface , as per user selection. For each line, the delay time is given by: I1-I4 O1-O4 AL SC SI SO , of the n-th line and TI is the delay increment (dash number). The desired addresses are shifted into , interface can also be used to enable/disable each delay line. The 3D7444 operates at 5 volts and has a Data Delay Devices
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SOIC-14 3D7444-10 3D7444-2 3D7444-4 3D7444-5 3D7444-8 0C-70C 3D7444D- DIP-14 3D7444-
Abstract: 3D3324 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D3324) FEATURES â'¢ â'¢ â'¢ â'¢ â , DESCRIPTION PIN DESCRIPTIONS The 3D3324 Quadruple Delay Line product family consists of fixeddelay CMOS , in a space saving surface mount 14-pin SOIC. Delay Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 4 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output Delay Line 4 , 3D3324D -200 3D3324D -500 3D3324D -1000 3D3324D -2000 3D3324D -5000 3D3324D -6000 DELAY PER LINE Data Delay Devices
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3D3324D-
Abstract: 3D7304 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7304) FEATURES · · · · · · · · , , click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D7304 Quadruple Delay Line product , 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC. Delay Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 4 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output Delay Line 4 Output +5 Volts Ground No Connection TABLE 1: PART NUMBER Data Delay Devices
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3D7304D- 3D7304- 3D7304G-
Abstract: 3D7324 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7324) FEATURES · · · · · · · · , here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D7324 Quadruple Delay Line product family , surface mount 14-pin SOIC. Delay Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 4 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output Delay Line 4 Output +5 Volts , 3D7324D-500 3D7324D-1000 3D7324D-2000 3D7324D-5000 3D7324D-6000 DELAY PER LINE (ns) 6 ± 1.0 8 ± 1.0 Data Delay Devices
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3D7324D-6
Abstract: 3D7304 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7304) FEATURES â'¢ â'¢ â'¢ â'¢ â , Delay Line product family consists of fixeddelay CMOS integrated circuits. Each package contains four , Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 4 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output Delay Line 4 Output +5 Volts Ground No Connection TABLE 1 , -40 -40 -50 -50 -100 -100 -200 -200 -300 -300 -400 -400 -500 -500 DELAY PER LINE (ns Data Delay Devices
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Abstract: 3D7314 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7314) FEATURES x x x x x x x x , , click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D7314 Quadruple Delay Line product , 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC. Delay Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 4 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output Delay Line 4 Output +5 Volts Ground No Connection TABLE 1: PART NUMBER Data Delay Devices
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3D7314D 3D7314G 3D7314D- 3D7314- 3D7314G-
Abstract: 3D3324 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D3324) FEATURES · · · · · · · · , DESCRIPTIONS The 3D3324 Quadruple Delay Line product family consists of fixeddelay CMOS integrated circuits , surface mount 14-pin SOIC. Delay Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 4 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output Delay Line 4 Output +3.3 Volts , 3D3324D -1000 3D3324D -2000 3D3324D -5000 3D3324D -6000 DELAY PER LINE (ns) 10 ± 1.0 15 ± 1.0 Data Delay Devices
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3D3324D-10
Abstract: 3D3323 MONOLITHIC TRIPLE FIXED DELAY LINE (SERIES 3D3323) FEATURES · · · · · · · · · , . FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D3323 Triple Delay Line product family consists of , offered in a space saving surface mount 8-pin SOIC. Delay Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output +3.3 Volts Ground No , -1000 3D3323Z -2000 3D3323Z -5000 3D3323Z -6000 NOTE: DELAY PER LINE (ns) 10 ± 1.0 15 ± 1.0 Data Delay Devices
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3D3323Z-10
Abstract: 3D7304 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7304) data\ , FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D7304 Quadruple Delay Line product family consists of , Delay Line 1 Input I2 Delay Line 2 Input I3 Delay Line 3 Input I4 Delay Line 4 Input Ol Delay Line 1 Output 02 Delay Line 2 Output 03 Delay Line 3 Output 04 Delay Line 4 Output VCC +5 Volts GND Ground N/C No Connection TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER DELAY PER LINE (ns) INPUT -
OCR Scan
74ls* for delaying output Digital Delay Line 3D7304G 3D7304D 470S2 Q001200
Abstract: 3D7304 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7304) data delay aevices.v inc. 3D7304 DIP , DESCRIPTION The 3D7304 Quadruple Delay Line product family consists of fixed-delay CMOS integrated circuits , en m VDD 3D N/c 3D 01 ID N/C m 02 m 03 m 04 3D7304D SOIC (150 Mil) PIN DESCRIPTIONS 11 Delay Line 1 Input I2 Delay Line 2 Input I3 Delay Line 3 Input I4 Delay Line 4 Input Ol Delay Line 1 Output 02 Delay Line 2 Output 03 Delay Line 3 Output 04 Delay Line 4 Output VCC +5 Volts GND Ground N/C No Connection -
OCR Scan
Abstract: -202. All units are manufactured as M IL-GRADE. D ESIG N A passive delay line is a special purpose Low Pass , digital signals whose bandwidth is compatible with the intended range of opera tion for the delay line. A , 14 11 13 12 8 10 14 15 15 RISE T IM E The rise time of a delay line, measured from the 10% to 90 , input rise time ( trj ) and the true rise time of the delay line ( tr ): Td = Total Delay ( ns ) Zo = , delay line's bandwidth is a function of the network's rise time which is determined by the total nu mber -
OCR Scan
MILD-23859 IL-D-83531 PASSIVE-S/93
Abstract: bel/defining a degree of excellence DELAY LINE MEASURING TECHNIQUES DEFINITIONS DELAY AND IMPEDANCE (Td & Zo) The delay time and impedance of a delay line may be expressed as: Zo = v7L t/C t where: Hf- RISE TIME (Tr) The rise time of a delay line may be ex pressed as: Tr = v 'T ro 2 -Tri2 where: Tr = Network Rise Time Tri = Input Rise time Tro = Output Rise Time The band width of the delay line , figure of merit of a delay line. The amount of inductance and capaci tance assigned to each section of a -
OCR Scan
Abstract: 3D7314 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7314) FEATURES · · · · · · · · , , click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D7314 Quadruple Delay Line product , 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC. Delay Line 1 Input Delay Line 2 Input Delay Line 3 Input Delay Line 4 Input Delay Line 1 Output Delay Line 2 Output Delay Line 3 Output Delay Line 4 Output +5 Volts Ground No Connection TABLE 1: PART NUMBER Data Delay Devices
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TTL 74LS 00
Abstract: Passive Delay Line Design Considerations A Passive Delay Line is a special purpose Low Pass Filter , intended range of operation for the delay line. A specific delay and impedance, determine the required LC , passive delay line applications: Rt = Zo 1) 0 Ct/2N_j_ rvm nrm mm nnm CWÜ_]_ ,T Td = / 1 1 J_L C t / 2 N 1 T T TT T T , Td = Total Delay ( ns ) Z0 = Impedance ( Ohms ) Lt = Total Line , _ Rise Time: The rise time of a delay line is typically measured from the 10% to 90% points of the -
OCR Scan
PASSIVE TV DELAY LINE
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