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"decompression compression"

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Abstract: . . . . . . . . . . . .32 7.1 Basic Compression/Decompression Example . . . . . . . . . . . . . . . , compression/decompression program. Section 4.0: Discusses the use of internal FIFOs. Programming , , compression operation of one record, decompression of one record and simultaneous compression and , intended for systems that only need decompression in hardware. The compression is done either in software , Printers Host Printers (Rasterization & AHA3422 AHA3422 Decompression only device, 16 MB/s compression done at ... Advanced Hardware Architectures
Original
datasheet

48 pages,
817.6 Kb

R3000 Motorola ColdFire 5202 MCF5102 AHA3431 AHA3430 AHA3422 AHA3411 AHA3410 TEXT
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Abstract: Compression/ Decompression Coprocessor IC Advanced Hardware Architectures, Inc. 2365 NE Hopkins Court Pullman , single chip CMOS VLSI coprocessor device that implements a lossless compression and decompression , device supports simultaneous compression and decompression operations at 25 MBytes/sec each. The device , MB/sec compression and decompression rates • 100 MB/sec burst data rate over a 32-bit data bus â , decompression operation at full bandwidth • Average 13 to 1 compression performance for bitmap image data ... OCR Scan
datasheet

53 pages,
3865.19 Kb

AHA3410B 16X32 WA99163-S601 TEXT
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Abstract: .7 Compression & Decompression Histories .8 7.1 History , hardware New in version 4 · Independent compression and decompression histories · Independent compress , the compression and decompression modules. LZSCL.S - This little-endian source file contains the , several common functions required by both the compression and decompression modules. LZSCB.S - This , ratio can be adjusted for optimal CPU performance. 7 Compression & Decompression Histories This ... Hifn
Original
datasheet

16 pages,
103.49 Kb

DS-0007-00 LZS221-960 TEXT
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Abstract: DATA COMPRESSION / DECOMPRESSION COPROCESSOR IC 90 89 88 87 86 85 84 83 82 81 80 79 78 , CMOS VLSI device that implements a lossless compression and decompression algorithm. The algorithm , compression and decompression operations at 25 MBytes/sec each. A Non-muxed microprocessor interface , D10 D9 D8 D7 FEATURES PERFORMANCE: · 25 MBytes/sec compression/decompression rates · 100 , out ports · Simultaneous compression/decompression operation at full bandwidth · Average 13 to 1 ... Comtech AHA
Original
datasheet

4 pages,
186.11 Kb

Comtech Aha date code AHA3410C-025 AHA3410C TEXT
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Abstract: COMPRESSION / DECOMPRESSION COPROCESSOR IC 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 , implements a lossless compression and decompression algorithm. The algorithm exhibits an average , 25 MBytes/sec compression/decompression rates · 100 MBytes/sec burst data rate over a 32-bit data , /decompression operation at full bandwidth · Average 13 to 1 compression ratio for bitmap image data , Single chip compression/decompression solution No external SRAM required Four 16 x 32-bit FIFOs ... Advanced Hardware Architectures
Original
datasheet

4 pages,
763.05 Kb

AHA3410C-025 AHA3410C TEXT
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Abstract: out ports • Simultaneous compression and decompression at full bandwidth • Average 15 to 1 , decompression engines • Counter checks errors in decompression SYSTEM INTERFACE: • Single chip compression , /Out 32 Data Port 16x32 Compression Data In/Out 16 Data Port 16 x 16 Decompression Data In/Out 32 Data , compression or decompression is performed using synchronous DMA over the 32-bit data port. The Video ports , compression or decompression is synchronous over the three data ports functioning as DMA masters. To initiate ... OCR Scan
datasheet

50 pages,
4102.15 Kb

R3000 Am29k AHA3411 IDT3081 ANDC13 AHA3410 TEXT
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Abstract: .8 Compression & Decompression Histories .9 8.1 History , library supports the simultaneous use of multiple compression and decompression histories. Each history is , faster modes Independent compression and decompression histories Independent compress and decompress , contains several common functions required by both the compression and decompression modules. LZSC.A - , turned on. Figure 1 lists the approximate speeds of compression and decompression over a range of 68K ... Hifn
Original
datasheet

15 pages,
107.27 Kb

LZS221-68 TEXT
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Abstract: coprocessor device that implements a lossless compression and decompression algorithm. The algorithm exhibits , compression and decompression operations at 25 MBytes/sec each. The device interfaces directly to various RISC and CISC processors from AMD, Intel and Motorola. Compression and decompression data transfers , MB/sec compression and decompression rates • 100 MB/sec burst data rate over a 32-bit data bus â , decompression operation at full bandwidth • Average 13 to 1 compression performance for bitmap image data ... OCR Scan
datasheet

47 pages,
3502.68 Kb

PS3410C-0197 i960CX ADVANCED HARDWARE ARCHITECTURES dsc-100 DDD11 D2553 TEXT
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Abstract: .8 Compression & Decompression Histories .8 8.1 History , compression and decompression histories. Each history is completely independent of other histories. In , compress and decompress modules Special faster modes Independent compression and decompression histories , contains several common functions required by both the compression and decompression modules. LZSC.ASM - , optimization switches turned on. Figure 1 lists the approximate speeds of compression and decompression over a ... Hifn
Original
datasheet

15 pages,
108.36 Kb

motorola 386 cpu 80486dx2-66 2156 compressor LZS221-386 TEXT
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Abstract: and video out ports · Simultaneous compression and decompression at full bandwidth · Average 15 to , through compression and decompression engines · Counter checks errors in decompression SYSTEM INTERFACE: · Single chip compression/decompression solution ­ no external SRAM required · Four 16 × 32 , Compression Data In/Out Decompression Data In/Out Decompression Data In/Out Decompressed Data Out 8 32 , compression or decompression is performed using synchronous DMA over the 32-bit data port. The Video ports ... Advanced Hardware Architectures
Original
datasheet

55 pages,
866.01 Kb

R3000 MO-108 IDT3081 AHA3411A-033 AHA3411 ANDC13 ADVANCED HARDWARE ARCHITECTURES TEXT
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Intel 22/04/1999 744.74 Kb ZIP jpegsr6b.zip