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Part : C/NEW DATA ISO Supplier : Keithley Instruments Manufacturer : Newark element14 Stock : - Best Price : $171.00 Price Each : $171.00
Part : ICOMP-DATA-IN Supplier : Black Box Manufacturer : Newark element14 Stock : - Best Price : - Price Each : -
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Abstract: 4 DIO 5 D11 6 D12 40 -0.4 -1000 2.4 Part of 16 Bit TRI-STATE I/O 7 DATA , 42 D7 40 -0.4 -1000 2.4 Part of 16 Bit TRI-STATE I/O 43 DATA SELECT 2 20 -0.4 A LOW on this input , I/O 49 LATCH DATA 2 20 -0.4 A HIGH on this input allows the I/O data on D0 â'" D7 to , last state. 50 D4 40 -0.4 -1000 2.4 Part of 16 Bit TRI-STATE I/O 51 LOAD DATA 2 60 -1.2 A LOW on , allows the I/O data on D8 â'" D15 to appear at the output of the FIRST RANK XMT REG. A LOW on this -
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MCT1555-3 TFD2747 MCT3231 MCT3232 IL-STD-1553 MARCONI ELECTRONIC marconi lc 28 IL-STD-1553A MCT-1553-3 MIL-STD-1553
Abstract: pages ï'´ 1024blocks. The device has a 2176-byte static registers which allow program and read data to , TC58NYG0S3HBAI6is a serial-type memory device which utilizes the I/O pins for both address and data input/output as , Control circuit to Column decoder I/O8 Command register Data register Row address buffer , Data Setup Time 12 ï'¾ ns tDH Data Hold Time 5 ï'¾ ns tWC Write Cycle , ï'¾ 25 s tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) ï'¾ 25 Toshiba
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TC58NYG0S3HBAI6 2012-08-31C
Abstract: Sheet Active S, B, I, E S, B, I, E S, B, I, E S, B, I, E S, B, I, E Data Sheet Data Sheet Data Sheet Data Sheet Data Sheet Active Active Active Active Active S, B, I, E S, B, I, E K, H, I, E K, H, I, E S, B, I, E K, H, I, E K, H, I, E Data Sheet Data Sheet Data Sheet , , RT RS 32 32 40 32 96 100 V, Q, S, B, E, I SMD / Data Sheet V, Q, S, B, E, I SMD / Data Sheet K, H, I, E Data Sheet K, H, I, E Data Sheet K, H, I, E Data Sheet Active Active Maxwell Technologies
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SCS750 9240LP 7805ALP 7809LP 54LVTH162240 ADC hard radiation EEPROM 16MB HSN-3000 79LV2040 54BCT244 54BCT245
Abstract: '¢ Serial data I/O supports CCB format communication with the system controller. â'¢ Direct display of , this pin. â'" I/O Vdo CE CL Dl DO 34 35 36 33 Serial data interface connections to the controller , : Synchronization clock Dl: Transfer data DO: Output data H I I I GND O Open TEST 27 This pin must be , ai Az A3«-Display data-Fixed data-*dd: I A11078 Note: BO to B3 and AO to A3.CCB , . bo bi B2 B3 AO ai A2 A3 *-Display data- Control data - DO i-1 L -
OCR Scan
LC75893M A1109 KS-1 capacitor ENN5971A 3204-MFP36S MFP36S 420TIS
Abstract: GSTROBE, these values are passed to the control latches. In this mode, data from I[0] is switched to Z[0] data from I[1] is switched to Z[1], etc. The input address values at D[4:0] and the output address values at A[4:0] are ignored in FlowThru Mode. All data input and output signals (I+/I[0:31], Z+/Z-[0:31 , Waveforms Figure 1: Normal Data Flow Timing Minimum Input Pulse Width & Propagation Delay TPW I+ [0:31 , ECL ECL ECL ECL I/O I I I I I Level ECL ECL ECL ECL ECL Serial data in Serial data in Serial Vitesse Semiconductor
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VSC851 32X32 G52167-0 VSC851-FX
Abstract: memory data storage. FEATURES ï'· Organization Memory cell array Register Page size Block size , buffer I/O Control circuit to Column decoder I/O8 Command register Data register , Time 5 ï'¾ ns tDS Data Setup Time 12 ï'¾ ns tDH Data Hold Time 5 ï , Array to Starting Address ï'¾ 25 s tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) ï'¾ 25 s tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah) ï Toshiba
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TC58NVG0S3HBAI4 2012-10-01C
Abstract: memory data storage. FEATURES ï'· Organization Memory cell array Register Page size Block size , Time 5 ï'¾ ns tDS Data Setup Time 12 ï'¾ ns tDH Data Hold Time 5 ï , Array to Starting Address ï'¾ 25 s tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) ï'¾ 25 s tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah) ï , tPROG Average Programming Time ï'¾ 300 700 s tDCBSYW2 Data Cache Busy Time in Toshiba
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TC58NVG0S3HTAI0
Abstract: memory data storage. FEATURES ï'· Organization Memory cell array Register Page size Block size , buffer I/O Control circuit to Column decoder I/O8 Command register Data register , Time 5 ï'¾ ns tDS Data Setup Time 12 ï'¾ ns tDH Data Hold Time 5 ï , Array to Starting Address ï'¾ 25 s tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) ï'¾ 25 s tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah) ï Toshiba
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TC58NYG0S3HBAI4
Abstract: 40 39 3$ 37 36 35 34 33 segâ'ž ' seg50 i osc, ' oscj ' Vod 1 Vss' Vlcd1 ce i scl i data ' mode i , [:i_ DATA_I Mode 1 Data I_I Data Block 1 I_ MODE I I_ Example 2(Mode 2): Write to Shift-register 2(51 to 100-bit) CE I LJ scl_i:]_t: DATA_I Mode 2 Data I_I Data , SCL DATA MODE LJ :i_[: Mode 3 Data I Data Block 3 Example 4(Mode 4): Write to Shift-register 4(151 to 200-bit) CE_J LJ SCL I .1 DATA_I Mode 4 Data I_I Data Block 4 MODE I I_ Example 5 -
OCR Scan
NJU6433 NJU6433F SCL 1058 ID48 1D45 dios hex to 7 segment decoder 200-S 5-888-N SEG32 SEG30
Abstract: TX DATA P I TXOATAS - rJ RX DATAS HV DATA s WRAP AROUND SWITCH -dp G-D FAILSAFEP FAILSAFE S Ig ,   CHANP/S «OUTENA «EKiCEKIÃ' _SQENAS "SERIAL DATA OUT Figure 1 : Block Diagram (Partial) I This , command Subaddress or Mode code mode command Bidirectional data I/O buffers. Interfacing with the , transmit Buffer Registers become transparent. Therefore, data on the subsystem I/O appears at the output of , available on the DO to D15 I/O bus by setting DATA SELECT lines low. Word parity is checked for after all -
OCR Scan
ARX2441 HCT86 manchester code encoder diagram state MIL-STD-883 MIL-STD-1553A 1-800-THE-1553
Abstract: memory data storage. FEATURES ï'· Organization Memory cell array Register Page size Block size , buffer I/O Control circuit to Column decoder I/O8 Command register Data register , Time 5 ï'¾ ns tDS Data Setup Time 12 ï'¾ ns tDH Data Hold Time 5 ï , Array to Starting Address ï'¾ 25 s tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) ï'¾ 25 s tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah) ï Toshiba
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TC58NVG1S3HTA00 2013-01-18C
Abstract: pages ï'´ 2048blocks. The device has two 4320-byte static registers which allow program and read data , TC58NYG2S0F is a serial-type memory device which utilizes the I/O pins for both address and data input/output , 12 ï'¾ ns tALH ALE Hold Time 5 ï'¾ ns tDS Data Setup Time 12 ï'¾ ns tDH Data Hold Time 5 ï'¾ ns tWC Write Cycle Time 25 ï'¾ ns tWH , Data Cache Busy in Read Cache (following 31h and 3Fh) ï'¾ 30 s tDCBSYR2 Data Cache Toshiba
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TC58NYG2S0FBAI4
Abstract: Motorola High­Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ , MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Bus Transceivers and D Flip-Flops , status of the Data­Source Selection pins, data may be routed to the outputs either from the flip­flops , or both of the ports are in the high­impedance state, these I/O pins may be used as inputs to the D flip­flops for data storage. The user should note that because the clocks are not gated with the Direction Motorola
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DL129 751E HC646 HC648 MC74HCXXXN TBA 1285 MC54/74HC646 LS646 MC54/74HC646/D
Abstract: command Subaddressor Mode code mode command Bidirectional Data I/O Buffers. Interfacing with the internal , subsystem I/O appears at the output of the transmit buffer register. With LATCH DATA held low, stable data , 1 r SEND DATA & LOAD DATA - lxx> u -fh LATCH DATA 4 -I -TE 9 -TE r -TE 8 â'¢ TE 7 , low-to-high transition of TAKE DATA. This data is made available in the DO to D15 I/O bus by setting DATA , and DATA SELECT 1 are activated to enable data in the receive registers onto the I/O bus (D0-D15). -
OCR Scan
BUS-65102 differential manchester encoder MIL-C-3098/42
Abstract: to 16 devices. 8) 8-bit Flash Data I/O. 9) Two-port Flash operation support. 5. MMC-Port for MMC , Host Data Bus 7 Micro-processor Address Bus 13 Host Data Bus 15 Host I/O VCC Card Enable 1. (Pull , Data Bus 8 Host Data Bus 0 Micro-processor Address Bus 3 Host Data Bus 9 Host Data Bus 1 I/O VCC Micro-processor Address Bus 2 Host Data Bus 10 Host Data Bus 2 Memory: Card is Write Protected PC Card I/O: Host Data I/O is 16-bit. IDE: Host Data I/O is 16-bit. Should be connected to I/O GND Should be Key Technology
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FC1304TU TQFP128-2 mmc micro SD socket usb read write toshiba Micro SD KTC-FC130 usb to sd card smartmedia ecc KTC-FC1304TU 1304TU TQFP128-1
Abstract: ^ ki fW c uWt i w o c Wu i t Wo C o 5-917 NJU6436 (2) Data Input Format ·Two kind of data , » |Dao~ "L" LEVEL Data Block 2 : from SEGi«, COHi to SEGao, COM« CE scl J L f i n f i n n n , Di 20 Diti Di?« Di t 7 Di 7» IDi 7 » I Di ao "L" LEVEL Data Block 4 : from SEG«a , ; O Data Block 2 O O ; ! Di i 7 Due Di 1« Di 2 0 Dl 2 1 Di 22 Dl 23 Dl 24 ) ; 0 · > CD , Data Block 4 · I SEGes · j O O I D 237 Ô 2SS &2S« &240 O O NauQapanRadio -
OCR Scan
KS 110 16 X 2 LCD Panel Display NJU6436F
Abstract: memory data storage. FEATURES ï'· Organization Memory cell array Register Page size Block size , Control circuit to Column decoder I/O8 Command register Data register Row address buffer , '¾ ns tDS Data Setup Time 12 ï'¾ ns tDH Data Hold Time 5 ï'¾ ns tWC , Array to Starting Address ï'¾ 25 s tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) ï'¾ 25 s tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah) ï Toshiba
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TH58NVG3S0HBAI4 2013-09-20C
Abstract: memory data storage. FEATURES ï'· Organization Memory cell array Register Page size Block size , Control circuit to Column decoder I/O8 Command register Data register Row address buffer , '¾ ns tDS Data Setup Time 12 ï'¾ ns tDH Data Hold Time 5 ï'¾ ns tWC , Array to Starting Address ï'¾ 25 s tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) ï'¾ 25 s tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah) ï Toshiba
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TH58NYG3S0HBAI4
Abstract: accessory board that allows up to 32 I/O pins to be controlled through a single Port connection on Elexol's I/O 24 Range. The Elexol I/O 24 Range consists of Ether I/O 24 R, Ether I/O 24 DIP R, USB I/O 24 R and the USB I/O 24 DIP R. The GPI/O 32 Board incorporates 2 x MCP23S17 GPIO expanders, which are split up into four 8 bit Ports (2 Ports per MCP23S17). This allows up to 32 I/O pins to be controlled via the Elexol I/O 24 SPI Protocol. BOARD FEATURES · · · · · 2 x MCP23S17 GPIO expander IC Elexol
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10 pin box header 10101010 elexol gpio 32
Abstract: timing. (1-3)Sh i ft-Reg i ster When the CE terminal is "H" (Enable mode), the display data is , display data writing. Example KMode 1): Write to Shift-register 1(1 to 50-bit) CE i lj i_ scL_i:;:;:;:;:;:]_ DATA_I Mode 1 Data I_I Data Block 1 I_ MODE I I_ Example 2(Mode 2): Write to Shift-register 2(51 to 100-bit) CE i lj scl_iiiiiiiiiiziiiiiiiiih_ DATA_I Mode 2 Data I_I Data Block~2 MODE I I , to 150-bit) CE_I u scL_tiizizizziiizzi DATA_I Mode 3 Data I_I Data Block 3 MODE I _ Example 4 -
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D1561 D1451 DSI DBI lcd dsi PLD-5 SEG49
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