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TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK pdf Buy

"cyclic redundancy check" data transmission "para

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Abstract: connection designed for high-speed data transmission at field level. PROFIBUS-DP has widespread usage for , protocol for data transmission. It is designed to support intrinsically safe applications and can be used , high-speed, time-critical data transmission at field level using low-cost connections. PROFIBUS-DP is a , buffer T3: transmission time between CME-PD01 CME-PD01 and VFD-E T1 Master CME-PD01 CME-PD01 Timer Data Buffer , Parameters 5.3 Cyclical Data of ... Delta Electronics
Original
datasheet

35 pages,
431.58 Kb

delta vfd control Delta VFD-E User manual CME-PD01 0x7501 profibus connector vfd M DELTA COMMUNICATION INSTRUCTION CMEPD01 delta ac drive delta PLC communication manual SPC3 profibus profibus 0x2101 vfd B DELTA manual DB9 RJ45 RS485 SG RS-485/rj45 delta vfd delta vfd RJ45 wiring profibus dp rs485 wiring delta vfd-e with modbus communication TEXT
datasheet frame
Abstract: connection designed for high-speed data transmission at field level. PROFIBUS-DP has widespread usage for , protocol for data transmission. It is designed to support intrinsically safe applications and can be used , PROFIBUS-DP is a PROFIBUS communication profile optimized for high-speed, time-critical data transmission at , . 11 Cyclical data of PD-01 PD-01 via PROFIBUS-DP . 12 Useful data structure as defined in PROFIDrive Profile 2.0. 12 Extended configuration ... Delta Electronics
Original
datasheet

36 pages,
719.36 Kb

vfd motor control deltronic modbus VFD-L delta vfd b profibus dp rs485 db9 rs 485 modbus delta vfd-l with modbus communication delta electronics VFD vfd B DELTA manual rs485 connection vfd-l to plc vfd M DELTA COMMUNICATION INSTRUCTION delta vfd-m with modbus communication PD-01 rs485 delta PD-01 profibus rs485 9 pin RJ11 PD-01 SPC3 profibus PD-01 profibus dp rs485 wiring PD-01 delta vfd-L PD-01 vfd B DELTA PD-01 delta vfd PD-01 PD-01 PD-01 TEXT
datasheet frame
Abstract: RF channel. See Figure 1. The IS-54 IS-54 standard separates the data bits into class 1 bits and class 2 , addition, a cyclic redundancy check (CRC) is calculated on the 12 class 1 bits designated as most , . The speech data is read into the simulation from an input speech file. This file is binary pulse-code-modulated 16-bit data. The VSELP encoder is the Motorola standard, which is available from the TIA. The , speech data. From the output of the VSELP encoder, the most perceptually significant bits of the encoded ... Texas Instruments
Original
datasheet

10 pages,
58.75 Kb

Viterbi Trellis Decoder texas Convolutional interleaver IS-54 IS54B rAised cosine SPRA135 TMS320 Viterbi Decoder 486DX TEXT
datasheet frame
Abstract: RF channel. See Figure 1. The IS-54 IS-54 standard separates the data bits into class 1 bits and class 2 , addition, a cyclic redundancy check (CRC) is calculated on the 12 class 1 bits designated as most , . The speech data is read into the simulation from an input speech file. This file is binary pulse-code-modulated 16-bit data. The VSELP encoder is the Motorola standard, which is available from the TIA. The , speech data. From the output of the VSELP encoder, the most perceptually significant bits of the encoded ... Texas Instruments
Original
datasheet

11 pages,
66.05 Kb

VSELP motorola 486DX Convolutional Convolutional decoder convolutional encoder interleaving convolutional interleave IS-54 Pi filter array design SPRA135 TMS320 viterbi algorithm IS54B IS-54B TEXT
datasheet frame
Abstract: RF channel. See Figure 1. The IS-54 IS-54 standard separates the data bits into class 1 bits and class 2 , addition, a cyclic redundancy check (CRC) is calculated on the 12 class 1 bits designated as most , . The speech data is read into the simulation from an input speech file. This file is binary pulse-code-modulated 16-bit data. The VSELP encoder is the Motorola standard, which is available from the TIA. The , speech data. From the output of the VSELP encoder, the most perceptually significant bits of the encoded ... Texas Instruments
Original
datasheet

11 pages,
61.86 Kb

TMS320 SPRA135 convolutional 486DX IS-54 IS-54-B TEXT
datasheet frame
Abstract: , data, and powerto a single data pin • Directly connects to a single port pin of a microproces , requirements to reader • 8-bit cyclic redundancy check ensures error-free selection • Zero standby power , BOTTOM VIEW PIN DESCRIPTION Pin 1 Pin 2 Pin 3 Pin 4 - Ground Data PIO Ground C-LEAD Pin 1 Pin 2 Pin 3 Pin 4-6 Ground Data PIO No Connect • 1-Wire communication operates , patents and other intellectual property rights, please refer to Dallas Semiconductor data books ... OCR Scan
datasheet

12 pages,
269.57 Kb

DS2405 TEXT
datasheet frame
Abstract: ensures compatibility with other MicroLAN™ products • Reduces control, address, data, and power to a single data pin • Directly connects to a single port pin of a microproces­ sor and communicates at , DS2405 DS2405 communications requirements to reader PIN DESCRIPTION • 8-bit cyclic redundancy check , cost TO-92, SOT-223, or 6-pin C-Lead surface mount package - Ground Data PIO Ground TO P V IE W See Mech. Drawing Pg. 344 C-LEAD Pin 1 Pin 2 Pin 3 Pin 4-6 Ground Data PIO No ... OCR Scan
datasheet

12 pages,
257.7 Kb

DS2405 TEXT
datasheet frame
Abstract: , destination address, length/type, data, and pad fields using a 32-bit Cyclic Redundancy Check (CRC) defined , data. Clears the status bit at the completion of the transmission. MAC Address The 48-bit MAC , Normal data transmission 1 0000 through 1111 Transmit error propagation RX_DV The PHY drives , ). The 4-bit transmit and receive data interface to the external PHY is little endian (bit 3 is the , the Ethernet unit of transmission; this specification does likewise © 2002 Xilinx, Inc. All rights ... Xilinx
Original
datasheet

20 pages,
320.83 Kb

vhdl ethernet xilinx vhdl code CRC 32 sfd 349 emac implementation DS441 00-00-5E-00-FA-CE vhdl code for ethernet csma cd TEXT
datasheet frame
Abstract: data transmission over a single dif­ ferential pair. The Serializer/Deserializer pair is targeted for , -bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor , 16±bit data payload with CRC (Cyclic Redundancy Check) for checking data integrity with programmable data transmission error detection and interrupt control B Up to 6 Programmable GPIO© B AT-SPEED , is always LOW. This data payload is optimized for signal transmission over an AC cou­ pled link ... OCR Scan
datasheet

45 pages,
902.24 Kb

DS92LX1621/DS92LX1622 TEXT
datasheet frame
Abstract: During Call Waiting Calling Line Identification Cyclic Redundancy Check Clear to Send Data Carrier , mechanism is protocol dependent). (ii) Several buffers of data are held waiting transmission across ISDN , CMX218 CMX218 ISDN Data/Telephony Protocol Engine D/218/1 D/218/1 October 1999 Advance Information Features Applications · Supports Incoming and Outgoing Calls · Feature Phones with Data , .120 / PPP Operation · PABX Telephones and Data · Supports CTR3 Approval · EPOS Terminals ... CML Microcircuits
Original
datasheet

34 pages,
347.86 Kb

CMX218 AM79C30 79C30 PSB21525 cmx605 Auto-bauding RJ45 pinout for siemens pabx D/218/1 TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
C161JC/Data/C161JC.REGS CSP.7-0 SEGNR,r 1 0 SFR 0xFE00 DPP0,0x0000 undef "CPU Data Page Pointer 0 Register (10 bits)" BFLD DPP0.9-0 DPP0PN,rw 0 0 SFR 0xFE02 DPP1,0x0001 undef "CPU Data DPP2,0x0002 undef "CPU Data Page Pointer 2 Register (10 bits)" BFLD DPP2.9-0 DPP2PN,rw 0 0 SFR 0xFE06 DPP3,0x0003 undef "CPU Data Page Pointer 3 Register (10 bits)"
/datasheets/files/infineon/mc_data/dave/products/c161jc.dip
Infineon 23/08/2002 7347.98 Kb DIP c161jc.dip
C161CS/Data/C161CS.REGS CSP.7-0 SEGNR,r 1 0 SFR 0xFE00 DPP0,0x0000 undef "CPU Data Page Pointer 0 Register (10 bits)" BFLD DPP0.9-0 DPP0PN,rw 0 0 SFR 0xFE02 DPP1,0x0001 undef "CPU Data DPP2,0x0002 undef "CPU Data Page Pointer 2 Register (10 bits)" BFLD DPP2.9-0 DPP2PN,rw 0 0 SFR 0xFE06 DPP3,0x0003 undef "CPU Data Page Pointer 3 Register (10 bits)"
/datasheets/files/infineon/mc_data/dave/products/c161cs.dip
Infineon 23/08/2002 7211.48 Kb DIP c161cs.dip
C161JI/Data/C161JI.REGS CSP.7-0 SEGNR,r 1 0 SFR 0xFE00 DPP0,0x0000 undef "CPU Data Page Pointer 0 Register (10 bits)" BFLD DPP0.9-0 DPP0PN,rw 0 0 SFR 0xFE02 DPP1,0x0001 undef "CPU Data DPP2,0x0002 undef "CPU Data Page Pointer 2 Register (10 bits)" BFLD DPP2.9-0 DPP2PN,rw 0 0 SFR 0xFE06 DPP3,0x0003 undef "CPU Data Page Pointer 3 Register (10 bits)"
/datasheets/files/infineon/mc_data/dave/products/c161ji.dip
Infineon 23/08/2002 7192.68 Kb DIP c161ji.dip
C161CS/Data/C161CS.REGS CSP.7-0 SEGNR,r 1 0 SFR 0xFE00 DPP0,0x0000 undef "CPU Data Page Pointer 0 Register (10 bits)" BFLD DPP0.9-0 DPP0PN,rw 0 0 SFR 0xFE02 DPP1,0x0001 undef "CPU Data DPP2,0x0002 undef "CPU Data Page Pointer 2 Register (10 bits)" BFLD DPP2.9-0 DPP2PN,rw 0 0 SFR 0xFE06 DPP3,0x0003 undef "CPU Data Page Pointer 3 Register (10 bits)"
/datasheets/files/infineon/mc_data/dave/products/c161cs2r.dip
Infineon 14/01/2005 7210.41 Kb DIP c161cs2r.dip
C164CM/Data/C164CM.REGS CSP.7-0 SEGNR,r 1 0 SFR 0xFE00 DPP0,0x0000 undef "CPU Data Page Pointer 0 Register (10 bits)" BFLD DPP0.9-0 DPP0PN,rw 0 0 SFR 0xFE02 DPP1,0x0001 undef "CPU Data DPP2,0x0002 undef "CPU Data Page Pointer 2 Register (10 bits)" BFLD DPP2.9-0 DPP2PN,rw 0 0 SFR 0xFE06 DPP3,0x0003 undef "CPU Data Page Pointer 3 Register (10 bits)"
/datasheets/files/infineon/mc_data/dave/products/c164cm.dip
Infineon 12/08/2002 6013.15 Kb DIP c164cm.dip
C164SM/Data/C164SM.REGS CSP.7-0 SEGNR,r 1 0 SFR 0xFE00 DPP0,0x0000 undef "CPU Data Page Pointer 0 Register (10 bits)" BFLD DPP0.9-0 DPP0PN,rw 0 0 SFR 0xFE02 DPP1,0x0001 undef "CPU Data DPP2,0x0002 undef "CPU Data Page Pointer 2 Register (10 bits)" BFLD DPP2.9-0 DPP2PN,rw 0 0 SFR 0xFE06 DPP3,0x0003 undef "CPU Data Page Pointer 3 Register (10 bits)"
/datasheets/files/infineon/mc_data/dave/products/c164sm.dip
Infineon 12/08/2002 5856.68 Kb DIP c164sm.dip
C164SL/Data/C164SL.REGS CSP.7-0 SEGNR,r 1 0 SFR 0xFE00 DPP0,0x0000 undef "CPU Data Page Pointer 0 Register (10 bits)" BFLD DPP0.9-0 DPP0PN,rw 0 0 SFR 0xFE02 DPP1,0x0001 undef "CPU Data DPP2,0x0002 undef "CPU Data Page Pointer 2 Register (10 bits)" BFLD DPP2.9-0 DPP2PN,rw 0 0 SFR 0xFE06 DPP3,0x0003 undef "CPU Data Page Pointer 3 Register (10 bits)"
/datasheets/files/infineon/mc_data/dave/products/c164sl.dip
Infineon 29/01/2002 5994.14 Kb DIP c164sl.dip
XC161CJ/Data/Xc161cj.REGS ;= REV 2002-05-23 DEV,C166,XC161CJ XC161CJ ;= ;* ; Module: ; XC161CJ XC161CJ.REGS ;- ; Description: ; This is the register definition file for the XC161CJ XC161CJ.
/datasheets/files/infineon/mc_data/dave/products/xc161cj_v24.dip
Infineon 09/02/2004 9113.92 Kb DIP xc161cj_v24.dip
C164SI/Data/C164SI.REGS CSP.7-0 SEGNR,r 1 0 SFR 0xFE00 DPP0,0x0000 undef "CPU Data Page Pointer 0 Register (10 bits)" BFLD DPP0.9-0 DPP0PN,rw 0 0 SFR 0xFE02 DPP1,0x0001 undef "CPU Data DPP2,0x0002 undef "CPU Data Page Pointer 2 Register (10 bits)" BFLD DPP2.9-0 DPP2PN,rw 0 0 SFR 0xFE06 DPP3,0x0003 undef "CPU Data Page Pointer 3 Register (10 bits)"
/datasheets/files/infineon/mc_data/dave/products/c164si.dip
Infineon 29/01/2002 5994.29 Kb DIP c164si.dip
XC161CJ/Data/Xc161cj.REGS ;= REV 2002-05-23 DEV,C166,XC161CJ XC161CJ ;= ;* ; Module: ; XC161CJ XC161CJ.REGS ;- ; Description: ; This is the register definition file for the XC161CJ XC161CJ.
/datasheets/files/infineon/mc_data/dave/products/xc161cj.dip
Infineon 09/02/2004 9113.92 Kb DIP xc161cj.dip