500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Direct from the Manufacturer

Part Manufacturer Description PDF & SAMPLES
DATALOG-M24LR-A STMicroelectronics Datalogger Reference Board For The M24LR64-R Dual Interface EEPROM
TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK
SWR-QII-SEPARATION Altera Corporation DEV SOFTWARE W/QUARTUS II RENEW
SW-QII-SEPARATION Altera Corporation DEV SOFTWARE W/QUARTUS II
UPA1A472MHD6TN Nichicon Corporation CAP,AL2O3,4.7MF,10VDC,20% -TOL,20% +TOL
UPA0J681MPD1TA Nichicon Corporation CAP,AL2O3,680UF,6.3VDC,20% -TOL,20% +TOL

"cyclic redundancy check" data transmission "para

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: connection designed for high-speed data transmission at field level. PROFIBUS-DP has widespread usage for , protocol for data transmission. It is designed to support intrinsically safe applications and can be used , high-speed, time-critical data transmission at field level using low-cost connections. PROFIBUS-DP is a , buffer T3: transmission time between CME-PD01 and VFD-E T1 Master CME-PD01 Timer Data Buffer , Parameters 5.3 Cyclical Data of Delta Electronics
Original
delta vfd-e with modbus communication profibus dp rs485 wiring delta vfd RJ45 wiring delta vfd RS-485/rj45 DB9 RJ45 RS485 SG 2006PDD23000013
Abstract: connection designed for high-speed data transmission at field level. PROFIBUS-DP has widespread usage for , protocol for data transmission. It is designed to support intrinsically safe applications and can be used , PROFIBUS-DP is a PROFIBUS communication profile optimized for high-speed, time-critical data transmission at , . 11 Cyclical data of PD-01 via PROFIBUS-DP . 12 Useful data structure as defined in PROFIDrive Profile 2.0. 12 Extended configuration Delta Electronics
Original
vfd B DELTA delta vfd-L delta vfd-m with modbus communication SPC3 profibus profibus rs485 9 pin RJ11 rs485 delta NL-5928 RS-485
Abstract: RF channel. See Figure 1. The IS-54 standard separates the data bits into class 1 bits and class 2 , addition, a cyclic redundancy check (CRC) is calculated on the 12 class 1 bits designated as most , . The speech data is read into the simulation from an input speech file. This file is binary pulse-code-modulated 16-bit data. The VSELP encoder is the Motorola standard, which is available from the TIA. The , speech data. From the output of the VSELP encoder, the most perceptually significant bits of the encoded Texas Instruments
Original
SPRA135 486DX Viterbi Decoder TMS320 rAised cosine IS54B TMS320C5 IS-54B
Abstract: RF channel. See Figure 1. The IS-54 standard separates the data bits into class 1 bits and class 2 , addition, a cyclic redundancy check (CRC) is calculated on the 12 class 1 bits designated as most , . The speech data is read into the simulation from an input speech file. This file is binary pulse-code-modulated 16-bit data. The VSELP encoder is the Motorola standard, which is available from the TIA. The , speech data. From the output of the VSELP encoder, the most perceptually significant bits of the encoded Texas Instruments
Original
viterbi algorithm Pi filter array design convolutional interleave convolutional encoder interleaving Convolutional decoder Convolutional
Abstract: RF channel. See Figure 1. The IS-54 standard separates the data bits into class 1 bits and class 2 , addition, a cyclic redundancy check (CRC) is calculated on the 12 class 1 bits designated as most , . The speech data is read into the simulation from an input speech file. This file is binary pulse-code-modulated 16-bit data. The VSELP encoder is the Motorola standard, which is available from the TIA. The , speech data. From the output of the VSELP encoder, the most perceptually significant bits of the encoded Texas Instruments
Original
IS-54-B
Abstract: , data, and powerto a single data pin â'¢ Directly connects to a single port pin of a microproces , requirements to reader â'¢ 8-bit cyclic redundancy check ensures error-free selection â'¢ Zero standby power , BOTTOM VIEW PIN DESCRIPTION Pin 1 Pin 2 Pin 3 Pin 4 - Ground Data PIO Ground C-LEAD Pin 1 Pin 2 Pin 3 Pin 4-6 Ground Data PIO No Connect â'¢ 1-Wire communication operates , patents and other intellectual property rights, please refer to Dallas Semiconductor data books -
OCR Scan
DS2405 2L1413Q
Abstract: ensures compatibility with other MicroLANâ"¢ products â'¢ Reduces control, address, data, and power to a single data pin â'¢ Directly connects to a single port pin of a microproces­ sor and communicates at , DS2405 communications requirements to reader PIN DESCRIPTION â'¢ 8-bit cyclic redundancy check , cost TO-92, SOT-223, or 6-pin C-Lead surface mount package - Ground Data PIO Ground TO P V IE W See Mech. Drawing Pg. 344 C-LEAD Pin 1 Pin 2 Pin 3 Pin 4-6 Ground Data PIO No -
OCR Scan
Abstract: , destination address, length/type, data, and pad fields using a 32-bit Cyclic Redundancy Check (CRC) defined , data. Clears the status bit at the completion of the transmission. MAC Address The 48-bit MAC , Normal data transmission 1 0000 through 1111 Transmit error propagation RX_DV The PHY drives , ). The 4-bit transmit and receive data interface to the external PHY is little endian (bit 3 is the , the Ethernet unit of transmission; this specification does likewise © 2002 Xilinx, Inc. All rights Xilinx
Original
DS441 vhdl code for ethernet csma cd 00-00-5E-00-FA-CE emac implementation sfd 349 vhdl code CRC 32
Abstract: data transmission over a single dif­ ferential pair. The Serializer/Deserializer pair is targeted for , -bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor , 16±bit data payload with CRC (Cyclic Redundancy Check) for checking data integrity with programmable data transmission error detection and interrupt control B Up to 6 Programmable GPIO© B AT-SPEED , is always LOW. This data payload is optimized for signal transmission over an AC cou­ pled link -
OCR Scan
DS92LX1621/DS92LX1622 SNLS327G DS92LX1621 DS92LX1622
Abstract: During Call Waiting Calling Line Identification Cyclic Redundancy Check Clear to Send Data Carrier , mechanism is protocol dependent). (ii) Several buffers of data are held waiting transmission across ISDN , CMX218 ISDN Data/Telephony Protocol Engine D/218/1 October 1999 Advance Information Features Applications · Supports Incoming and Outgoing Calls · Feature Phones with Data , .120 / PPP Operation · PABX Telephones and Data · Supports CTR3 Approval · EPOS Terminals CML Microcircuits
Original
79C30 RJ45 pinout for siemens pabx Auto-bauding cmx605 PSB21525 AM79C30 CMX605 PSB-21525 CMX218S1
Abstract: -bit cyclic redundancy check (CRC). - Flow control to prevent data from accumulating at the receiving end , for transmission, and the data is ignored. Otherwise, the MLAPD continues to process the l-frame by , -Frame Transmission Queueing When the host has data ready for transmission on a logical link, the host prepares one , MOTOROLA i SEMICONDUCTOR TECHNICAL DATA MC68606 Technical Sum m ary Multi-Link Access , data transfer appli cations in Integrated Services Digital Network (ISDN) configurations. The LAPD -
OCR Scan
920/Q M68000 84-LEAD
Abstract: data field is 46 bytes or more, the pad field will have 0 bytes. For transmission, this field will be , , destination address, length/type, data, and pad fields using a 32-bit Cyclic Redundancy Check (CRC) defined , and appends it to the end of the data. · Clears the status bit at the completion of the transmission , the data. · Clears the status bit at the completion of the transmission. · Clearing the status bit , 6.2i or later · Memory mapped direct I/O interface to the transmit and receive data dual port Xilinx
Original
fpga frame buffer vhdl examples vhdl code for ethernet mac spartan 3 FF896 Net Send Lite CR203990 CR209050 CR209051
Abstract: 51.84 Mbit/s (STS-1) data rates · Bit serial, nibble, or byte-parallel line interface · Compatible with , packet termination operation · Works with commercially available external FIFOs · Terminal data loopback , TXC-05101C is a high speed, High Level Data Link Controller (HDLC) designed to send and receive , connects with other TranSwitch devices to allow for the rapid design of reliable packet transmission , product life data and on this p ro d u c t. subject to cha n g e . C ontact TranS w itch A p plications -
OCR Scan
CRC-16 CRC-32
Abstract: zt7102 IOP310 cmm220 re-enumeration ZT5089 MPCHC5091 . 21 Redundancy, Synchronization, and Failover , Requirements . 24 3.4 Initial Data , Data Sync Failure . 25 3.5 , 5.10.1 Global Data , Excessive Reboot/Failover 5.10.2 Process-Specific Data Intel
Original
ZT 7102 IPMI command format introduction intel 5400 cmmg IOP310
Abstract: Configuration method 8-2 8.1.3 Frame Structure 8-5 8.1.4 List of Commands 8-8 8.1.5 Data Type , program storage / memory function ・ Data storage / memory function ・ Application program execution , data exchange with other systems, such as KGLWIN, computers Interface 2-4 Chapter 2 System , ) Data register Operation modes RUN, STOP, PAUSE, DEBUG Self-diagnosis functions Detect errors of scan time, memory, I/O, battery, and power supply Data back-up method Battery-back-up IMO
Original
f0035 PLC K7M-DR40S F0150 F015F F0160 F017F F0500 F050F
Abstract: (quaternary) pulse amplitude modulation code with no redundancy. Data is grouped into pairs of bits for , . Transmission from the T7237 to the microprocessor carries register data only. The interrupt line to the , m i c ro e I e c t ro n i c s g r o u p Data Sheet February 1998 Lucent Technologies Bell , adapter (TA) equip­ ment providing 2-wire termination of the network with B- and D-channel data , and voice/ data ports â'" Allows access to 2B+D data on TDM bus â  Other â'" Single +5 V ( -
OCR Scan
T7256 F-06561 800-521-CORE
Abstract: transmission without the need to re-acquire the packet data over the processor bus. This is accomplished by , Transmit status FIFO became full following the transmission of a packet and data was lost. Care must be , Ethernet unit of transmission; this specification does likewise © 2004 Xilinx, Inc. All rights reserved , bits).The 4-bit transmit and receive data interface to the external PHY is little endian (bit 3 is the , and RX FIFOs for holding data for more than one packet. 2K byte depth is sufficient for normal 1518 Xilinx
Original
0x235c ds435 DS435
Abstract: SLVS physical layer is purpose-built for an extremely low power and low EMI data transmission while , once power is stable and within specification and link transmission is desired. Before data can be , Interface Data integrity is insured with a 5-bit CRC field. CRC checking is done for both WRITE and READ , Power Consumption S 5-bit CRC for data integrity S Low Power sleep state S 3.3V Tolerant Master Clock , SERIAL BUS PINS DDP 1 1 IO, si vs Differential Data - Positive, Transceiver DDN 1 1 -
OCR Scan
LM4308 LS225B
Abstract: Cyclic Redundancy Check Clear to Send Data Carrier Detect Direct Dialling Inwards Data Terminal , ) Several buffers of data are held waiting transmission across ISDN. Flow control is applied to the remote end (the mechanism is protocol dependent) if excessive data is held pending transmission to the DTE , CMX228 ISDN Protocol Engine with D - channel Data D/228/1 October 1999 Advance Information Features Applications · Full ISDN Voice and Data Services · Feature Phones with Data CML Microcircuits
Original
CMX228S1
Abstract: Preliminary Data Sheet May 1997 microelectronics group Lucent Technologies Bell Labs , , and data recovery (immune to false lock), and receive decoder â  CEPT/E1 interference immunity as , attenuator selectable for use in transmit or receive path. Jitter attenuation characteristics are data , Quad T1/E1 Line Interface and Octal T1/E1 Monitor Preliminary Data Sheet May 1997 Table of , .1 Facility Data Link Features -
OCR Scan
T7698 CB119 TR54016 TR-TSY-000170 TR-TSY000009 TR-TSY-000499
Showing first 20 results.