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"content addressable memory" search compare match current voltage

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Abstract: Addressable Memory ( NCAM ) match is detected the device will then output a Match Flag and the Address of , participate in a search. Upon detection of a match, the device will output the match flag, the address of , . The current active Configuration Register set controls, Writes, Reads, Moves and Compare operations , NL81480A NL81480A NL82480A NL82480A 1K X 64 2K X 64 Content Addressable Memory ( NCAM ) Features · · · , Priority Encoder / RESET DEMUX Validity Bits / EC Memory Control, Match & Flag Logic ... Netlogic Microsystems
Original
datasheet

18 pages,
173.86 Kb

"Content Addressable Memory" netlogic 016Fh 0230H 0309H 0324H 0427H 0507H 0804H 0B22H 0927H NetLogic Microsystems 0127H Priority Encoder CAM 01AEH NL81480A NL82480A Content Addressable Memory NL81480A NL82480A Netlogic NL81480A NL82480A "Content Addressable Memory" NL81480A NL82480A netlogic CAM NL81480A NL82480A NL81480A NL81480A NL82480A NL82480A TEXT
datasheet frame
Abstract: OUT BIT COMPARE FOR ONE OR MORE BITS 50% tDM- MATCH OUTPUT tl/f/9857-10 FIGURE 5. Search Mode , words. A search/compare is performed by placing a LOW on the bit mask inputs and presenting a data pattern to the data inputs. Corresponding to the bit mask inputs, the match outputs (m0-m3) go LOW if a , CM ffWk National MjA Semiconductor F100142 F100142 4 x 4-Bit Content Addressable Memory General Description The F100142 F100142 is a 4 word by 4-bit Content Addressable Memory (CAM). Reading is accomplished when ... OCR Scan
datasheet

7 pages,
199.74 Kb

F100142 content addressable memory resistor Mk2 f100145 TDD 1605 tms 1035 TEXT
datasheet frame
Abstract: , the data input word is simultaneously compared to each of the stored memory words. A search/compare fs , Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) Operating Range (Note 2) 0°C to , input LOW Voltage Input LOW Current Min -1035 -1830 -1045 -1165 -1830 0.50 Typ Max -880 -1620 -1610 -880 , an output enable. MATCH OUTPUT \ (-.DM- 50% 1 • * \ ~látjjj—¡fS" 7 ' 50% FIGURE 5. Search , New Designs r-HC-23-3/ 100142 4 x 4-Bit Content Addressable Memory General Description The 100142 is a ... OCR Scan
datasheet

7 pages,
278.63 Kb

F100145 TEXT
datasheet frame
Abstract: DS28E04-100 DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO ABSOLUTE MAXIMUM RATINGS All Pins: Voltage to , Standby Supply Current PINS A0 TO A6 Input Low Voltage SYMBOL IGND ICC ICCS CONDITIONS , High Voltage VIHA Input Load Current POL PIN Input Low Voltage ILA VILPOL Pin at GND , , VCC) (Note 1) Leakage Current PIO PINS Input Low Voltage ILKPOL VX 0.3V Pin at 5.25V Input High Voltage Output Low Voltage at 4mA Leakage Current Minimum Sensed PIO Pulse Output Pulse ... Maxim Integrated Products
Original
datasheet

37 pages,
761.13 Kb

DS28E04-100 TEXT
datasheet frame
Abstract: -100: 4096-Bit 1-Wire Addressable EEPROM with PIO ABSOLUTE MAXIMUM RATINGS All Pins: Voltage to GND All , Current Supply Current Standby Supply Current PINS A0 TO A6 Input Low Voltage SYMBOL IGND ICC , (Note 1) Input High Voltage VIHA Input Load Current POL PIN Input Low Voltage ILA VILPOL , max(VPUP, VCC) (Note 1) Leakage Current PIO PINS Input Low Voltage ILKPOL VX 0.3V Pin at 5.25V Input High Voltage Output Low Voltage at 4mA Leakage Current Minimum Sensed PIO Pulse ... Maxim Integrated Products
Original
datasheet

36 pages,
341.59 Kb

J-STD-020A DS28E04S-100 DS2490 DS2480B CRC16 111kbps DS28E04-100 TEXT
datasheet frame
Abstract: -Wire Addressable EEPROM with PIO ABSOLUTE MAXIMUM RATINGS All Pins: Voltage to GND All Pins: Sink Current , ) Input Load Current POL PIN Input Low Voltage ILA VILPOL (Note 1) Input High Voltage VIHPOL VX = max(VPUP, VCC) (Note 1) Leakage Current PIO PINS Input Low Voltage ILKPOL Pin , (Note 5) ILKP Pin at 5.25V Output Low Voltage at 4mA Leakage Current Minimum Sensed PIO , Load Current High-to-Low Switching Threshold Input Low Voltage Input High Voltage Low-to-High ... Maxim Integrated Products
Original
datasheet

37 pages,
724.23 Kb

DS28E04-100 TEXT
datasheet frame
Abstract: results of a Compare operation. During a compare operation, when there is no match, RBUS is High-Z. For a compare operation, when there is a match, this bus outputs the CAM index of the Highest Priority Match , in the following cycle. The Match Flag is available in the current clock cycle. The user must set , in the memory will not enter the compare operation and behave as if a match occurred for that , register holds the address of the highest priority match. This register is updated after all compare ... Netlogic Microsystems
Original
datasheet

28 pages,
882.14 Kb

"routing tables" 292-P ipCAM NetLogic Ternary Content Addressable NL82721 NL82721R Priority Encoder CAM RBUS12 Ternary CAM ternary netlogic NetLogic netlogic CAM TEXT
datasheet frame
Abstract: Supply Voltage (V) Normalized Dynamic Supply Current vs. Ambient Temp. Vdd=3.3V, 100% Compare , operation. During a compare operation, when there is no match, RBUS is High-Z. For a compare operation , not enter the compare operation and behave as if a match occurred for that particular bit. If a mask , register holds the address of the highest priority match. This register is updated after all compare , is written. Reserved; will read `000'. Match flag. Updated after all compare operations; reflects ... Netlogic Microsystems
Original
datasheet

28 pages,
851.24 Kb

NL84620R NL84620 ipCAM ethernet module ipCAM "routing tables" TEXT
datasheet frame
Abstract: ) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the , PCA counter and the module's capture/compare register. • The match bit MAT (CCAPMn.3) when set will , = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in , an unwanted match doesn't occur while modifying the compare value. Writing to CCAPnH will set ECOM , options: • 1. periodically change the compare value so it will never match the PCA timer, • 2 ... OCR Scan
datasheet

72 pages,
3949.63 Kb

VQFP44 80C51 80C52 05A2 JLCC-68 PDIL40 PLCC44 TS87C51RB2 ic 80c51rd2 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 C51RB2/RC2/RD2 TEXT
datasheet frame
Abstract: results of a Compare operation. During a compare operation, when there is no match, RBUS is High-Z. For a compare operation, when there is a match, this bus outputs the CAM index of the Highest Priority Match , compare instruction are output on RBUS in the following cycle. The Match Flag is available in the , compare operation and behave as if a match occurred for that particular bit. If a mask bit is `0', the , match. This register is updated after all compare operations. This register is read only and is updated ... Netlogic Microsystems
Original
datasheet

27 pages,
520 Kb

netlogic cam memory "routing tables" Ternary CAM NL82721R NetLogic Ternary Content Addressable counter up/down ipcam Content Addressable Memory ternary netlogic NL82721 "Content Addressable Memory" NetLogic ternary content addressable memory netlogic CAM TEXT
datasheet frame

Archived Files

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addressable bits is located at byte addresses 20H - 2FH of the lower data RAM. Bit 0 of the internal data byte area typically provides 128 bytes of direct addressable SFRs. The SFRs which are located at addresses , timers, capture/compare units, A/D converters, watchdog units, or a multiply/divide unit are typical compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble , complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or
/datasheets/files/infineon/mc_data/dave/products/c508.dip
Infineon 01/02/2000 5502.86 Kb DIP c508.dip
addressable bits is located at byte addresses 20H - 2FH of the lower data RAM. Bit 0 of the internal data byte area typically provides 128 bytes of direct addressable SFRs. The SFRs which are located at addresses , timers, capture/compare units, A/D converters, watchdog units, or a multiply/divide unit are typical compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble , complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or
/datasheets/files/infineon/mc_data/dave/products/c505l.dip
Infineon 06/06/2000 3932.36 Kb DIP c505l.dip
. 21 2.5.9 Capture / Compare (CAPCOM) Units . 177 14 THE CAPTURE / COMPARE . 186 14.3 CAPTURE / COMPARE REGISTERS . 187 14.3.1 Selection of Capture Modes and Compare Modes . 189 14.5 COMPARE MODES
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/7317.htm
STMicroelectronics 20/10/2000 740.4 Kb HTM 7317.htm
Mode 0 = 83 Mode 1 = 84 Mode 2 = 85 Mode 3 = 86 The Compare/Capture Unit (CCU) = 86 Timer 2 Operation = 91 Timer 2 Registers = 91 Timer 2 Operating Modes = 95 Operation of the Compare Timer = 98 Compare Timer Registers = 98 Operating Modes of the Compare Timers = 100 Compare Functions of the CCU = 101 Compare Mode 0 = 102 Compare Mode 1 = 104 Compare Mode 2 = 105 Timer- and Compare-Register Configurations of the CCU = 106 Timer 2 - Compare Function with Registers CRC, CC1 to CC4 = 107 Timer 2 -
/datasheets/files/infineon/mc_data/dave/products/c517a.dip
Infineon 21/09/2004 3216.42 Kb DIP c517a.dip
addressable bits is located at byte addresses 20H - 2FH of the lower data RAM. Bit 0 of the internal data byte area typically provides 128 bytes of direct addressable SFRs. The SFRs which are located at addresses , timers, capture/compare units, A/D converters, watchdog units, or a multiply/divide unit are typical compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble , complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or
/datasheets/files/infineon/mc_data/dave/products/c505a.dip
Infineon 01/02/2000 4539.55 Kb DIP c505a.dip
addressable bits is located at byte addresses 20H - 2FH of the lower data RAM. Bit 0 of the internal data byte area typically provides 128 bytes of direct addressable SFRs. The SFRs which are located at addresses , timers, capture/compare units, A/D converters, watchdog units, or a multiply/divide unit are typical compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble , complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or
/datasheets/files/infineon/mc_data/dave/products/c505ca.dip
Infineon 01/02/2000 4716.25 Kb DIP c505ca.dip
addressable bits is located at byte addresses 20H - 2FH of the lower data RAM. Bit 0 of the internal data byte area typically provides 128 bytes of direct addressable SFRs. The SFRs which are located at addresses , timers, capture/compare units, A/D converters, watchdog units, or a multiply/divide unit are typical compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble , complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or
/datasheets/files/infineon/mc_data/dave/products/c505c.dip
Infineon 01/02/2000 4108.68 Kb DIP c505c.dip
These instructions are useful to perform data search in Memory Source pointer ; incremented if compare : INNOVATIVE SOLUTIONS FOR EMBEDDED CONTROL. When you compare different microcontrollers, you can estimate the other groups of reg- isters. Since changing the current group involves only one instruction, the concept PAGE CORE PAGE 1 3 3 2 ; KEEP TRACK OF CURRENT GROUP PUSHW RPP ;SAVE REGISTER POINTER (1) PUSH PPR in the common address space which is the Memory Space. A total addressable memory space of 4 Mbytes
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6430.htm
STMicroelectronics 02/04/1999 77.26 Kb HTM 6430.htm
8-bit Analog to Digital Converter, with Automatic voltage monitoring capabilities and external low power consumption and low voltage operation for power-efficient and low-cost embedded systems. multifunction timer has a 16-bit Up/Down counter supported by two 16-bit Compare regis- ters and two watchdog gen- erates an interrupt when the input voltage moves out of a preset threshold. 9 8/199 option is selected. V PP : Programming voltage for EPROM/OTP de- vices. Must be connected to V
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5464-v4.htm
STMicroelectronics 26/01/2001 408.05 Kb HTM 5464-v4.htm
EMBEDDED CONTROL When you compare different microcontrollers, you can estimate the relative computing power groups of reg- isters. Since changing the current group involves only one instruction, the concept of in the common address space which is the Memory Space. A total addressable memory space of 4 Mbytes current program execution can be suspended to allow the ST9 to exe- cute a specific response routine. If the event generates an interrupt request, the current pro- gram status is saved after the current
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6430-v1.htm
STMicroelectronics 20/10/2000 79.6 Kb HTM 6430-v1.htm