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Part Manufacturer Description PDF & SAMPLES
5962-9681201QLA Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE 1149.1 24-CDIP -55 to 125
5962-9681201Q3A Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE 1149.1 28-LCCC -55 to 125
SNJ54ABT8996JT Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE 1149.1 24-CDIP -55 to 125
SN54ABT8996W Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE 1149.1 24-CFP
SNJ54ABT8996FK Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE 1149.1 28-LCCC -55 to 125
5962-9681201QKA Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE 1149.1 24-CFP -55 to 125

"content addressable memory" precharge

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 20Mbit QUAD-Search Content Addressable Memory Features & Benefits 20Mbit density Supports large routing tables and enables low-cost, low-power, more reliable system designs 360 Million , QUAD-Search TCAMs together using the cascade interface signals Sub-core pre-charge technology Uses , Content Addressable Memory (TCAM) devices for performing ultra-fast data packet searches. The new Renesas , Content Addressable Memory Typical application The 20Mbit, 360MHz device can make deterministic packet Renesas Electronics
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tcam R8A20410BG renesas tcam tcam renesas renesas CAM Xelerated tcam 360-MSPS R10PF0001EU0100
Abstract: Synchronous First-In First-Out Memory - up to 64Kbits - Synchronous Content Addressable Memory with Binary - up to 32Kbits - Synchronous Content Addressable Memory with Ternary - up to 32Kbits - , (differential) HSTL 1.5V, SRAM interface 300 Hot Swap PCI 1V pre-charge, VIO precharge 33 Samsung Electronics
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STD150 ternary content addressable memory VHDL SMART ASIC bga ARM1020E ARM dual port SRAM compiler 0.13um standard cell library Samsung ASIC STDL150 ARM920T/ARM940T
Abstract: Addressable Memory with Binary - up to 32Kbits - Single-Part Synchronous static SRAM with burst Read/Write , Hot Swap PCI 1V pre-charge, VIO precharge 1.0 compliant, 3.3V TIA/EIA-644 Design Kits Samsung Electronics
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samsung hdd Samsung Soc processor UART 16C450 ARM9TDMI ARM920t datasheet ARM SRAM compiler
Abstract: Addressable Memory with Binary - up to 32Kbits - Single-Part Synchronous static SRAM with burst Read/Write , Hot Swap PCI 1V pre-charge, VIO precharge 1.0 compliant, 3.3V TIA/EIA-644 Design Kits Samsung Electronics
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teaklite DSPG Samsung S ARM STD130 ARM940T ARM926EJ
Abstract: First-Out Memory - up to 64Kbits - Synchronous Content Addressable Memory with Binary - up to 32Kbits , ) 500(differential) HSTL 1.5V, SRAM interface 300 Hot Swap PCI 1V pre-charge, VIO precharge 1.0 compliant, 3.3V TIA/EIA-644 Design Kits Logic Synthesis Synopsys Design Compiler Samsung Electronics
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STDH150 usb dspg jtag 0.13Um ST jtag samsung s CA95134 Avant Electronics
Abstract: bits - synchronous Content Addressable Memory - up to 32K bits X : Not Support 2 Samsung , pre-charge, VIO precharge 1.0 compliant, 3.3V Design Flow Design Kits Logic Synthesis Synopsys Samsung Electronics
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synopsys dc ultra rm2510 STD110 IEEE1284 ARM920T 16C550
Abstract: bits - synchronous Content Addressable Memory - up to 32K bits X : Not Support 2 Samsung , pre-charge, VIO precharge 1.0 compliant, 3.3V Design Flow Design Kits Logic Synthesis Synopsys Samsung Electronics
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0.18-um STD110 ASIC piler jtag samsung 16C450 1.8V SRAM STD131
Abstract: 's location would be achieved by the Precharge, Active, Read/Write sequence. It is important that the memory , GPIO (GPIO_WKUP_6). The total addressable memory is split in equal parts on the 2 chip selects even , columns (A10 is used in connection with the precharge operation; therefore it is not really part of the , Active command to read / write delay is 2 XLB clocks · Precharge command to active command delay is , oris stw r5,r4 r5,r5,0x8000 r5,MEMCTL_CONTROL(r8) # write CONTROL # Step 6) issue precharge Motorola
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MGT5100 PPC823 PPC8260 MT4632M16 MT48LC16M16A2 Dynamic RAM controller AN2248/D
Abstract: number of addressable columns. · PRC TO RAS DELAY. This parameter determines the Precharge to RAS , number of addressable columns is 256 (A07). Thus, the page size should be configured to 256 , to Precharge delay, which is typically given in the datasheet as tRAS. PRE + 2×Autorefresh + MRS , at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be , . This parameter determines the RAS to Precharge delay, which is typically given in the datasheet as Analog Devices
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EE-210 ADSP-TS201S ADSP-BF533 ADSP-TS201 sdram controller ADSP-TS201 reference manual defbf533 MT48LC4M32B2 bf533 sdram full example c code ADSP-21065L ADSP-BF531/ADSP-BF532/ADSP-BF533
Abstract: . This number corresponds to the number of addressable columns. From the datasheet: Table 2 SDRAM , number of addressable columns is 256(A0-7). Thus, the page size should be configured to 256 , PRC TO RAS DELAY. This parameter determines the Precharge to RAS delay, which is typically given in , (SDRCON_RAS2PC5). · RAS TO PRC DELAY: This parameter determines the RAS to Precharge delay, which is , INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. [.] Once in the Analog Devices
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ADSP-21161N BF533 ADSP-TS203S ADSP-TS203 ADSP-TS202 ADSP-TS201 SDRAM MT48LC4M32B2 MT48LC16M16B2
Abstract: 's location would be achieved by the Precharge, Active, Read/Write sequence. It is important that the memory , addressable memory is split into equal parts on the 2 chip selects even when one is not used (by programming , rows and A0-A9 plus A11 for the columns. (A10 is used in connection with the precharge operation , Precharge command to active command delay is 2 XLB clocks · Refresh to active command delay is 6 XLB , write CONTROL # Step 6) issue precharge all mr ori stw r6,r5 r6,r5,0x0002 r6,MEMCTL_CONTROL Motorola
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AN2248 MT48LC32M16A2 0X0054 MT48LC8M8A2 MT48LC2M32B2 MT46V64M8 equivalent
Abstract: Preliminary version Added New Partnumber and User addressable density Changed Case dimension Changed SMART , Capacity Unformatted Capacity 32GB 25GB 64GB 50GB User Addressable Sectors 62,533,296 , ) P2 V33 3.3V power (Unused) P3 V33 3.3V power, pre-charge, 2nd mate (Unused) P4 GND 1st mate P5 GND 2nd mate P6 GND 2nd mate P7 V5 5V power, pre-charge , V12 12V power, pre-charge, 2nd mate (Unused) P14 V12 12V power (Unused) P15 V12 Samsung Electronics
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Samsung 64Gb Nand flash 01h-FDh SAT-PH22-S2A-FG S3C49 73212 50GB S3C49RBXZZ MCBQE32G5MPQ-0VA03 MCBQE25G5MPQ-0VA03 MCCOE64G5MPQ-0VA03 MCCOE50G5MPQ-0VA03
Abstract: subsystem in units of megabytes, megabits, and number of addressable words. It is useful to compare these , . Duration of precharge command (t_rp) - 20 ns Precharge command period. ACTIVE to READ or , (t_wr, No auto precharge) - 14 ns Write recovery if explicit precharge commands are issued. This SDRAM controller always issues explicit precharge commands. Settings CAS latency Altera
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NII51005-7 d4564163-a80 MT48LC4M32B2-7 d4564163 NEC D4564163-A80 d456 SDR100 PC100
Abstract: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Precharge . . . . . . . . , . . . . . . . . 111 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . 114 45.3 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 125 45.8 Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 45.8.1 Read with Auto Precharge Spansion
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TCMS 225 J 250 AVA CL 20 S29WS-N S72WS256ND0 S72WS256NDE S72WS256NEE S72WS256N 16M/32M
Abstract: Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . 114 46.3 Precharge . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . 125 46.8 Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . , 46.8.1 Read with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spansion
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S73WS256N marking code qa1 148 TRANSISTOR BFW 11 pin diagram 32M/16M
Abstract: Product Specifications 3.1 Capacity Table 2. User Addressable Sectors Unformatted Capacity Total User Addressable Sectors in LBA Mode 80 GB 156,301,488 160 GB 312,581,808 Notes: 1 , Mating Order1 P6 V5 5 V Power. Not connected4 2nd Mate P7 V5 5V Power, Pre-charge , connected2 Mating Order (3.3 V Power. pre-charge) 3, 4 2nd Mate P4 Ground 1st Mate P5 , ) Total number of user addressable sectors Obsolete Multi-word DMA modes supported/selected 66 F Intel
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SSDSA1MH080G2 SSDSA2MH080G2 SSDSA1MH160G2 SSDSA2MH160G2 SSDSA1MH080G201 SSDSA1MH160G201 X18-M/X25-M 322296-001US
Abstract: . User Addressable Sectors Unformatted Capacity Total User Addressable Sectors in LBA Mode 80 GB , . pre-charge) 2nd Mate 1st Mate P10 Ground3 P11 DAS6 P12 Ground3, 4 P13 V127 , F Total number of user addressable sectors 0FFFFFFFh (160 GB) 62 X 0h 63 F , for 160 GB on page 1. Updated ordering information on page 2. Updated User Addressable Sectors for Intel
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SSDSA1MH160G1 X18-M hp compaq 6910p compaq 6910P notebook sata ssd controller intel nand flash intel 8201 sata ssd SSDSA1MH080G1 SSDSA2MH080G1 SSDSA2MH160G1 319765-008US
Abstract: ® Solid-State Drive 320 Series 2.0 2.1 Table 1. Product Specifications Capacity User Addressable Sectors Unformatted Capacity (Total User Addressable Sectors in LBA Mode) 78,165,360 156,301,488 234,441 , Test Pin 3.3 V Power 3.3 V Power, pre-charge Definition Mating Order1 2nd Mate 2nd Mate 1st Mate 1st , ; pre-charge) 2nd Mate 1st Mate 1st Mate 1st Mate 1st Mate 2nd Mate 2nd Mate 1st Mate 2nd Mate 1st Mate 1st , number Reserved Extended Number of User Addressable Sectors (QWord) Minimum number of 512-byte data Intel
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JESD218 intel ssd 320 intel 25nm nand flash intel flash 25nm intel ssd ISO-7779 325152-001US
Abstract: Addressable Sectors Unformatted Capacity 80 GB 120 GB 160 GB Total User Addressable Sectors in LBA Mode 156 , (Continued) Function V5 V5 Key Optional Optional Definition 5 V Power. Not connected4 5V Power, Pre-charge , . pre-charge) 2nd Mate 1st Mate 1st Mate 1st Mate 5 V Power 5 V Power 5 V Power 3 Definition Mating Intel
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SSDSA2M080G2XX SSDSA2M160G2XX SSDSA1M160G2XX SSDSA2MH080G2XX SSDSA2MJ080G2XX SSDSA2MH160G2XX 22 pin SSD connector SSDSA1M080G2XX SSDSA2M120G2XX
Abstract: . 6 1.2.5 PRECHARGE , .15 2.4 PRECHARGE OPERATIONS , . A 2 n-bit DRAM is typically organised as 2n/2 rows by 2 n /2 columns. The rows are addressable using the Row Address Select (RAS) signal, and the columns are addressable using the Column Address , every cell. 1.2.5 Precharge It is very important that the bit lines of the DRAM are kept in the Hitachi
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SH7750S SH7751 EDS2516ACTA-7A diagram CD 5265 cs Elpida SDRAM transistor 2N 5269 SH7750 256-M SE-F080
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