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POWEREST Texas Instruments Power Estimation Tool (PET) pdf Buy
POE-PD-POWER-REF Texas Instruments LM5072 5V out 25W IEEE 802.3at Compliant POE+ PD Power Reference Design pdf Buy
SOLARMAGIC-SOLARPOWEROPTIMIZER-REF Texas Instruments SolarMagic SM3320-RF-EV Solar Power Optimizer with RF Communications Reference Design pdf Buy

"content addressable memory" power match precharge

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: match the SDRAM chip chosen for the system. See "Instantiating the Core in SOPC Builder" on page 1­6 , configuration automatically changes values on the Memory Profile and Timing tabs to match the specific , subsystem in units of megabytes, megabits, and number of addressable words. It is useful to compare these , . Delay after power up, before initialization - 100 s The delay from stable clock and power to , . Duration of precharge command (t_rp) - 20 ns Precharge command period. ACTIVE to READ or ... Altera
Original
datasheet

22 pages,
204 Kb

AS4LC1M16S1-10 EP2S60F672C5 MT48LC2M32B2 MT48LC2M32B2-7 NII51005-7 nec v5.0.0 SDR100 MT48LC4M32B2 d456 NEC D4564163-A80 d4564163 MT48LC4M32B2-7 sdram controller d4564163-a80 TEXT
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Abstract: . 6 1.2.5 PRECHARGE , .15 2.4 PRECHARGE OPERATIONS , . A 2 n-bit DRAM is typically organised as 2n/2 rows by 2 n /2 columns. The rows are addressable using the Row Address Select (RAS) signal, and the columns are addressable using the Column Address , every cell. 1.2.5 Precharge It is very important that the bit lines of the DRAM are kept in the ... Hitachi
Original
datasheet

80 pages,
1054.48 Kb

transistor 2N 5269 equivalent EDS2516ACTA-7A Hitachi DSA0071 part MARKING hbs SH4 programming manual SH7750 SH7750S SH7751 transistor 2N 5269 Elpida SDRAM diagram CD 5265 cs TEXT
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Abstract: . 6 PRECHARGE , .13 2.4 Precharge Operations , . The rows are addressable using the Row Address Select (RAS) signal, and the columns are addressable , sense amplifier do the restoring work on every cell. 1.2.5 Precharge It is very important that the bit , precharge can be hidden. One bank can be accessed while the others are being precharged. This approach ... Hitachi
Original
datasheet

69 pages,
775.38 Kb

TRANSISTOR a3w Elpida SDRAM Hitachi Capacitor Guide Hitachi DSA0071 hitachi naming convention hitachi sh3 PD45128163G5-A10-9JF SH-7709A SH7622 SH7706 SH7729R SH7729 SH7727 SH772 SH7709A SH7709 SH7709S TEXT
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Abstract: . 6 PRECHARGE , .13 2.4 Precharge Operations , . The rows are addressable using the Row Address Select (RAS) signal, and the columns are addressable , sense amplifier do the restoring work on every cell. 1.2.5 Precharge It is very important that the bit , precharge can be hidden. One bank can be accessed while the others are being precharged. This approach ... Hitachi Semiconductor
Original
datasheet

70 pages,
807.31 Kb

transistor 2N 5269 equivalent PD45128163G5-A10-9JF SH7622 SH7706 SH7709 SH7709A SH7727 SH7729 SH7729R SH7709S TEXT
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Abstract: Test Pin 3.3 V Power 3.3 V Power, pre-charge Definition Mating Order1 2nd Mate 2nd Mate 1st Mate 1st , - Data Set Management Command Trim attribute Power Management - 3.3 V (1.8-inch form factor) or 5 V (2.5-inch form factor) SATA Supply Rail - SATA interface power management - OS-aware hot plug/removal - Enhanced power-loss data protection Power - Active (MobileMark , values vary by capacity. 2. 4 KB = 4,096 bytes. 3. Device Initiated Power Management (DIPM)-enabled. ... Intel
Original
datasheet

28 pages,
367.16 Kb

ISO-7779 intel ssd intel nand flash intel flash 25nm intel 25nm nand flash intel ssd 320 JESD218 TEXT
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Abstract: on Split Bus Data Sheet ADVANCE INFORMATION Distinctive Characteristics MCP Features Power , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Precharge . . . . . . . . , . . . . . . . . 111 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . 114 45.3 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... Spansion
Original
datasheet

242 pages,
3745.89 Kb

S72WS256NEE S72WS256NDE S72WS256ND0 S29WS-N 225 J 250 AVA CL 20 TCMS S72WS256N 16M/32M TEXT
datasheet frame
Abstract: Power supply voltage of 1.7 to 1.95V High Performance Flash access time: 80ns Flash burst frequency , Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . 114 46.3 Precharge . . . . . . . . . . . . . . . . . . ... Spansion
Original
datasheet

242 pages,
3741.42 Kb

TRANSISTOR BFW 11 pin diagram TCMS S73WS256N marking code qa1 148 32M/16M TEXT
datasheet frame
Abstract: Active Power Down Mode (with MRS bit A12 is set to "1") Precharge Power Down Mode Page 24 Rev. 1.0 , " Active Power Down and Precharge Power Down two additional timing parameters (tANPD and tAXPD) define if , 60 60 60 57 ns Bin (CL-tRCD-TRP) tck · 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V , read and write bursts · Auto-Refresh, Self-Refresh and power saving PowerDown modes · Average Refresh , power supply and are available in FBGA packages. An Auto-Refresh and Self-Refresh mode is provided ... Infineon Technologies
Original
datasheet

91 pages,
1225.58 Kb

HYB18T256800AC-5 HYB18T256800AC HYB18T256400AC-5 HYB18T256400AC-3 HYB18T256400AC HYB18T256160AC-5 HYB18T256160AC-3 HYB18T256160AC TEXT
datasheet frame
Abstract: is set to "1") Precharge Power Down Mode Page 24 Rev. 0.8 August 2003 INFINEON , measured from tAOFD. ODT Timing for Precharge Power-Down and Active Power Power-Down Mode (with slow , 1) Asynchronous ODT timings apply for Precharge Power-Down Mode and "Slow Exit" Active Power Down , the Power Down Modes "Slow Exit" Active Power Down and Precharge Power Down two additional timing , DDR2 Bin (CL-tRCD-TRP) · · · · 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) compatible ... Infineon Technologies
Original
datasheet

88 pages,
1102.46 Kb

128 MB DDR2 SDRAM DDR2-400 HYB18T256160AC-3 HYB18T256160AC-5 HYB18T256400AC HYB18T256400AC-3 HYB18T256400AC-5 HYB18T256800AC HYB18T256800AC-5 vm 256MB DDR 400 HYB18T256160AC TEXT
datasheet frame
Abstract: A12 is set to "1") Precharge Power Down Mode Page 24 Rev. 1.12 March 2004 INFINEON , ODT timing mode switch When entering the Power Down Modes "Slow Exit" Active Power Down and Precharge , ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) compatible) I/O · DRAM organisations with 4, 8 and 16 , Auto-Refresh, Self-Refresh and power saving PowerDown modes · Average Refresh Period 7.8 us at a TCASE lower , a RAS / CAS multiplexing style. The DDR2 devices operate with a 1.8V +/-0.1V power supply and are ... Infineon Technologies
Original
datasheet

90 pages,
1227.18 Kb

HYB18T512800AC-5 HYB18T512800AC HYB18T512400AC-5 HYB18T512400AC HYB18T512160AC-5 HYB18T512160AC TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
No abstract text available
/download/83986109-129761ZC/hitpdf.zip ()
Hitachi 23/02/1996 378.09 Kb ZIP hitpdf.zip
module Two 8-bit PWM Two 32-bit counters and capture registers n Low power controller Real time interface (ASC) Low power controller Teletext interface PROGRAMMABLE TRANSPORT IC FOR DVB APPLICATIONS . 82 12 Clocks and low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.2 Low power control . 83 12.3 Low power configuration registers
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/4556.htm
STMicroelectronics 20/10/2000 332.28 Kb HTM 4556.htm
IDE CONTROLLER n DMA CONTROLLER n INTERRUPT CONTROLLER n TIMER / COUNTERS n POWER MANAGEMENT power down. Host I/F X86 Core HDRAM GDRAM EIDE ISA 82C206 82C206 PCI Slave PCI Master/ Slave PCI BUS ISA BUS control. n Low power and system management modes. n Optimized design for 3.3V operation. n DRAM Controller including CAS pulse width, CAS pre-charge time, and RAS to CAS delay. n 60, 70, 80 & 100ns DRAM speeds. n n Co-processor error support logic. n Power Management n Four power saving modes: On, Doze, Standby
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6375-v2.htm
STMicroelectronics 14/06/1999 468.85 Kb HTM 6375-v2.htm
133MHz 2X data transfer mode w Bus mastering DMA PCI 2.1 interface w ACPI power management interface . 8 2.8 POWER 2.5 DEVICE ENABLE SIGNALS 2.6 DISPLAY INTERFACE 2.7 VIDEO DAC AND PLL ANALOG SIGNALS 2.8 POWER SUPPLY power supply for the video DACs. PLLVDD P Analog power supply for all clock synthesizers. VDD P Digital power supply. GND P Ground. MPCLAMP P MPCLAMP is connected to +5V to protect the 3.3V RIVA128ZX RIVA128ZX from
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6065-v1.htm
STMicroelectronics 02/04/1999 133.16 Kb HTM 6065-v1.htm
IDE CONTROLLER n DMA CONTROLLER n INTERRUPT CONTROLLER n TIMER / COUNTERS n POWER MANAGEMENT power down. Host I/F X86 Core HDRAM GDRAM EIDE ISA 82C206 82C206 PCI Slave PCI Master/ Slave PCI BUS ISA BUS control. n Low power and system management modes. n Optimized design for 3.3V operation. n DRAM Controller including CAS pulse width, CAS pre-charge time, and RAS to CAS delay. n 60, 70, 80 & 100ns DRAM speeds. n n Co-processor error support logic. n Power Management n Four power saving modes: On, Doze, Standby
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6375-v1.htm
STMicroelectronics 02/04/1999 468.89 Kb HTM 6375-v1.htm
. . . . . . . . . . . . 407 14. POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 14.2. POWER MANAGEMENT POWER MANAGEMENT CHAPTER . . . . . . . . . . . . . . . . . . . . . . 445 STPC CLIENT Issue 2.2 - Table 7-53. Bank 0 RAS precharge time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 7-56. Bank 1 RAS precharge time . . . . . . . . . . . . . . . . . . . . . .
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6701.htm
STMicroelectronics 20/10/2000 579.16 Kb HTM 6701.htm
and capture registers n Low power controller Real time clock Watchdog timer n Programmable IO filter engine 2 MPEG decode DMAs IEEE 1284 interface 2 SmartCard interface (ASC) Low power controller . 82 12 Clocks and low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.2 Low power control . 83 12.3 Low power configuration registers
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/4556-v1.htm
STMicroelectronics 02/04/1999 322.32 Kb HTM 4556-v1.htm
UPDATE HISTORY FOR VIDEO CONTROLLER CHAPTER . . . . . . . . . . . . . . . . . . . . . . . 407 14. POWER . . . . . . . . . 409 14.2. POWER MANAGEMENT CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 14.3 UPDATE HISTORY FOR POWER MANAGEMENT CHAPTER . . . . . . . . . . . . . . . . . . . . 61 Table 7-53. Bank 0 RAS precharge time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 7-56. Bank 1 RAS precharge time . . . . . . .
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6701-v1.htm
STMicroelectronics 13/09/2000 564.97 Kb HTM 6701-v1.htm
power controller Real time clock Watchdog timer n Programmable IO module n Professional toolset engine 2 MPEG decode DMAs IEEE 1284 interface 2 SmartCard interface (ASC) Low power controller . 82 12 Clocks and low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.2 Low power control . 83 12.3 Low power configuration registers
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/4556-v2.htm
STMicroelectronics 25/05/2000 324.45 Kb HTM 4556-v2.htm
interface w ACPI power management interface support w 0.35 micron 5LM CMOS w 300 PBGA DESCRIPTION The . 8 2.8 POWER 2.5 DEVICE ENABLE SIGNALS 2.6 DISPLAY INTERFACE 2.7 VIDEO DAC AND PLL ANALOG SIGNALS 2.8 POWER SUPPLY power supply for the video DACs. PLLVDD P Analog power supply for all clock synthesizers. VDD P Digital power supply. GND P Ground. MPCLAMP P MPCLAMP is connected to +5V to protect the 3.3V RIVA128ZX RIVA128ZX from
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6065.htm
STMicroelectronics 20/10/2000 139.1 Kb HTM 6065.htm