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Part Manufacturer Description PDF & SAMPLES
POWEREST Texas Instruments Power Estimation Tool (PET)
SOLARMAGIC-SOLARPOWEROPTIMIZER-REF Texas Instruments SolarMagic SM3320-RF-EV Solar Power Optimizer with RF Communications Reference Design
POE-PD-POWER-REF Texas Instruments LM5072 5V out 25W IEEE 802.3at Compliant POE+ PD Power Reference Design
SN74SSQEC32882ZALR Texas Instruments JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
5962-9681201QLA Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE 1149.1 24-CDIP -55 to 125
5962-9681201Q3A Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE 1149.1 28-LCCC -55 to 125

"content addressable memory" power match precharge

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: match the SDRAM chip chosen for the system. See "Instantiating the Core in SOPC Builder" on page 1­6 , configuration automatically changes values on the Memory Profile and Timing tabs to match the specific , subsystem in units of megabytes, megabits, and number of addressable words. It is useful to compare these , . Delay after power up, before initialization - 100 s The delay from stable clock and power to , . Duration of precharge command (t_rp) - 20 ns Precharge command period. ACTIVE to READ or Altera
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NII51005-7 d4564163-a80 sdram controller MT48LC4M32B2-7 d4564163 NEC D4564163-A80 d456 PC100
Abstract: . 6 1.2.5 PRECHARGE , .15 2.4 PRECHARGE OPERATIONS , . A 2 n-bit DRAM is typically organised as 2n/2 rows by 2 n /2 columns. The rows are addressable using the Row Address Select (RAS) signal, and the columns are addressable using the Column Address , every cell. 1.2.5 Precharge It is very important that the bit lines of the DRAM are kept in the Hitachi
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SH7750S SH7751 EDS2516ACTA-7A diagram CD 5265 cs Elpida SDRAM transistor 2N 5269 SH7750 256-M SE-F080
Abstract: . 6 PRECHARGE , .13 2.4 Precharge Operations , . The rows are addressable using the Row Address Select (RAS) signal, and the columns are addressable , sense amplifier do the restoring work on every cell. 1.2.5 Precharge It is very important that the bit , precharge can be hidden. One bank can be accessed while the others are being precharged. This approach Hitachi
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SH7622 SH7706 SH7709 SH7709A SH7709S SH7727 SH772 SH7729
Abstract: . 6 PRECHARGE , .13 2.4 Precharge Operations , . The rows are addressable using the Row Address Select (RAS) signal, and the columns are addressable , sense amplifier do the restoring work on every cell. 1.2.5 Precharge It is very important that the bit , precharge can be hidden. One bank can be accessed while the others are being precharged. This approach Hitachi Semiconductor
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SH7729R PD45128163G5-A10-9JF transistor 2N 5269 equivalent
Abstract: Test Pin 3.3 V Power 3.3 V Power, pre-charge Definition Mating Order1 2nd Mate 2nd Mate 1st Mate 1st , - Data Set Management Command Trim attribute Power Management - 3.3 V (1.8-inch form factor) or 5 V (2.5-inch form factor) SATA Supply Rail - SATA interface power management - OS-aware hot plug/removal - Enhanced power-loss data protection Power - Active (MobileMark , values vary by capacity. 2. 4 KB = 4,096 bytes. 3. Device Initiated Power Management (DIPM)-enabled. Intel
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JESD218 intel ssd 320 intel 25nm nand flash intel flash 25nm intel nand flash intel ssd 325152-001US
Abstract: on Split Bus Data Sheet ADVANCE INFORMATION Distinctive Characteristics MCP Features Power , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Precharge . . . . . . . . , . . . . . . . . 111 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . 114 45.3 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spansion
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TCMS 225 J 250 AVA CL 20 S29WS-N S72WS256ND0 S72WS256NDE S72WS256NEE S72WS256N 16M/32M
Abstract: Power supply voltage of 1.7 to 1.95V High Performance Flash access time: 80ns Flash burst frequency , Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . 114 46.3 Precharge . . . . . . . . . . . . . . . . . . Spansion
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S73WS256N marking code qa1 148 TRANSISTOR BFW 11 pin diagram 32M/16M
Abstract: Active Power Down Mode (with MRS bit A12 is set to "1") Precharge Power Down Mode Page 24 Rev. 1.0 , " Active Power Down and Precharge Power Down two additional timing parameters (tANPD and tAXPD) define if , 60 60 60 57 ns Bin (CL-tRCD-TRP) tck · 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V , read and write bursts · Auto-Refresh, Self-Refresh and power saving PowerDown modes · Average Refresh , power supply and are available in FBGA packages. An Auto-Refresh and Self-Refresh mode is provided Infineon Technologies
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HYB18T256400AC HYB18T256800AC HYB18T256160AC-3 HYB18T256160AC-5 HYB18T256400AC-3 HYB18T256400AC-5 HYB18T256160AC DDR2-400 DDR2-533 DDR2-667
Abstract: is set to "1") Precharge Power Down Mode Page 24 Rev. 0.8 August 2003 INFINEON , measured from tAOFD. ODT Timing for Precharge Power-Down and Active Power Power-Down Mode (with slow , 1) Asynchronous ODT timings apply for Precharge Power-Down Mode and "Slow Exit" Active Power Down , the Power Down Modes "Slow Exit" Active Power Down and Precharge Power Down two additional timing , DDR2 Bin (CL-tRCD-TRP) · · · · 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) compatible Infineon Technologies
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vm 256MB DDR 400 HYB18T256800AC-5 128 MB DDR2 SDRAM HYB18T256400/800/160AC
Abstract: A12 is set to "1") Precharge Power Down Mode Page 24 Rev. 1.12 March 2004 INFINEON , ODT timing mode switch When entering the Power Down Modes "Slow Exit" Active Power Down and Precharge , ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) compatible) I/O · DRAM organisations with 4, 8 and 16 , Auto-Refresh, Self-Refresh and power saving PowerDown modes · Average Refresh Period 7.8 us at a TCASE lower , a RAS / CAS multiplexing style. The DDR2 devices operate with a 1.8V +/-0.1V power supply and are Infineon Technologies
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HYB18T512400AC HYB18T512800AC HYB18T512160AC-5 HYB18T512400AC-5 HYB18T512800AC-5 HYB18T512160AC DDR2-553
Abstract: . ODT Timing for Precharge Power-Down and Low Power Power-Down Mode T-7 CK, CK T-6 T-5 T , Self-Refresh · Power Saving Power-Down modes · 7.8 us Maximum Average Periodic Refresh Interval · Lead and , 0.1V Power Supply Voltage · 4 internal memory banks · Programmable CAS Latency: 3, 4 and 5 · , single 1.8V +/-0.1V power supply and are available in FBGA packages. An Auto-Refresh and Self-Refresh , NC,(A15) NC,(A13) Notes: 1) VDDL and VSSDL are power and ground for the DLL.They are isolated on Infineon Technologies
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HYB18T256400AF37 HYB18T256400/800/160AF
Abstract: Down Mode (with MRS bit A12 is set to "1") Precharge Power Down Mode Page 24 Rev. 0.92 December , Down and Precharge Power Down two additional timing parameters (tANPD and tAXPD) define if synchronous , 667 5 15 15 60 4 12 12 57 tck ns ns ns · 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL , Auto-Refresh, Self-Refresh and power saving PowerDown modes · Average Refresh Period 7.8us at a TCASE lower , DDR2 devices operate with a 1.8V +/-0.1V power supply and are available in FBGA packages. An Infineon Technologies
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ODT01
Abstract: . ODT Timing for Precharge Power-Down and Low Power Power-Down Mode T-7 CK, CK T-6 T-5 T , Strength Data-Output Driver · Auto-Refresh and Self-Refresh · Power Saving Power-Down modes · 7.8 us , components 84 pin PTFBPA for x16 components · 1.8V ± 0.1V Power Supply Voltage · 4 internal memory banks · , . These devices operate with a single 1.8V +/-0.1V power supply and are available in FBGA packages. An , power and ground for the DLL.They are isolated on the device from VDD, VDDQ, VSS and VSSQ. 2) NC,(A14 Infineon Technologies
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HYB18T512400AF5 HYB18T512400/800/160AF
Abstract: GB of addressable memory. The thirteen row/column multiplexed address signals (SDMA[12:0]) in , SDRAM configurations, the value of PGMAX multiplied by 64 determines the activate to precharge interval , active page by issuing a precharge bank command. PGMAX must be sufficiently less than the maximum row active time for the SDRAM device to ensure that the issuing of a precharge command is not stalled by a , complete before issuing the precharge command to the SDRAM. In the worst case, the Tsi107 initiates a Integrated Device Technology
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AN005 F010 F018 registered buffer parity 80C2000
Abstract: . ODT Timing for Precharge Power-Down and Low Power Power-Down Mode T-7 T-6 T-5 T-4 T , ODT (On-Die Termination) · 4 bit prefetch architecture · Power Saving Power-Down modes · 1.8V ± 0.1V Power Supply Voltage · 8 internal memory banks, selectable by three bank address bits · , , column, and bank address devices. These devices operate with a single 1.8V +/-0.1V power supply and , NC Notes: 1) VDDL and VSSDL are power and ground for the DLL.They are isolated on the device Infineon Technologies
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HYB18T1G800AF-5 HYB18T1G800AF-3 HYB18T1G400AF-5 HYB18T1G400AF-3 HYB18T1G160AF-5 HYB18T1G160AF-3 HYB18T1G400/800/160AF
Abstract: modes are: Slow Exit Acitve Power Down Mode (with MRS bit A12 is set to "1") Precharge Power Down Mode , Precharge Power-Down and Active Power Power-Down Mode (with slow exit) (Asynchronous ODT timings) T0 , Precharge Power-Down Mode and "Slow Exit" Active Power Down Mode (MRS bit A12 set to "1"), where the on-die , Power Down and Precharge Power Down two additional timing parameters (tANPD and tAXPD) define if , (CL-tRCD-TRP) · 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) compatible) I/O · DRAM organisations with Infineon Technologies
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HYB18T512400/800/160AC
Abstract: . I Technology Power 2 2 1 0.13 um , memory timings, address and bank sizes, and memory addressing modes are programmable. System power can , , configuration registers and other important addressable locations, the maximum DDR memory is limited to 3.5 , which enables the DDR SDRAM controller power management and self-refresh features. Table 3. IBM 440GP SDRAM0_CFG1 Bits 1 0 SRE 1 1 Name PMEN Description Self-refresh entry Power management Motorola
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AN2661 MPC8540 LG E500 MPC8560 user openpic MPC8560
Abstract: disabled. These modes are: Slow Exit Active Power Down Mode (with MRS bit A12 is set to "1") Precharge , Precharge Power-Down Mode and "Slow Exit" Active Power Down Mode (MRS bit A12 set to "1"), where the on-die , Down Modes "Slow Exit" Active Power Down and Precharge Power Down two additional timing parameters , Data Rate CAS Latency (CL) tRCD tRP tRAS tRC tck ns ns ns ns · 1.8V ± 0.1V Power Supply 1.8 V ± , Auto-Refresh, Self-Refresh and power saving PowerDown modes · Average Refresh Period 7.8 us at a TCASE lower Infineon Technologies
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Abstract: . 2-38 Recommended power states , 3-27 Figure 3-28 Figure 3-29 Figure 3-30 Figure 3-31 xii PRECHARGE to command and AUTO REFRESH to command timing, tRP and tRFC . 2-30 ACTIVE to PRECHARGE, and PRECHARGE to PRECHARGE timing , . 2-44 Force precharge with zero force precharge time . 2-44 Force precharge after power_dwn_prd time ARM
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DMC-340 Jedec JESD209 DMC TOOL PL301 DMC-340 Supplement to AMBA Designer trustzone 0331G ID111809
Abstract: Table 1-4: Power segment GND P6 Ground P7 GND Ground 5V Pre-Charge 5V 5V Ground , ­ Sustained write: up to 135 MB/sec Zero power data retention ­ No battery required for data , °C ­ Storage: -40°C to 100°C Supply voltage ­ 5.0 V ± 5% Low power consumption ­ Active , -pin SATA male connector ­ 15-pin SATA power connector RoHS compliant Capacities ­ 8, 16, 32, 64 , Flash bad-block management ­ S.M.A.R.T. technology ­ Power Failure Management ­ Quick Erasae NAND Apacer Technology
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sata male 15 pin sata AP-SAFD254QA008GS-ETE SAFD254 Apacer block diagram of sata SSD drive AP-SAFD254QA
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