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POWERSTEP01 STMicroelectronics System-in-package integrating microstepping controller and 10 A power MOSFETs
POWERSTEP01TR STMicroelectronics System-in-package integrating microstepping controller and 10 A power MOSFETs
POWEREST Texas Instruments Power Estimation Tool (PET)
POWERSTRIP-6 HellermannTyton 6 OUTLET POWERSTRIP
POWERSTRIP-10 HellermannTyton 10 OUTLET POWERSTRIP
POWERSTRIP-10S HellermannTyton 10 OUTLET POWERSTRIP W/SRG PROTE

"content addressable memories" power match

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Addressable Memory ( NCAM ) match is detected the device will then output a Match Flag and the Address of , Content Addressable Memory ( NCAM ) CAM Status After Hardware Reset or Power On Reset 1480 64 bits , NL81480A NL82480A 1K X 64 2K X 64 Content Addressable Memory ( NCAM ) Features · · · , Reset pin works in parallel to internal Power On Reset circuitry 44-pin PLCC package 5V CMOS , Priority Encoder / RESET DEMUX Validity Bits / EC Memory Control, Match & Flag Logic Netlogic Microsystems
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netlogic CAM Netlogic Content Addressable Memory 01AEH Priority Encoder CAM I/O15 NL8X480A I/O15-0 44-PIN
Abstract: at applications requiring large look-up tables. Based on ternary Content Addressable Memory (CAM , , SCT9000, SCT9020 & SCT9022). Key Features · 18,874,368 bits true ternary Content Addressable Memory , , enabling vendors to support both IPv4 and IPv6 classification in a single chip. Offering the lowest power consumption in its class, the SCT1842 also supports a complex power management feature based on a software programmable, patent pending block select technique. Power management is deterministic in nature, not -
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SCT2000 0C-48 Ternary CAM Sibercore ternary content addressable memory Sibercore Technologies SCT9022 Sibercore Technologies OC-192 SCT-001-1842
Abstract: today's system requirements. Based on ternary Content Addressable Memory (CAM) technology, the SCT9022 , Addressable Memory (CAM) storage · Supports entry widths of 36, 72, 144, 288, 360, 432 and 576-bits · 3 , support both IPv4 and IPv6 classification in a single chip. Offering the lowest power consumption in its class, the SCT9022 also supports a complex power management feature based on a software programmable, patent pending block select technique. Power management is deterministic in nature, not statistical -
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tag 9022 9022 OC-48 SCT-001-9022
Abstract: The SCT9020 offers the fastest ternary Content Addressable Memory (CAM) based Packet Forwarding , Addressable Memory (CAM) storage · Register Configurable as 32K x 288, 64K x 144, 128K x 72 , 256K x 36 or , performance penalty. SiberCore is pleased to introduce new power management features in the Ultra-9M family. If the power management features are fully utilized, a cascade of four Ultra-9Ms can be configured to consume up to an order of magnitude less power than competing solutions. The SCT9020 CAM-based -
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OC-768 Ultra-9M longest prefix match CAM ternary SCT-001-9020
Abstract: family offering the fastest ternary Content Addressable Memory (CAM) based Packet Forwarding Engine , . Key Features · 9,437,184 bits true ternary Content Addressable Memory (CAM) storage · Register , to introduce new power management features in the Ultra-9M. If the power management features are , less power than competing solutions. The Ultra-9M is the only CAM-based PFE to support fully , Classification and Filtering · Classless Inter-Domain Routing (CIDR) · Longest Prefix Match (LPM) · Network Sibercore Technologies
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Abstract: MCM69C432 100 (TQ) TQFP 180 ns Match Time 4Q97 Content addressable memory for communication applications. 16K connections. 4K x 64 3.3 V MCM69C232 100 (TQ) TQFP 160 ns Match Time Now Content addressable memory for communication applications. 4K connections. MPC2605 241 , programmed while remaining in the system. Motorola's low power flash memory products are ideally suited for , , VPP = 5.0 V Power Supply 3.3 Volt 3.3 Volt 3.3 Volt 3.3 Volt Power Supply 120 ns 120 Motorola
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mips r5000 48-pin TSOP package tray mcm6249 Motorola Master Selection Guide XCM 12 MCM69R820A
Abstract: featuring a high level of support block integration and low power consumption. The LPC1700 microcontrollers , SYSTICK timer, Wakeup Interrupt Controller (WIC), Memory Protection Unit (MPU), four reduced power modes , , ultra-low power RTC with separate battery supply, and up to 70 general purpose I/O pins. The LPC1700 , Blocks 4. Power Structure and Management 5. Peripherals 6. Miscellaneous AN10878_1 Application , -bit DAC interfaces. · DMA can also be triggered by a Timer match condition. · GPIO registers are NXP Semiconductors
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LPC1700 cortex m3 LPC1700 i2c LPC1700 adc LPC2368 user manual LPC1768 bootloader NXP LPC1768 LPC2300/2400 LPC2000 RS-485/EIA-485
Abstract: package. The fully static design of the T89C51RD2 allows to reduce system power consumption by bringing , software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is , Programming) using standard VCC power supply. FLASH contains low level FLASH programming routines and a , Power control modes: · Idle Mode. · Power-down mode. · Power-off Flag. 1 T89C51RD2 · Power supply , , RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON Power and clock control registers: PCON Atmel
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89C51RD2 parallel programming 89c51rd2 application notes atmel 89c51rd2 T87C51RD2 80C51 80C52 89C51RD2 PDIL40 PLCC44 VQFP44
Abstract: T89C51RD2 allows to reduce system power consumption by bringing the clock frequency down to any value, even , further reduction in power consumption. In the idle mode the CPU is frozen while the peripherals and the , sources with 4 priority levels ISP (In System Programming) using standard VCC power supply. FLASH contains , Timer (One-time enabled with Reset-Out) · · Power control modes: · Idle Mode. · Power-down mode. · Power-off Flag. 1 Preliminary T89C51RD2 · Power supply: 5V +/- 10% or 3V ­ 10,+20% (Metal Temic Semiconductors
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PLCC68 VQFP64
Abstract: ports in a 64/68 pins package. The fully static design of the T89C51RD2 allows to reduce system power , has 2 software-selectable modes of reduced activity for further reduction in power consumption. In , Interrupt sources with 4 priority levels ISP (In System Programming) using standard VCC power supply. · , ALE) · Hardware Watchdog Timer (One-time enabled with Reset-Out) · Power control modes: · Idle Mode. · Power-down mode. 1 T89C51RD2 · Power supply: - M version: Commercial and industrial Atmel
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89C51RD2 pwm application note 64Kx8 RAM ATMEL 89C51RD2 datasheet T89C51RD2 Instruction set Architecture T89C51RD2 Bootloader Errata Sheet 89C51RD2 EEPROM
Abstract: select via keyboard 36 digit LNR (Last Number Redial) 20 memories addressable with direct keys and the , . 25 Vss Negative terminal of power supply. 26 TB Tone burst output: LS high MT high , see p. 7 Error (%) ± 0.7% Positive terminal of power supply Keyboard Layout COLUMN 2 , procedures revert it to default LD mode: Power On Reset The on chip analogue power on reset circuit , sliding cursor protocol is implemented. If new entries match the previous LNR RAM contents, pressing the austriamicrosystems AG
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AS2574B AS2590 auto dialling circuit AMS handsfree chip diode code m10
Abstract: keyboard 36 digit LNR (Last Number Redial) 20 memories addressable with direct keys and the 2nd key or , internal pull-down resistor. Debounce 25 ms. Negative terminal of power supply. Tone burst output: LS high , 28 Vdd Positive terminal of power supply Keyboard Layout COLUMN 3 4 5 In off-hook state all , . 1995 Data Sheet Power On Reset The on chip analogue power on reset circuit monitors the supply , cursor protocol is implemented. If new entries match the previous LNR RAM contents, pressing the LNR key -
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AUSTRIA MIKRO SYSTEME INTERNATIONAL
Abstract: ) Using Standard VCC Power Supply Boot Flash Contains Low Level Flash Programming Routines and a Default , with Reset-out) Power Control Modes: ­ Idle Mode ­ Power-down Mode Power Supply: ­ M version , package. The fully static design of the T89C51RD2 allows to reduce system power consumption by bringing , software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is , : Contact the Sales Office for ground connection. 40 44 38 I Power Supply: This is the power Atmel
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T89C51RD2-SLSCM atmel 80C52 T89C51RD2 ordering information 4243G
Abstract: Levels ISP (In-System Programming) Using Standard VCC Power Supply Boot Flash Contains Low Level Flash , ALE) â'" Hardware Watchdog Timer (One-time Enabled with Reset-out) Power Control Modes: â'" Idle Mode â'" Power-down Mode Power Supply: â'" M version: Commercial and Industrial 4.5V to 5.5V: 40 , fully static design of the T89C51RD2 allows to reduce system power consumption by bringing the clock , of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen Atmel
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Abstract: Interrupt Sources With 4 Priority Levels ISP (In-System Programming) Using Standard VCC Power Supply Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply Boot ROM Contains Serial Loader for , Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag Power Control Modes: Idle Mode, Power-down Mode Power Supply: 2.7V to 5.5V Temperature Ranges: Industrial (-40 to +85°C) Packages: PLCC44 , of XRAM. The fully static design of the AT89C51RE2 allows to reduce system power consumption by Atmel
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TI PLCC44 Watchdog AT89C51RE2 VQFP64 stepping motor MB02 intel 8051 microcontroller architecture FCB 20 BP 8051 basics 7663B
Abstract: unchanged during the Write cycle. The Match line associated with each location is fed into a Priority , , along with flags indicating Match, Multiple Match and Full. The Match and Full flags are also available , Match and System Full indications in vertically cascaded LAN CAM arrays. In such arrays, if no match , information during system initialization. During a Comparison cycle, the 10 bits of the Match address in a , within the P1480. Conditions set by the contents of this register are Reset, enable or disable Match -
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HB3113
Abstract: Interrupt Sources With 4 Priority Levels ISP (In-System Programming) Using Standard VCC Power Supply Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply Boot ROM Contains Serial Loader for , Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag Power Control Modes: Idle Mode, Power-down Mode Power Supply: 2.7V to 5.5V Temperature Ranges: Industrial (-40 to +85°C) Packages: PLCC44 , of XRAM. The fully static design of the AT89C51RE2 allows to reduce system power consumption by Atmel
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8051 coding for temperature measurement microcontroller 8051 multi keyboard intel 8051 microcontroller dc motor interface with 8051 AT89C51RE2-RLTUM
Abstract: P8xCE559 has two software selectable modes of power reduction - Idle Mode and power-down mode. The Idle , Analog ground for ADC Analog power supply (+5 V) for ADC AVSS2 AVDD2 77 76 Analog ground; for PLL oscillator Analog power supply; (+5 V) for PLL oscillator P5.7 ­ P5.0 5 ­ 12 Port 5 8 , ) VDD1, VDD2, VDD3, VDD4 14, 28, 53, 66 Digital power supply: +5 V power supply pins during normal operation and power reduction modes. All pins must be connected. VSS1, VSS2 VSS3, VSS4 13 Philips Semiconductors
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P83CE559 P80CE559 inverter sla 1003 P80CE559EBB P80CE559EFB ste ae c 642 P83CE559/P80CE559 P80CE559/P83CE559 CE559 P89CE559
Abstract: two software selectable modes of power reduction - Idle Mode and power-down mode. The Idle Mode , digital conversion reference resistor. AVSS1 AVDD1 3 4 Analog ground for ADC Analog power supply (+5 V) for ADC AVSS2 AVDD2 77 76 Analog ground; for PLL oscillator Analog power supply , , 28, 53, 66 Digital power supply: +5 V power supply pins during normal operation and power , .7 CMSR0 } CMSR1 } CMSR2 } compare and set/reset CMSR3 } outputs on a match with timer T2 CMSR4 Philips Semiconductors
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P83CE558 P80CE558 P89CE558 philips 3595 P8xCE558 P80CE558EFB P80CE558EBB P83CE558/P80CE558/P89CE558 P80CE558/P83CE558/P89CE558 CE558
Abstract: and logic. In addition, the P8xC557E4 has two software selectable modes of power reduction â'" Idle , resistor. AVssi avdd1 3 4 Analog ground for ADC Analog power supply (+5 V) for ADC AVss2 avdd2 77 76 Analog ground; for PLL oscillator Analog power supply; (+5 V) for PLL oscillator P5.7- P5.0 5-12 Port5 8 , > vdd3> vdd4 14, 28, 53, 66 Digital power supply: +5 V power supply pins during normal operation and power reduction modes. All pins must be connected. vss1. vss2 vss3> vss4 13, 29, 54, 67 Digital ground -
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cmo tcon P80C557E4 P80C557E4EBB P80C557E4EFB P83C557E4 P89C557E4 P83C557E4/P80C557E4/P89C557E4 P80C557E4/P83C557E4/P89C557E4 C557E4
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