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"content addressable memories" power match

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Abstract: Addressable Memory ( NCAM ) match is detected the device will then output a Match Flag and the Address of , Content Addressable Memory ( NCAM ) CAM Status After Hardware Reset or Power On Reset 1480 64 bits , NL81480A NL81480A NL82480A NL82480A 1K X 64 2K X 64 Content Addressable Memory ( NCAM ) Features · · · , Reset pin works in parallel to internal Power On Reset circuitry 44-pin PLCC package 5V CMOS , Priority Encoder / RESET DEMUX Validity Bits / EC Memory Control, Match & Flag Logic ... Netlogic Microsystems
Original
datasheet

18 pages,
173.86 Kb

"Content Addressable Memory" netlogic 016Fh 0230H 0309H 0324H 0427H 0507H 0804H 0B22H 0927H NetLogic Microsystems 0127H Priority Encoder CAM 01AEH NL81480A NL82480A Content Addressable Memory NL81480A NL82480A Netlogic NL81480A NL82480A "Content Addressable Memory" NL81480A NL82480A netlogic CAM NL81480A NL82480A NL81480A NL81480A NL82480A NL82480A TEXT
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Abstract: at applications requiring large look-up tables. Based on ternary Content Addressable Memory (CAM , , SCT9000 SCT9000, SCT9020 SCT9020 & SCT9022 SCT9022). Key Features · 18,874,368 bits true ternary Content Addressable Memory , , enabling vendors to support both IPv4 and IPv6 classification in a single chip. Offering the lowest power consumption in its class, the SCT1842 SCT1842 also supports a complex power management feature based on a software programmable, patent pending block select technique. Power management is deterministic in nature, not ... Original
datasheet

2 pages,
407.85 Kb

0C-48 longest prefix match CAM SCT9022 Sibercore Technologies Sibercore Technologies SCT9022 SCT9000 ternary content addressable memory Sibercore SCT2000 SCT1842 Ternary CAM SCT9020 TEXT
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Abstract: today's system requirements. Based on ternary Content Addressable Memory (CAM) technology, the SCT9022 SCT9022 , Addressable Memory (CAM) storage · Supports entry widths of 36, 72, 144, 288, 360, 432 and 576-bits · 3 , support both IPv4 and IPv6 classification in a single chip. Offering the lowest power consumption in its class, the SCT9022 SCT9022 also supports a complex power management feature based on a software programmable, patent pending block select technique. Power management is deterministic in nature, not statistical ... Original
datasheet

2 pages,
394.62 Kb

SCT9000 9022 "Content Addressable Memory" ternary Ternary CAM SCT2000 SCT9022 Sibercore Technologies SCT9022 tag 9022 SCT9020 TEXT
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Abstract: The SCT9020 SCT9020 offers the fastest ternary Content Addressable Memory (CAM) based Packet Forwarding , Addressable Memory (CAM) storage · Register Configurable as 32K x 288, 64K x 144, 128K x 72 , 256K x 36 or , performance penalty. SiberCore is pleased to introduce new power management features in the Ultra-9M family. If the power management features are fully utilized, a cascade of four Ultra-9Ms can be configured to consume up to an order of magnitude less power than competing solutions. The SCT9020 SCT9020 CAM-based ... Original
datasheet

2 pages,
310.69 Kb

ternary content addressable memory ternary OC-768 longest prefix match CAM Ultra-9M Ternary CAM Sibercore SCT9020 TEXT
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Abstract: family offering the fastest ternary Content Addressable Memory (CAM) based Packet Forwarding Engine , . Key Features · 9,437,184 bits true ternary Content Addressable Memory (CAM) storage · Register , to introduce new power management features in the Ultra-9M. If the power management features are , less power than competing solutions. The Ultra-9M is the only CAM-based PFE to support fully , Classification and Filtering · Classless Inter-Domain Routing (CIDR) · Longest Prefix Match (LPM) · Network ... Sibercore Technologies
Original
datasheet

2 pages,
407.65 Kb

Ultra-9M ternary Sibercore Technologies SCT9000 OC-768 Ternary CAM TEXT
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Abstract: MCM69C432 MCM69C432 100 (TQ) TQFP 180 ns Match Time 4Q97 Content addressable memory for communication applications. 16K connections. 4K x 64 3.3 V MCM69C232 MCM69C232 100 (TQ) TQFP 160 ns Match Time Now Content addressable memory for communication applications. 4K connections. MPC2605 MPC2605 241 , programmed while remaining in the system. Motorola's low power flash memory products are ideally suited for , , VPP = 5.0 V Power Supply 3.3 Volt 3.3 Volt 3.3 Volt 3.3 Volt Power Supply 120 ns 120 ... Motorola
Original
datasheet

7 pages,
57.61 Kb

XCM f MCM69L818A MCM69L819A MCM69L820A MCM69R736A MCM69R737A MCM69R818A MCM69R819A MCM69R820A XCM 12 Motorola Master Selection Guide mcm6249 48-pin TSOP package tray mips r5000 TEXT
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Abstract: featuring a high level of support block integration and low power consumption. The LPC1700 LPC1700 microcontrollers , SYSTICK timer, Wakeup Interrupt Controller (WIC), Memory Protection Unit (MPU), four reduced power modes , , ultra-low power RTC with separate battery supply, and up to 70 general purpose I/O pins. The LPC1700 LPC1700 , Blocks 4. Power Structure and Management 5. Peripherals 6. Miscellaneous AN10878 AN10878_1 Application , -bit DAC interfaces. · DMA can also be triggered by a Timer match condition. · GPIO registers are ... NXP Semiconductors
Original
datasheet

24 pages,
562.32 Kb

u860 diode lpc1768 gpio interrupt LPC1700 ADC code example LPC2368 gpio ports PROCESS CONTROL TIMER BASED TOPICS AN10878 lpc2368 applications notes RS 485 eia ARM LPC1768 instruction set LPC1768 lpc1768 gpio arm7 iap NXP LPC1768 LPC1768 bootloader LPC2368 user manual LPC1700 adc LPC1700 i2c LPC1700 cortex m3 LPC1700 TEXT
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Abstract: package. The fully static design of the T89C51RD2 T89C51RD2 allows to reduce system power consumption by bringing , software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is , Programming) using standard VCC power supply. FLASH contains low level FLASH programming routines and a , Power control modes: · Idle Mode. · Power-down mode. · Power-off Flag. 1 T89C51RD2 T89C51RD2 · Power supply , , RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON Power and clock control registers: PCON ... Atmel
Original
datasheet

87 pages,
572.76 Kb

T87C51RD2 atmel 89c51rd2 89c51rd2 application notes 89C51RD2 parallel programming T89C51RD2 80C51 80C52 TEXT
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Abstract: T89C51RD2 T89C51RD2 allows to reduce system power consumption by bringing the clock frequency down to any value, even , further reduction in power consumption. In the idle mode the CPU is frozen while the peripherals and the , sources with 4 priority levels ISP (In System Programming) using standard VCC power supply. FLASH contains , Timer (One-time enabled with Reset-Out) · · Power control modes: · Idle Mode. · Power-down mode. · Power-off Flag. 1 Preliminary T89C51RD2 T89C51RD2 · Power supply: 5V +/- 10% or 3V ­ 10,+20% (Metal ... Temic Semiconductors
Original
datasheet

84 pages,
732.52 Kb

89c51rd2 application notes T89C51RD2 80C51 80C52 TEXT
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Abstract: ports in a 64/68 pins package. The fully static design of the T89C51RD2 T89C51RD2 allows to reduce system power , has 2 software-selectable modes of reduced activity for further reduction in power consumption. In , Interrupt sources with 4 priority levels ISP (In System Programming) using standard VCC power supply. · , ALE) · Hardware Watchdog Timer (One-time enabled with Reset-Out) · Power control modes: · Idle Mode. · Power-down mode. 1 T89C51RD2 T89C51RD2 · Power supply: - M version: Commercial and industrial ... Atmel
Original
datasheet

86 pages,
568.56 Kb

89C51RD2 89c51rd2 application notes 80C52 ANM072 xaf hsb PDIL40 T89C51RD2 PLCC68 PLCC44 philips 89C51RD2 89C51RD2 EEPROM T89C51RD2 Bootloader Errata Sheet T89C51RD2 Instruction set Architecture 89C51RD2 parallel programming ATMEL 89C51RD2 datasheet 64Kx8 RAM 89C51RD2 pwm application note atmel 89C51RD2 80C51 TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
ADDRESSABLE MEMORIES MOTOROLA DEVELOPS CONTENT ADDRESSABLE MEMORIES FOR SALE AT sampling the MCM69C232 MCM69C232 and MCM69C432 MCM69C432 very low cost content addressable memories (CAM) designed 64 MCM69C232 MCM69C232 and the 16K x 64 MCM69C432 MCM69C432. In each part, the widths of the match field and the output field are programmable, with the match time designed to be 160 nanoseconds (ns). As a result include: . Single 3.3 V +-5% power supply . 50MHz maximum clock rate . Programmable 12 to 64
/datasheets/files/motorola/design-n/home2/press/html/pr960_98.htm
Motorola 25/11/1996 5.14 Kb HTM pr960_98.htm
ADDRESSABLE MEMORIES MOTOROLA DEVELOPS CONTENT ADDRESSABLE MEMORIES FOR SALE AT sampling the MCM69C232 MCM69C232 and MCM69C432 MCM69C432 very low cost content addressable memories (CAM) designed 64 MCM69C232 MCM69C232 and the 16K x 64 MCM69C432 MCM69C432. In each part, the widths of the match field and the output field are programmable, with the match time designed to be 160 nanoseconds (ns). As a result include: . Single 3.3 V +-5% power supply . 50MHz maximum clock rate . Programmable 12 to 64
/datasheets/files/motorola/design-n/home2/press/html/pr960_99.htm
Motorola 25/11/1996 5.14 Kb HTM pr960_99.htm
Content Addressable Memories for Sale at Dramatically Lower Prices than Industry Standard Fast SRAM content addressable memories (CAM) designed specifically for internetworking applications that require widths of the match field and the output field are programmable, with the match time designed to be 160 Product features include: Single 3.3 V +-5% power supply 50MHz maximum clock rate Programmable 12 to 64 bit wide match field (MCM69C232 MCM69C232) Programmable 14 to 64 bit wide match field
/datasheets/files/motorola/design-n/sps/fastsram/093096ca.htm
Motorola 25/11/1996 7.45 Kb HTM 093096ca.htm
256Kbit-1Mbit, BurstRAMs successfully address the issues of speed, cost efficiency, and power consumption that Ethernet and ATM system designs, we're working on a flexible 4K x 64 Content Addressable Memory (CAM) device for clock speeds up to 100MHz. Widths of the match and output fields will be programmable and match time will be 160ns with a cycle time of 320ns. Another innovation we're developing is a family
/datasheets/files/motorola/design-n/sps/fastsram/shark.htm
Motorola 25/11/1996 8.79 Kb HTM shark.htm
XC9500 XC9500 CPLD Power Sequencing 30 KB XAPP110 XAPP110 XC9500 XC9500 Understanding XC9500XL XC9500XL CPLD Power 90 KB Power Down Mode With Spartan-XL FPGAs 20 KB XAPP124 XAPP124 Spartan-XL Conserving Power With Auto Power Down Mode in Spartan-XL FPGAs   Virtex Power Estimator User Guide 90 KB XAPP152 XAPP152
/datasheets/files/xilinx/docs/rp00003/rp00319.htm
Xilinx 19/03/2000 192.75 Kb HTM rp00319.htm
remains unchanged during and after a reset as long as the power supply is not turned off. The XRAM content is also maintained when the C500 microcontrollers are in power saving modes. 1.2.2.1 Internal addressable bits is located at byte addresses 20H - 2FH of the lower data RAM. Bit 0 of the internal data byte area typically provides 128 bytes of direct addressable SFRs. The SFRs which are located at addresses , complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or
/datasheets/files/infineon/mc_data/dave/products/c504.dip
Infineon 01/02/2000 5668.08 Kb DIP c504.dip
No abstract text available
/download/99213260-653674ZC/silverbox-cd.zip ()
Philips 18/06/2004 10852.57 Kb ZIP silverbox-cd.zip
. 245 19 POWER REDUCTION MODES . 250 19.2 POWER DOWN MODE. 251 19.2.1 Protected Power Down Mode. 251 19.3 INTERRUPTIBLE POWER DOWN MODE operating modes - such as system reset, power reduction modes, interrupt handling, and system
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/7317.htm
STMicroelectronics 20/10/2000 740.4 Kb HTM 7317.htm
remains unchanged during and after a reset as long as the power supply is not turned off. The XRAM content is also maintained when the C500 microcontrollers are in power saving modes. 1.2.2.1 Internal addressable bits is located at byte addresses 20H - 2FH of the lower data RAM. Bit 0 of the internal data byte area typically provides 128 bytes of direct addressable SFRs. The SFRs which are located at addresses , complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or
/datasheets/files/infineon/mc_data/dave/products/c508.dip
Infineon 01/02/2000 5502.86 Kb DIP c508.dip
module Two 8-bit PWM Two 32-bit counters and capture registers n Low power controller Real time interface (ASC) Low power controller Teletext interface PROGRAMMABLE TRANSPORT IC FOR DVB APPLICATIONS . 82 12 Clocks and low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.2 Low power control . 83 12.3 Low power configuration registers
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/4556.htm
STMicroelectronics 20/10/2000 332.28 Kb HTM 4556.htm