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"chip level"

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Abstract: finish filtering 2 samples per chip 2 samples per chip 2 samples per chip 1 Channel with , Channels 1 Channel with FPGA for serial to parallel conversion 2 samples per chip 2 samples per chip 4 Channels 2 samples per chip 2 Channels with FPGA for serial to parallel conversion 1 sample per chip 100 2 samples per chip 2 Channels 2 Channels 2 Channels 4 samples per chip 4 samples per chip Digital AGC Digital AGC 4 Channels 4 Channels 4 samples Analog Devices
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AD6620 AD6624 AD6624A AD6634 AD6635 AD6636 AD9957 AD6652 AD6633 CDMA2000
Abstract: controlling the noise level and preventing howling with howling detector, double talk detector, attenuation function, and a gain control function. The devise also controls the low level noise with a center clipping function. Further, the MSM7602 I/O interface supports m-law PCM . The use of a single chip CODEC, such as , time: MSM7602-001 . For a single chip: 23 ms (max.) MSM7602-011 . For a cascade connection (can also be used for a single chip) Master chip: 23 ms (max.) Slave chip: 31 OKI Electric Industry
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echo ic digital echo 28pin echo IC 3.3 echo amplifier IC 28pin Digital Echo delay 16 Pin ICs DIGITAL ECHO IC E2U0037-28-82 MSM7520 MSM7566/7704 MSM7543/7533 SSOP28-P-485-0 QFP56-P-910-0
Abstract: noise level and preventing howling with howling detector, double talk detector, attenuation function, and a gain control function. The devise also controls the low level noise with a center clipping function. Further, the MSM7602 I / O interface supports |i-law P C M . The use of a single chip CODEC, such , time: M SM 7602-001.For a single chip: 23 ms (max.) M SM 7602-011.For a cascade connection (can also be used for a single chip) M aster chip: 23 ms (max.) Slave chip: 31 -
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U0037-28-82 SM7602 65-2K
Abstract: Liquid Crystal Display Controllers as Chip for COG and TCP packages for driving medium-size, 4-level , : +44-1628 585160 Key Features · · · · · · Driving of 4-level Grey Scale Displays Single chip control 8 , Crystal Display Controllers as Chip for COG and TCP packages for driving Colour STN Displays in Mobile , Display Modes Single chip control and Dual chip control 8-/16-bit parallel bus or high speed SCI or IIC , chip Design study only Single chip Dual chip Dual chip Dual chip Resolution 104x80 128x80 128x136 Hitachi
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HD66760 HD66762 HD66765 HD66752 HD66753 128x80 Display Controllers 128x128 HD6676 HD66761 HD66763 HD66764
Abstract: 750mW/ 133 3 Level/ Channel 8V 16 Resistive/ 14V On Chip 1/Channel On Chip 32 , Level/ Channel 8V 16 Resistive/ 14V On Chip 1/Channel On Chip 32 8 to ±25% 13.3 of Delay 15 to 26 64 Ld TQFP VENUS3 2 Pre1W/ 400 3 Level/ Production Channel 8V 16 Resistive/ 14V On Chip 1/Channel On Chip 32 6.4 to ±12.5% 12.8 of Delay 12 to 25 64 Ld TQFP VENUS4 2 Engineering 600mW/ 400 3 Level/ Sample Channel 8V 16 Intersil
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EL7155 EL7156 EL7158 ISL55100A ISL55100B ISL55110 VENUS3 pluto2 neptune ATE VENUS TQFP 132 PACKAGE SATURN 2 1-888-INTERSIL
Abstract: addition, a quality conversation is made possible by controlling the level and preventing howling with a , controlling the silence level with a center clipping function. The MSM7620 I/O interface supports n-law PCM. The use of a single chip CODEC, such as the MSM7543, allows the configuration an economic and , echoes. â'¢ Cancellable echo delay time: MSM7620-001 .For a single chip: 27 ms (max.) MSM7620-011 .For a cascade connection (can also be used for a single chip) Master chip -
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ECHO canceller IC sft 43 MSM7602-001GS-K MSM7620-001GS-K MSM7620-011GS-BK
Abstract: side, such a process is not a batch process at wafer level, dispensing has to be done chip by chip , Wafer Level CSP with Solder Support Structure Jörg Jasper EM-Marin S.A., Rue des Sors 3, CH , , Germany Abstract Chip scale package (CSP) and flip chip interconnects proliferate in telecommunication and other portable products. Wafer level CSP (WCSP) can provide a package that meets the cost requirements in this rapidly growing market. For such a package, all processing is performed at wafer level EM Microelectronic-Marin
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CH-2074 dycostrate without underfill D-13355
Abstract: Input Chip select Chip is enabled when CS is at "I" level. Set CS to"H" level before executing , selected when ORG is "L" level. RDY/BÃSY Output Status output "L" level is output during program or chip erase operation. "H" level Is output when program or chip erase operation is completed. VCC Power , input, CS can be set to "H" level ever while the internal rewriting process is operating. (3) Chip , address. After Chip Erase instruction is input, CS can be set to "H" level even while the internal -
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TC89102P tc89101p tc89101 71845 TC89102 TC89101/89102 TC89101P
Abstract: program or chip erase operation. "H â' level is output w hen program or chip erase operation is , can be set to "H" level ever while the internal rewriting process is operating. (3) Chip Erase , . After Chip Erase instruction is input, CS can be set to "H" level even while the internal erasing , signal from DO. "L" level is output during Program or Chip Erase operation. "H" level is output when , supply ♦ Program and Chip Erase ♦ User Selectable Organization 8-bitor 16-bit Chip select -
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Abstract: FUNCTION PIN NAME Input/Output FUNCTIONS CS Input Chip select Chip is enabled when CS is at "L" level , "L" level is output during Program or Chip Erase operation. "H" level is output when Program or Chip , Program or Chip Erase operation. "H" level is output when Program or Chip Erase operation is completed , ™¦ Erase/Write Disable for low power supply ♦ Program and Chip Erase ♦ User selectable , ¡ -»- RDY/BÃSY DI -Â»â  C 3 6 â¡ ORG DO -[I 4 5 â¡ â *- GND BLOCK DIAGRAM Chip select CS Clock -
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TCS9101 roy todd ma 8910
Abstract: FREQUENCY DOUBLER CHIP, 1.3 - 4.0 GHz INPUT Isolation @ +15 dBm Drive Level* Conversion Gain vs. Drive Level CONVERSION GAIN (dB) 2 FREQUency MULTIPLIERS - Passive - CHIP 2-2 *With respect to , HMC158 v06.0711 GaAs MMIC PASSIVE FREQUENCY DOUBLER CHIP, 1.3 - 4.0 GHz INPUT Features Conversion Loss: 15 dB Fo, 3Fo, 4Fo Isolation: 40 dB Input Drive Level: 10 to 20 dBm Die Size: 1.0 x 1.15 x 0.18 mm 2 FREQUency MULTIPLIERS - Passive - CHIP Typical Applications The HMC158 is suitable Hittite Microwave
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Abstract: DOUBLER CHIP, 1.3 - 4.0 GHz INPUT Conversion Gain vs. Drive Level Isolation @ +15 dBm Drive Level* CONVERSION GAIN (dB) 2 FREQUENCY MULTIPLIERS - PASSIVE - CHIP 2-2 *With respect to input level , HMC158 v05.0810 GaAs MMIC PASSIVE FREQUENCY DOUBLER CHIP, 1.3 - 4.0 GHz INPUT Typical Applications Features Conversion Loss: 15 dB Fo, 3Fo, 4Fo Isolation: 40 dB Input Drive Level: 10 to 20 dBm Die Size: 1.0 x 1.15 x 0.1 mm 2 FREQUENCY MULTIPLIERS - PASSIVE - CHIP The HMC158 is suitable Hittite Microwave
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Abstract: INTEGRATED CIRCUITS PCA9504A Glue chip 4 Product data Supersedes data of 2000 Aug 16 Philips Semiconductors 2002 Mar 28 Philips Semiconductors Product data Glue chip 4 , , buffering signals, and switching between power wells. The PCA9504A Glue Chip 4 integrates miscellaneous motherboard logic and analog functions into a single, small footprint 56-pin TSSOP device. The Glue Chip 4 , FLUSH_OUT_FWH SECONDARY_HD 27 30 LATCHED_BACKFED_CUT BACKFEED_CUT 28 The PCA9504A Glue Chip 4 is a Philips Semiconductors
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82801BA INTEL 845 MOTHERBOARD CIRCUIT diagram PC 845 MOTHERBOARD CIRCUIT diagram JESD78 JESD22-A114 intel 845 MOTHERBOARD CIRCUIT
Abstract: Applications FREQUENCY MULTIPLIERS - PASSIVE - CHIP 2 Features The HMC158 is suitable for , Point-to-Point Radios Input Drive Level: 10 to 20 dBm · UNII & HiperLAN Die Size: 1.0 x 1.15 x 0.1 mm , with respect to input signal level. The doubler uses the same diode/balun technology used in Hittite , , As a Function of Drive Level Input = +10 dBm Parameter Min. Typ. Frequency Range, Input , level) 45 dB 3FO Isolation (with respect to input level) 40 50 dB 4FO Isolation Hittite Microwave
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Frequency Doubler use diode frequency doubler balun mmic A
Abstract: possible by controlling the level and preventing howling with a howling detector, double talk detector, attenuation function and a gain control function, and by controlling the low level noise w ith a center clipping function. The M SM7620 I / O interface supports |i-law PCM. The use of a single chip CODEC, such , echoes. · Cancelable echo delay time: M SM 7620-001. For a single chip: 23 ms (max.) M SM 7620-011. For a cascade connection (can also be used for a single chip) M aster -
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echo delay st ic E2U0038-28-81 SM7543 QFP64-P-1414-0 80-BK
Abstract: HMC158 v06.0711 GaAs MMIC PASSIVE FREQUENCY DOUBLER CHIP, 1.3 - 4.0 GHz INPUT Typical Applications FREQUENCY MULTIPLIERS - PASSIVE - CHIP 2 Features The HMC158 is suitable for , Point-to-Point Radios Input Drive Level: 10 to 20 dBm â'¢ UNII & HiperLAN Die Size: 1.0 x 1.15 x 0.18 mm , with respect to input signal level. The doubler uses the same diode/balun technology used in Hittite , , As a Function of Drive Level Input = +10 dBm Parameter Min. Typ. Input = +15 dBm Max Hittite Microwave
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Abstract: , attenuator function, and gain control functions, and by suppressing low level noise with a center clipper function. The I/O interface of the ML50000 supports m-law PCM. Use of a single chip codec such as the , The gain control function (GC) becomes effective at the level of ­10 dBm0. · Cancellable echo delay time: ML50000-001 . For a single chip: 21 ms (max.) ML50000-011 . For a cascade connection (can also be used for a single chip) Master chip: 21 ms (max.) Slave OKI Electric Industry
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MSM7704 E2U0066-28-92
Abstract: DESCRIPTION Divider Ratio & /INH Pin Function Chip Surface Treatment Duty Level , . The series is also available in chip form. APPLICATIONS FEATURES Oscillation Frequency , fundamental only) : 3-State : 3.3V±10%, 5.0V±10% : Stand-by function included Selectable from Chip Enable , Capacitors Cg, Cd Packages : SOT-26, Chip Form (1.3x0.8mm) PIN CONFIGURATION PIN ASSIGNMENT PIN , FUNCTION /INH Q0 "H" or OPEN Clock Output "L" H = High level L = Low level High impedance Torex Semiconductor
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XC2164 MARKING SO SOT26 XC21 ETR1414 XC2164A XC2164K 125MH
Abstract: is "L" level. RDY/BUSY Output Status output "L" level is output during program or chip erase operation. "H" level is output when program or chip erase operation is completed. VCC Power supply + 5V , at all address. After Chip Erase instruction is input, CS can be set to "H" level even while the , RDY/BUSY status signal from DO. "L" level is output during Program or Chip Erase operation. "H" level , power supply ♦ Program and Chip Erase ♦ User Selectable Organization 8-bit or 16-bit BLOCK -
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Abstract: functions, and by suppressing low level noise with a center clipper function. The I/O interface of the ML50000 supports m-law PCM. Use of a single chip codec such as the MSM7704 (3V) or the MSM7533 (5V , ) becomes effective at the level of ­10 dBm0. · Cancellable echo delay time: ML50000-001 . For a single chip: 21 ms (max.) ML50000-011 . For a cascade connection (can also be used for a single chip) Master chip: 21 ms (max.) Slave chip: 31 ms (max OKI Electric Industry
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bidirectional clipper
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