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"chip level"

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Abstract: finish filtering 2 samples per chip 2 samples per chip 2 samples per chip 1 Channel with , Channels 1 Channel with FPGA for serial to parallel conversion 2 samples per chip 2 samples per chip 4 Channels 2 samples per chip 2 Channels with FPGA for serial to parallel conversion 1 sample per chip 100 2 samples per chip 2 Channels 2 Channels 2 Channels 4 samples per chip 4 samples per chip Digital AGC Digital AGC 4 Channels 4 Channels 4 samples ... Analog Devices
Original
datasheet

2 pages,
17.6 Kb

AD6620 AD6622 AD6623 AD6624 AD6624A AD6633 AD6634 AD6635 AD6636 AD6652 AD9957 TEXT
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Abstract: controlling the noise level and preventing howling with howling detector, double talk detector, attenuation function, and a gain control function. The devise also controls the low level noise with a center clipping function. Further, the MSM7602 MSM7602 I/O interface supports m-law PCM . The use of a single chip CODEC, such as , time: MSM7602-001 MSM7602-001 . For a single chip: 23 ms (max.) MSM7602-011 MSM7602-011 . For a cascade connection (can also be used for a single chip) Master chip: 23 ms (max.) Slave chip: 31 ... OKI Electric Industry
Original
datasheet

29 pages,
232.14 Kb

MSM7602-011 MSM7602-001GS-K MSM7602-001 MSM7602 DIGITAL ECHO IC Digital Echo delay 16 Pin ICs echo amplifier IC 28pin 28pin echo IC 3.3 digital echo echo ic E2U0037-28-82 TEXT
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Abstract: noise level and preventing howling with howling detector, double talk detector, attenuation function, and a gain control function. The devise also controls the low level noise with a center clipping function. Further, the MSM7602 MSM7602 I / O interface supports |i-law P C M . The use of a single chip CODEC, such , time: M SM 7602-001.For a single chip: 23 ms (max.) M SM 7602-011.For a cascade connection (can also be used for a single chip) M aster chip: 23 ms (max.) Slave chip: 31 ... OCR Scan
datasheet

29 pages,
502.19 Kb

U0037-28-82 MSM7602 TEXT
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Abstract: Liquid Crystal Display Controllers as Chip for COG and TCP packages for driving medium-size, 4-level , : +44-1628 585160 Key Features · · · · · · Driving of 4-level Grey Scale Displays Single chip control 8 , Crystal Display Controllers as Chip for COG and TCP packages for driving Colour STN Displays in Mobile , Display Modes Single chip control and Dual chip control 8-/16-bit parallel bus or high speed SCI or IIC , chip Design study only Single chip Dual chip Dual chip Dual chip Resolution 104x80 128x80 128x136 ... Hitachi
Original
datasheet

2 pages,
851.04 Kb

Hitachi DSAUTAZ006 HD66765 HD66762 HD66752 HD66760 HD66753 128x128 Display Controllers 128x80 TEXT
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Abstract: 750mW/ 133 3 Level/ Channel 8V 16 Resistive/ 14V On Chip 1/Channel On Chip 32 , Level/ Channel 8V 16 Resistive/ 14V On Chip 1/Channel On Chip 32 8 to ±25% 13.3 of Delay 15 to 26 64 Ld TQFP VENUS3 2 Pre1W/ 400 3 Level/ Production Channel 8V 16 Resistive/ 14V On Chip 1/Channel On Chip 32 6.4 to ±12.5% 12.8 of Delay 12 to 25 64 Ld TQFP VENUS4 2 Engineering 600mW/ 400 3 Level/ Sample Channel 8V 16 ... Intersil
Original
datasheet

4 pages,
38.78 Kb

ate dps EL7154 EL7155 EL7156 EL7158 ISL55100A ISL55100B ISL55110 ISL55111 JUPITER PMU SATURN 2 TQFP 132 PACKAGE VENUS neptune ATE pluto2 VENUS3 TEXT
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Abstract: addition, a quality conversation is made possible by controlling the level and preventing howling with a , controlling the silence level with a center clipping function. The MSM7620 MSM7620 I/O interface supports n-law PCM. The use of a single chip CODEC, such as the MSM7543 MSM7543, allows the configuration an economic and , echoes. • Cancellable echo delay time: MSM7620-001 MSM7620-001 .For a single chip: 27 ms (max.) MSM7620-011 MSM7620-011 .For a cascade connection (can also be used for a single chip) Master chip ... OCR Scan
datasheet

27 pages,
561.97 Kb

MSM7620-011GS-BK MSM7620-001GS-K MSM7620 MSM7602-001GS-K MSM7543 sft 43 ECHO canceller IC MSM7520 TEXT
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Abstract: side, such a process is not a batch process at wafer level, dispensing has to be done chip by chip , Wafer Level CSP with Solder Support Structure Jörg Jasper EM-Marin S.A., Rue des Sors 3, CH , , Germany Abstract Chip scale package (CSP) and flip chip interconnects proliferate in telecommunication and other portable products. Wafer level CSP (WCSP) can provide a package that meets the cost requirements in this rapidly growing market. For such a package, all processing is performed at wafer level ... EM Microelectronic-Marin
Original
datasheet

4 pages,
150.56 Kb

without underfill CH-2074 dycostrate D-13355 TEXT
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Abstract: Input Chip select Chip is enabled when CS is at "I" level. Set CS to"H" level before executing , selected when ORG is "L" level. RDY/BÜSY Output Status output "L" level is output during program or chip erase operation. "H" level Is output when program or chip erase operation is completed. VCC Power , input, CS can be set to "H" level ever while the internal rewriting process is operating. (3) Chip , address. After Chip Erase instruction is input, CS can be set to "H" level even while the internal ... OCR Scan
datasheet

11 pages,
371.36 Kb

TC89102P TC89102 71845 tc89101 tc89101p TC89101/89102 TC89101P TEXT
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Abstract: program or chip erase operation. "H ” level is output w hen program or chip erase operation is , can be set to "H" level ever while the internal rewriting process is operating. (3) Chip Erase , . After Chip Erase instruction is input, CS can be set to "H" level even while the internal erasing , signal from DO. "L" level is output during Program or Chip Erase operation. "H" level is output when , supply ♦ Program and Chip Erase ♦ User Selectable Organization 8-bitor 16-bit Chip select ... OCR Scan
datasheet

11 pages,
147.9 Kb

TC89101/89102 TC89101P TC89102P TEXT
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Abstract: FUNCTION PIN NAME Input/Output FUNCTIONS CS Input Chip select Chip is enabled when CS is at "L" level , "L" level is output during Program or Chip Erase operation. "H" level is output when Program or Chip , Program or Chip Erase operation. "H" level is output when Program or Chip Erase operation is completed , ™¦ Erase/Write Disable for low power supply ♦ Program and Chip Erase ♦ User selectable , –¡ -»- RDY/BÜSY DI -»■ C 3 6 □ ORG DO -[I 4 5 □ ■*- GND BLOCK DIAGRAM Chip select CS Clock ... OCR Scan
datasheet

10 pages,
171.75 Kb

TC89102P ma 8910 TC89101P tc89101 TC89102 roy todd TCS9101 TC89101/89102 TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
at the chip level (i.e., they will not appear in the main module port declaration). Instead, they
/datasheets/files/xilinx/weblinx/techdocs/646-v1.htm
Xilinx 23/09/1996 2.24 Kb HTM 646-v1.htm
Xilinx Answer #646 : XACT 5.2.0: How to drive GSR, GR, and GTS in a Verilog simulation using ES-Verilog? GSR, GR, and GTS are defined as global wires at the bottom of the .v Verilog source file generated by XNF2Verilog or XNF2CDS for a design in a module called _globals. These signals are buried and not hooked up at the chip level (i.e., they will not appear in the main module port declaration). Instead, they are declared as wires in a separate global
/datasheets/files/xilinx/docs/wcd0004a/wcd04a13.htm
Xilinx 16/02/1999 6.18 Kb HTM wcd04a13.htm
Developer Site Standard Template Version 2.1 (Replace with your Title) Key Tronic USB Keyboard Opens the Door to New Functionality and Features Key Tronic Corporation has announced the first Universal Serial Bus(USB) computer keyboard. A member of the Key Tronic KT-2000 KT-2000 product family, the new keyboard integrates the Intel 8x930Ax USB peripheral controller. "We have used a variety of Intel USB development tools on the board and chip level," says Key Tronic
/datasheets/files/intel/design/news/usb0227-v1.htm
Intel 31/01/1999 3.8 Kb HTM usb0227-v1.htm
problems with logic, physical pin connections, or programming. Chip check - examines a special class of checks for signals, components, or both at the chip level, such as placement rules with respect to one side of the device, etc. All checks - performs net, block, and chip checks. When you , block, and chip checks. In EPIC, you can run the net check on selected objects or on all of the
/datasheets/files/xilinx/docs/wcd0003e/wcd03ea1.htm
Xilinx 16/02/1999 2.63 Kb HTM wcd03ea1.htm
electrically at the block or chip level and programmed in-system on a byte-by-byte basis using only a single memory and a 1Mbit of SRAM. The deviced is offered in the new Chip Scale Package solutions: LBGA48 LBGA48 1.0mm are distinguishable by the use of the three chip enable lines: EF for the Flash memory, E1S and E2S
/datasheets/files/stmicroelectronics/stonline/press/magazine/prodnews/3rdedi99/pnews10.htm
STMicroelectronics 12/11/1999 4.85 Kb HTM pnews10.htm
>_globals. These signals are buried and not hooked up at the chip level (i.e., they will not appear in the
/datasheets/files/xilinx/weblinx/techdocs/646.htm
Xilinx 23/04/1997 2.13 Kb HTM 646.htm
Developer Site Standard Template Version 2.1 (Replace with your Title) Key Tronic USB Keyboard Opens the Door to New Functionality and Features Key Tronic Corporation has announced the first Universal Serial Bus(USB) computer keyboard. A member of the Key Tronic KT-2000 KT-2000 product family, the new keyboard integrates the Intel 8x930Ax USB peripheral controller. "We have used a variety of Intel USB development tools on the board and chip level," says Key Tronic
/datasheets/files/intel/design/news/usb0227.htm
Intel 31/07/1998 3.82 Kb HTM usb0227.htm
protection at the chip level," Binneboese said, "we can help maximize content quality and security, allowing
/datasheets/files/motorola/design-n/home2/press/html/pr960604.htm
Motorola 25/11/1996 3.14 Kb HTM pr960604.htm
Developer Site Standard Template Version 2.1 (Replace with your Title) Key Tronic USB Keyboard Opens the Door to New Functionality and Features Key Tronic Corporation has announced the first Universal Serial Bus(USB) computer keyboard. A member of the Key Tronic KT-2000 KT-2000 product family, the new keyboard integrates the Intel 8x930Ax USB peripheral controller. "We have used a variety of Intel USB development tools on the board and chip level," says Key Tronic
/datasheets/files/intel/products one/design/news/usb0227.htm
Intel 30/04/1999 3.8 Kb HTM usb0227.htm
"We have used a variety of Intel USB development tools on the board and chip level," says Key Tronic
/datasheets/files/intel/design/usb/keytron.htm
Intel 03/08/1997 8.85 Kb HTM keytron.htm