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"bus steering logic"

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Abstract: DMA Steering Logic modules. · Connects directly to the ISA bus · Supports 8 bit ISA bus , DMA request channel 4; an unused The ISA Bus DMA Steering Logic Module is designed so that , all 15 channels supported DMA Steering Logic Module · Implements all 7 DMA channels Serial EEPROM , to their counterparts on the ISA bus. The Programmable I/O Select Logic Module enables the Plug and , to the output pad, becoming the BRD_SEL line. The DMA Steering Logic module allows the system to ... Xilinx
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datasheet

18 pages,
175.48 Kb

XC4000 93C46 COMPM8 TEXT
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Abstract: - TRANSMIT DATA . REGISTER N DIGITAL ALGORITHM AND CODE CONVERTER CONTROL LOGIC STEERING LOGIC 18 (26 , DATA BUS —\ BUFFER \f—l/ INTERRUPT LOGIC I/O CONTROL 14(19) 15(201 17122) NOTE: NUMBERS NEXT , ) Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair , period (tGTp), Vc reaches the threshold (VTSl) of the steering logic to register the tone pair, latching , to the 4-bit bi-directional data bus when the Receive Data Register is read. The steering circuit ... OCR Scan
datasheet

3 pages,
248.84 Kb

SC11280EV SC11280EN SC11280CV SC11280CN SC11280 circuit diagram of dtmf generator Call Progress Tone generator 20-PIN steering TEXT
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Abstract: : 64-Bit Only Devices Add Internal Data Steering Logic for 32/64-Bit Systems To enable these , QWORD (lm_dxfrn is asserted). This process is shown in Figure 2. Add Internal Data Steering Logic for , , these functions provide the option of enabling data steering logic on l_dato[63.32] and l_beno[7.4]. , enables into the low and high DWORD storage areas, respectively. To enable the data steering logic, turn on the Add Internal Data Steering Logic for 32/66-Bit Systems option. 1 The data steering logic ... Altera
Original
datasheet

6 pages,
164.76 Kb

MT64 64-BIT PCI/MT64 PCI/T64 TEXT
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Abstract: EPS Electric Power Steering Table of Contents CAN BUS, ESD Protection. 3 CAN BUS, ISO9141 ISO9141 Bus Transceiver. 4 CAN BUS, K-Line Bus Controller , Power Steering : CAN BUS, ISO9141 ISO9141 Bus Transceiver Integred Circuit Product Name Status , SMD SO-8 SMD SO-8 page 4 EPS Electric Power Steering : CAN BUS, K-Line Bus Controller ... Vishay Intertechnology
Original
datasheet

22 pages,
57.31 Kb

ISO9141 TEXT
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Abstract: necessary steering logic for the master and slave read data buses. Write Data Path Unit · Each PLB arbiter write data path unit contains the necessary steering logic for the master and slave write data , . The PLB crossbar switch control unit manages request steering from PLB masters to the appropriate , . Each PLB arbiter consists of a bus arbitration control unit which manages the address and data flow through its PLB segment. Each bus arbitration control unit supports arbitration for twelve PLB masters ... IBM
Original
datasheet

2 pages,
24.15 Kb

PLB4ARB12M2W C27E505 TEXT
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Abstract: Unit · Each PLB arbiter read data path unit contains the necessary steering logic for the master and , necessary steering logic for the master and slave write data buses. Parity Support · Optional parity and , request steering from PLB masters to the appropriate PLB arbiter based on the address presented by each master and contains device control registers. Each PLB arbiter consists of a bus arbitration control unit which manages the address and data flow through its PLB segment. Each bus arbitration control ... IBM
Original
datasheet

2 pages,
24.42 Kb

Crossbar TEXT
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Abstract: D2 D3 Interrupt Logic IRQ/CP Digital Algorithm and Code Converter Steering Logic , Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair , validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair , microprocessor bus is provided and is directly compatible with 6800 series microprocessors. Credit card , Logic Bias Circuit VDD VRef VSS Transmit Data Register Status Register Control Logic ... Original
datasheet

18 pages,
96.18 Kb

cts knights cts knights radio DTMF decoder DTMF decoder with decoded outputs MP036S MT8870 mt8870 example code MT8880 DTMF RECEIVER MT8880C MT8880CE MT8880CN MT8880CP MT8880CS pin diagram explanation of mt8870 MT8870 dtmf decoder TQC-203-A-9S TEXT
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Abstract: logic timing diagrams. Input Signal Processing Stereo inputs L and R are fed to both the Steering , Surround Steering No Surround Channel Delay Required Built-In White Noise Generator 48-Lead SSOP (RS , GND INPUTS OUTPUTS LEFT LEFT RIGHT ANALOG SIGNAL PROCESSING RIGHT STEERING MATRIX , LOGIC AND NOISE GENERATOR RESET The SSM2005 SSM2005 is available from Analog Devices, subject to the License and Royalty requirements as described on the following page of the data sheet. STEERING CONTROL ... Analog Devices
Original
datasheet

15 pages,
126.34 Kb

simple surround circuit diagram surround amplifier 5.1 surround sound circuits block diagram of 5.1 surround sound car subwoofer amplifier circuit 5.1 subwoofer printed circuit boards simple surround speaker circuit diagram simple subwoofer circuit diagram subwoofer crossover schematic low pass subwoofer circuit diagram subwoofer amplifier circuit diagram 5.1 surround sound diagrams subwoofer preamplifier circuit 5.1 surround sound amplifier circuits TEXT
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Abstract: status register steering logic control register a control register receive □ata register Ü data bus buffer interrupt logic I/O control cc ref "ss StGT - 9] do -]d1 - ] d2 ■ h d3 . , Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair , the steering logic to register the tone pair, latching its 10 This Material Copyrighted By Its , presented to the four bit bi-directional data bus when the Receive Data Register is read. The steering ... OCR Scan
datasheet

18 pages,
704.71 Kb

SC11280 SC112 Call Progress Tone generator block diagram for simple IR transmitter SC11280CN SC11270 TEXT
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Abstract: steering logic for the master and slave read data buses. Write Data Path Unit · The PLB arbiter write data path unit contains the necessary steering logic for the master and slave write data buses , highly integrated Core+ASIC systems Highlights The processor local bus is a high performance on-chip bus used in highly integrated Core+ASIC systems. The PLB supports read and write data transfers between master and slave devices equipped with a PLB bus interface and connected through PLB signals ... IBM
Original
datasheet

2 pages,
22.95 Kb

PLB4ARB8M Non-Pipelined processor C27E503 TEXT
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