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"alu 4 bit"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 16-bit, 32 instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g , B CO MSB B MUX IA0-4 ALU S MUX CEB MSS 5 BARREL SHIFTER CI SHIFT , from the ALU is loaded into an internal 1 bit register, so that it is available as an input to the ALU , condition or a zero result. For the overflow condition to be 4 active the ALU result must have Zarlink Semiconductor
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PDSP1601 PDSP1601A 4 bit barrel shifter circuit diagram 4 bit barrel shifter 8 bit barrel shifter 4 bit barrel shift register datasheet barrel shifter 16 BIT ALU design with data sheet PDSP1601/PDSP1601A DS3705
Abstract: 64_62161_591 4* T- tt3 KSRC 3-bit value which exercises the /, and l0 source controls of the ALU A & B , '¢ Flexible Host and DMA Interfaces â'¢ Supports Single/Double Precision FPU â'¢ 2901 ALU Superset â'¢ 32-Bit ALU or 2 16-Bit ALUs â'¢ 2910 Sequencer Superset â'¢ 2Kb Data Cache â'¢ 3-Address Generators â , superset of the AMD 2901 as shown in Figures 2,3,4. Instructions to the ALU are supplied directly out of , cycle. Associated with the ALU is a 16 x 32-bit register file. The address lines lor the dual-ported -
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kbaa amd 2901 alu weitek FPU weitek WTL3164 Kaaa
Abstract: ARCHITECTURE 3.1.1 Data ALU Input Registers (X1, X0, Y1, Y0) X1, X0, Y1, and Y0 are 16-bit latches which , , B1 and B0 are 16-bit latches which serve as data ALU accumulator registers. A2 and B2 are 8-bit , data ALU operations specify the 40-bit accumulator registers as source and/or destination operands The accumulator registers are treated as two 40-bit registers A (A2:A1:A0) and B (B2:B1:B0) for data ALU , output and supply a source accumulator of the same form. Most data ALU operations specify the 40-bit Motorola
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8 bit booth multiplier block diagram 8 bit booth multiplier modified booth circuit diagram XX0100 011XXX 1110XX XX0101
Abstract: , 32 Instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g. 200ns 64-bit , 12E` D ' ?22GS13 0 0 1 0 0 4 5 t> Symbol MSB MSS Description ALU B-input multiplexer , into an internal 1 bit register, so that it is available as an input to the ALU on the next cycle. In , overflow condition to be active the ALU result must have overflowed into the 16th (sign) bit, (this flag Is -
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0D1G04 84-PIN 120-PIN AC120 7220S13 T-90-20
Abstract: 16-bit, 32 instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g , B CO MSB B MUX IA0-4 ALU S MUX CEB MSS 5 BARREL SHIFTER CI SHIFT , from the ALU is loaded into an internal 1 bit register, so that it is available as an input to the ALU , condition or a zero result. For the overflow condition to be 4 active the ALU result must have Zarlink Semiconductor
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AC84 GC100 PDSP16112 PDSP16116 PDSP16318
Abstract: 4 of 19 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA59032 32-Bit , microprocessor that combines the functions of eight 2901 4-bit slice processors and distributed look-ahead carry , SOURCE I(8:0) INSTRUCTION BUS 2 3 4 ALU FUNCTION 5 6 7 MICROINSTRUCTION , 32-BIT ALU F Cn A OEn OVR OUTPUT DATA MUX Cn32 F Y(31:0) IA211001108 , by 32-bit 2-port RAM and the high-speed ALU. Data in any of the 32 words of the RAM can be read InnovASIC Semiconductor
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WS59032 32X32 4 BIT ALU IC bit slice processors functional diagram of ALU using mux IA211001108-03 13X13 IA59032-CPGA100I
Abstract: 16-bit, 32 instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g , B CO MSB B MUX IA0-4 ALU S MUX CEB MSS 5 BARREL SHIFTER CI SHIFT , from the ALU is loaded into an internal 1 bit register, so that it is available as an input to the ALU , condition or a zero result. For the overflow condition to be 4 active the ALU result must have Zarlink Semiconductor
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bfp mark diode Shift register designed by Max Plus
Abstract: SN74AS8832 32'Bit Registered ALU â'¢ Compatible with AS888 architecture and instruction set â'¢ 3-port I/O architecture â'¢ Simultaneous ALU and register operations â'¢ 64-word by 36-bit , Description The 74AS8832 is a 32-bit registered ALU that can be configured to operate as four 8-bit ALUs, two 16-bit ALUs or a single 32-bit ALU. The processor's instruction set is 100 percent upwardly , U s -A-⺠Z,C,OVR,N BYOF3-BYOFO Figure 1. 32-Bit Registered ALU This Material Copyrighted By -
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ALU 8 bit register file 3 bit magnitude comparator AS8832 SIM74AS8832 DA/B31-DA/BO Y31-Y0 IESI03-IESIOO
Abstract: snnnnnnnnnnnnnnnnnnnnn^ 11 10 9 1 AC84 LC84 FEATURES 16-bit, 32 instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad , Symbol MSB MSS B 1 5 - BO Pin No. (LC84 Package) 2 3 4 - 19 20 21 Description ALU B-input multiplexer , CEB CLK MS AO - MSA1 2 3 - 2 4 A 1 5 -A O 2 5 -4 0 41 42 4 3 -4 6 4 7 -5 0 ALU A-input , is loaded into an internal 1 bit register, so that it is available as an input to the ALU on the next -
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GG 26 HB3923-1 1601/PDSP
Abstract: FEATURES s s s s s s s s 16-bit, 32 instruction 10MHz ALU 16-bit, 10MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers , MSB B MUX IA0-4 ALU S MUX CEB MSS 5 BARREL SHIFTER CI SHIFT CONTROL , bit register, so that it is available as an input to the ALU on the next cycle. In the manner , provide flags indicating that the ALU result is within a factor of two or four of overflowing the 16 bit Mitel Semiconductor
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barrel shifter block diagram 32 bit barrel shifter circuit diagram design of priority encoder 00FF DS3763
Abstract: 16-bit, 32 instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g , B CO MSB B MUX IA0-4 ALU S MUX CEB MSS 5 BARREL SHIFTER CI SHIFT , from the ALU is loaded into an internal 1 bit register, so that it is available as an input to the ALU , condition or a zero result. For the overflow condition to be 4 active the ALU result must have Zarlink Semiconductor
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32 bit barrel shifter 16 bit barrel shifter circuit diagram block diagram for barrel shifter block alu
Abstract: s s s s s s s s s 16-bit, 32 instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers , A B CO MSB B MUX IA0-4 ALU S MUX CEB MSS 5 BARREL SHIFTER CI , , the carry out from the ALU is loaded into an internal 1 bit register, so that it is available as an , overflow condition or a zero result. For the overflow condition to be 4 active the ALU result must Mitel Semiconductor
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barrel shifter circuit diagram 4 bit barrel shifter using mux multicycle barrel shifter
Abstract: bit registers and each supporting 8 instructions (see Table 4). The instructions for the ALU , instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g. 200ns 64-bit Accumulate , . CLK Description All registers are loaded, and outputs MSAO - MSA1 2 3 -2 4 ALU A-lnput , Carry In to LSB of ALU. IAO - IA3 IA4 81 -8 4 1 Instruction inputs to ALU.1 IA4 = MSB. These -
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MIL883
Abstract: 10MHz ALU 16-bit, 10MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 , AO - MSA1 41 -4 2 ALU A-input m ultiplexer select control.1 This input are latched internally on , bit register, so that it is available as an input to the ALU on the next cycle. In the manner, M , provide flags indicating that the ALU result is within a factor of two or four of overflowing the 16 bit , to be active the ALU result must have overflowed into the 16th (sign) bit, (this flag is only -
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100-LEAD
Abstract: FEATURES s s s s s s s s 16-bit, 32 instruction 10MHz ALU 16-bit, 10MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers , MSB B MUX IA0-4 ALU S MUX CEB MSS 5 BARREL SHIFTER CI SHIFT CONTROL , bit register, so that it is available as an input to the ALU on the next cycle. In the manner , provide flags indicating that the ALU result is within a factor of two or four of overflowing the 16 bit Zarlink Semiconductor
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18 x 16 barrel shifter design of 18 x 16 barrel shifter multiplexers 74 LS 150 IA04 4 bit barrel shift register 4 bit ALU
Abstract: instruction 10MHz ALU 16-bit, 10MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g. 200ns 64-bit Accumulate , B IA0-4 CI 5 BARREL SHIFTER SHIFT CONTROL IS0-3 SV0-3 SVOE RAD-2 3 3 ALU REG FILE LEFT , into an internal 1 bit register, so that it is available as an input to the ALU on the next cycle. In , overflow condition to be active the ALU result must have overflowed into the 16th (sign) bit, (this flag is Zarlink Semiconductor
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Diode SV03 81 Diode RA02 msa01 4*4 barrel shifter design
Abstract: widely used 4-bit 7400 family (74181, 251, 381) ALUs. FUNCTIONAL DESCRIPTION The IDT49C402A is a high-speed, fully cascadable 16-bit CMOS ALU slice with 64-by-16-bit register file. It combines the standard functions of four 2901s (4-bit ALU) and a 2902 (carry lookahead) with additional control features , the source operand select of the ALU (I0, I1, I2), a 3-bit instruction field used to control the 8 possible functions of the ALU (I3, I4, I5), and a 3-bit instruction field (I6, I7, I8) for selecting the Integrated Device Technology
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IDT74FCT374A 2901s 8 BIT ALU design by cmos 4 bit ALU USING VLSI 8 BIT ALU by 74181 alu 74181 functional diagram of ALU G/F15 32-BIT
Abstract: 16-bit, 32 instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g , B CO MSB B MUX IA0-4 ALU S MUX CEB MSS 5 BARREL SHIFTER CI SHIFT , from the ALU is loaded into an internal 1 bit register, so that it is available as an input to the ALU , condition or a zero result. For the overflow condition to be 4 active the ALU result must have Zarlink Semiconductor
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opal
Abstract: CO RAO RA1 RA2 Cl IA0 IA1 IA2 1A3 APPLICATIONS 16-bit, 32 Instruction 20M Hz ALU , Independent A LU and Shifter Operation G raphics 4 x 16-bit On C hip S cratchpad Registers D atabase , from thé ALU is loaded into an internal 1 bit register, so that it is available as an input to the , source of the new MSB (see ALU INSTRUCTION SET). When the most significant 16 bit byte is right shifted , the effect of: 1. 2. 3. 4. 5. Clearing ALU and Barrel Shifter register files to zero -
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PDSP1601A0 MIL-883C
Abstract: , 32 instruction 10MHz ALU 16-bit, 10MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g. 200ns 64-bit , A REG A MUX BFP MSA0-1 2 B REG A B CO MSB B MUX IA0-4 ALU S MUX , carry out from the ALU is loaded into an internal 1 bit register, so that it is available as an input , where in the 16 bit field by the Barrel Shifter, allowing the AND function of the ALU to perform Zarlink Semiconductor
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