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"Frame rate conversion"

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Abstract: deinterlacing. Other functions such as chroma resampling, color space conversion and frame rate conversion-all , Quartus (HDL) Frame Rate Conversion SOPC Builder R G MA Deinterlacer Clipper AFD Clipper , Space Converter Frame Buffer Scaler Cb Frame Rate Conversion R Test Pattern , buffer) Run-time controllable frame rate conversion Genlock Mixer present on one video processing , rate up to 1080p60 One DVI input-Interlaced or progressive, any resolution and frame rate up to ... Altera
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10 pages,
615.08 Kb

h.264 encoder hdmi rx giris Optix PCIe BT.656 PCIE SWITCH IDT Silicon Optix HDMI rx Gennum HDMI converter SDI sdi gennum HDMI Rx OSD scaler genesis video scaler Sigma Designs 1080p60 video encoder 1080p60 sdi to hdmi hdmi SDI HDMI to SDI converter chip TEXT
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Abstract: rising edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame , convert frame. The MSB from the previous conversion is latched out on the rising edge of FS. The rising edge of FS during an internal convert (see Figure 12) aborts the conversion and starts a new frame , convert frame. The MSB from the previous conversion is latched out on the falling edge of CS. This signal , of conversion. A new frame can be started with the end of conversion. 7 ADS7890 ADS7890 www.ti.com ... Texas Instruments
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25 pages,
343.1 Kb

ttl 365 hex 3 state buffer THS4211 THS4031 ADS7890IPFBT ADS7890IPFBR ADS7890 3F80 SLAS409 14BIT 25MSPS TEXT
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Abstract: . 7 Frame Rate Conversion , configured to operate on a different clock from the core. Simple frame rate conversion is employed to , , bob, intra and inter motion adaptive deinterlacing algorithms • Frame rate conversion â , pixel sample clock. The frame buffer module handles the rate conversion, and the line buffer and deinterlacing engine operate at the output pixel clock rate. When frame rate conversion is disabled, all the ... Lattice Semiconductor
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31 pages,
2272.36 Kb

IPUG97 TEXT
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Abstract: PRODUCT BRIEF FRAME RATE CONVERTER sxFC A 1 T he Silicon Optix high performance sxFC1A Frame Rate Converter is the ideal companion integrated circuit for the Silicon Optix sxZX1 Image Processor for applications requiring frame rate management. The Silicon Optix sxFC1A functions as a graphics and video frame buffer controller capable of performing frame rate conversion by replicating or dropping incoming data as necessary to maintain a set output frame rate. The Silicon Optix sxFC1A can be ... Silicon Optix
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2 pages,
607.5 Kb

Video Frame rate Converter sync to HSYNC and VSYNC converter "Frame rate conversion" sxfc1a gmFC1A Silicon Optix Optix TEXT
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Abstract: TIMING AND SYNCHRONIZATION PRODUCT CATALOG ZL30110 ZL30110 ZL30112 ZL30112 ZL30113 ZL30113 Rate Conversion PLLs , rates or standard Ethernet clock rates Multiple PLLs per device for rate conversion Line card , compliance Number of rate conversion Digital PLLs Maximum frequency (MHz) Number of SONET/SDH/ Ethernet , ) Package size RATE CONVERSION PLLs Zarlink’s telecom rate conversion phase locked loops (PLLs , failure ZL30110 ZL30110 Rate conversion DPLL with stand by capability ZL30112 ZL30112 ZL30113 ZL30113  Number of ... Zarlink Semiconductor
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8 pages,
354.63 Kb

ZL30110 ZL30112 TEXT
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Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and ... Texas Instruments
Original
datasheet

29 pages,
631.63 Kb

ADS7890 SLAS409 14BIT 25MSPS TEXT
datasheet frame
Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and ... Texas Instruments
Original
datasheet

28 pages,
499.39 Kb

ADS7890 SLAS409 14BIT 25MSPS TEXT
datasheet frame
Abstract: rising edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame , convert frame. The MSB from the previous conversion is latched out on the rising edge of FS. The rising edge of FS during an internal convert (see Figure 12) aborts the conversion and starts a new frame , convert frame. The MSB from the previous conversion is latched out on the falling edge of CS. This signal , of conversion. A new frame can be started with the end of conversion. 7 ADS7890 ADS7890 www.ti.com ... Texas Instruments
Original
datasheet

24 pages,
322.87 Kb

THS4211 THS4031 rf mems switch ADS7890IPFBT ADS7890IPFBR ADS7890 3F80 SLAS409 14BIT 25MSPS TEXT
datasheet frame
Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and ... Texas Instruments
Original
datasheet

29 pages,
1009.64 Kb

ADS7890 SLAS409 14BIT 25MSPS TEXT
datasheet frame
Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and ... Texas Instruments
Original
datasheet

28 pages,
499.65 Kb

ADS7890 SLAS409 14BIT 25MSPS TEXT
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