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Part Manufacturer Description PDF & SAMPLES
CS8420-DSR Cirrus Logic Converters - Sample Rate IC Digital Audio Sample Rate Convertr
CLP0212FPXX5Z01A GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power
CLP0224FPXXXZ03A GE Critical Power CLP0224 Open Frame Power Supply, 90 - 264Vac input; 24Vdc output; 200W Output Power, Conformal Coated
CLP0212FPEX5Z02A GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power
CLP0412FPXXXZ01A GE Critical Power CLP0412 Open Frame Power Supply, 90 - 265Vac Input; 12Vdc Output; 450W Output Power
CLP0212FPXX5Z03A GE Critical Power CLP0212 Open Frame Power Supply, 90 - 264Vac input; 12Vdc output; 200W Output Power

"Frame rate conversion"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: deinterlacing. Other functions such as chroma resampling, color space conversion and frame rate conversion-all , Quartus (HDL) Frame Rate Conversion SOPC Builder R G MA Deinterlacer Clipper AFD Clipper , Space Converter Frame Buffer Scaler Cb Frame Rate Conversion R Test Pattern , buffer) Run-time controllable frame rate conversion Genlock Mixer present on one video processing , rate up to 1080p60 One DVI input-Interlaced or progressive, any resolution and frame rate up to Altera
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HDMI to SDI converter chip hdmi SDI sdi to hdmi 1080p60 1080p60 video encoder Sigma Designs
Abstract: rising edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame , convert frame. The MSB from the previous conversion is latched out on the rising edge of FS. The rising edge of FS during an internal convert (see Figure 12) aborts the conversion and starts a new frame , convert frame. The MSB from the previous conversion is latched out on the falling edge of CS. This signal , of conversion. A new frame can be started with the end of conversion. 7 ADS7890 www.ti.com Texas Instruments
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3F80 ADS7890IPFBR ADS7890IPFBT THS4031 THS4211 ttl 365 hex 3 state buffer SLAS409 14BIT 25MSPS 25-MSPS
Abstract: . 7 Frame Rate Conversion , configured to operate on a different clock from the core. Simple frame rate conversion is employed to , , bob, intra and inter motion adaptive deinterlacing algorithms â'¢ Frame rate conversion â , pixel sample clock. The frame buffer module handles the rate conversion, and the line buffer and deinterlacing engine operate at the output pixel clock rate. When frame rate conversion is disabled, all the Lattice Semiconductor
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IPUG97 E2011 LFXP2-40E-7F484C
Abstract: PRODUCT BRIEF FRAME RATE CONVERTER sxFC A 1 T he Silicon Optix high performance sxFC1A Frame Rate Converter is the ideal companion integrated circuit for the Silicon Optix sxZX1 Image Processor for applications requiring frame rate management. The Silicon Optix sxFC1A functions as a graphics and video frame buffer controller capable of performing frame rate conversion by replicating or dropping incoming data as necessary to maintain a set output frame rate. The Silicon Optix sxFC1A can be Silicon Optix
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Optix Silicon Optix gmFC1A sxfc1a sync to HSYNC and VSYNC converter Video Frame rate Converter
Abstract: TIMING AND SYNCHRONIZATION PRODUCT CATALOG ZL30110 ZL30112 ZL30113 Rate Conversion PLLs , rates or standard Ethernet clock rates Multiple PLLs per device for rate conversion Line card , compliance Number of rate conversion Digital PLLs Maximum frequency (MHz) Number of SONET/SDH/ Ethernet , ) Package size RATE CONVERSION PLLs Zarlinkâ'™s telecom rate conversion phase locked loops (PLLs , failure ZL30110 Rate conversion DPLL with stand by capability ZL30112 ZL30113  Number of Zarlink Semiconductor
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ZL30106 GR-1244 ZL30131 ZL30132 ZL30145 ZL30146
Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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Abstract: rising edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame , convert frame. The MSB from the previous conversion is latched out on the rising edge of FS. The rising edge of FS during an internal convert (see Figure 12) aborts the conversion and starts a new frame , convert frame. The MSB from the previous conversion is latched out on the falling edge of CS. This signal , of conversion. A new frame can be started with the end of conversion. 7 ADS7890 www.ti.com Texas Instruments
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rf mems switch
Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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ISO/TS16949
Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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Abstract: edge of FS starts a new sample and convert frame. The MSB from the previous conversion is latched out , the conversion and starts a new frame. 42 CS I Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out , Figure 7) aborts the conversion and starts a new frame. 24, 34, 40 +VBD Digital power supply , progress and continues to be high until the end of conversion. A new frame can be started with the end of Texas Instruments
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Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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Abstract: Rate Conversion Line Card Synchronizer Output Synthesizers n Frame Pulse SONET , TIMING ND A SYNCHRONIZATION PRODUCT CATALOG ZL30110 ZL30112 ZL30113 Rate Conversion , rates or standard Ethernet clock rates Multiple PLLs per device for rate conversion Line card , x 10 mm TQFP Jitter compliance Number of rate conversion Digital PLLs Maximum frequency (MHz , output pins for lock indication & reference failure ZL30110 Rate conversion DPLL with stand by -
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ZL30108 ZL30321 ZL30136 ZL30143 TCXO 20 MHZ CABGA STM-64 GR-253 ZL30100 ZL30102
Abstract: rising edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame , convert frame. The MSB from the previous conversion is latched out on the rising edge of FS. The rising edge of FS during an internal convert (see Figure 12) aborts the conversion and starts a new frame , convert frame. The MSB from the previous conversion is latched out on the falling edge of CS. This signal , of conversion. A new frame can be started with the end of conversion. 7 ADS7890 www.ti.com Texas Instruments
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Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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Abstract: SAMPLING DYNAMICS Conversion time Acquisition time Maximum throughput rate Aperture delay Aperture jitter , edge to avoid conversion abort Delay time, 9th SCLK rising edge to FS rising edge for frame abort , Figure 12) aborts the conversion and starts a new frame. Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The MSB from the previous conversion is latched out on , 7) aborts the conversion and starts a new frame. Digital power supply for all digital inputs and Texas Instruments
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Abstract: A/D conversion. High Frame Rate and High Signalto-Noise Ratio Characteristics As the demand for , HD CMOS Image Sensor for Industrial Applications Achieves a High Frame Rate and a High S/N Ratio , high frame rate, high signal-to-noise ratio and full HD to Sony's CMOS image sensor lineup for , of this volume. â  High frame rate (120 frame/s) â  Supporting HD 1080p and HD 720p modes â , and the IMX136LLJ, that Sony are now releasing deliver 120 frame/s in 10-bit A/D conversion mode in Sony
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IMX136LQJ IMX122 sony HD image sensor IMX136LQJ/LLJ 38M-E IMX122LQJ IMX104LQJ 1944H
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