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"Error correction"

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Abstract: . 16 Figure 2.1.5.7 Receive _MAIN After 1st Horizontal Error Correction . 17 Figure 2.1.5.8 Reception After 2nd Horizontal Error Correction . 18 Figure , Figure 2.2.5.10 Reception After 2nd Horizontal Error Correction . 41 Figure , . 44 Figure 2.2.5.14 Receive _SUB After 1st Horizontal Error Correction . 45 , regenerated by error correction. Therefore, by watching for missing packets, simultaneous reception of the ... OKI Electric Industry
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53 pages,
334.26 Kb

MSM9562/63/66/67 TEXT
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Abstract: bje is not are su is tice:Th metric limits No para Some ERROR CORRECTION WITH VARIABLE , , Euclidean stage, Chen search & error value stage), so it realizes high speed error correction operation. Capable of erasure correcting function and it improves error correction performance. · Where error , is tice:Th metric limits No para Some M64403FP M64403FP ERROR CORRECTION WITH VARIABLE LENGTH AND , :Th metric limits No para Some M64403FP M64403FP ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE ... Mitsubishi
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17 pages,
83.1 Kb

M64403FP D181 Z65T BJE 61 aRm3 T22N TEXT
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Abstract: . 16 Figure 2.1.5.7 Receive _MAIN After 1st Horizontal Error Correction . 17 Figure 2.1.5.8 Reception After 2nd Horizontal Error Correction . 18 Figure , Figure 2.2.5.10 Reception After 2nd Horizontal Error Correction . 41 Figure , . 44 Figure 2.2.5.14 Receive _SUB After 1st Horizontal Error Correction . 45 , sub-station reception, missing main station packets can be regenerated by error correction. Therefore, by ... OKI Electric Industry
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56 pages,
372.37 Kb

VICS TUNER Si 2158 Tuner MSM9562/63/66/67 TEXT
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Abstract: SYNCHRONIZATION REGISTERS . 5-34 5.8 ERROR CORRECTION REGISTERS , consisting of an SCF, frame synchronization circuit, and error correction circuit on a single chip. They , frame memory enables automatic error correction. · Built-in bandpass filter (SCF) · Built-in block , Vref SG Filter Section PN Descrambler Receive RAM SÆP FRAME memory Error correction , / disconnection _SUB (R_04) Clock regeneration _SUB Receive RAM after first horizontal error correction ... OKI Electric Industry
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86 pages,
415.02 Kb

QFP44-P-910-0 MSM9562GA MSM9562 MSM9554 MSM9552 TEXT
datasheet frame
Abstract: SYNCHRONIZATION REGISTERS . 5-34 5.8 ERROR CORRECTION REGISTERS , consisting of an SCF, frame synchronization circuit, and error correction circuit on a single chip. They , frame memory enables automatic error correction. · Built-in bandpass filter (SCF) · Built-in block , first horizontal error correction _SUB Tuner Block synchronization _SUB (L1BF_SUB) Receive , automatically accumulate the received data after the first horizontal error correction in the frame memory ... OKI Electric Industry
Original
datasheet

86 pages,
415.07 Kb

QFP44-P-910-0 MSM9563GA MSM9555 MSM9553 MSM9563 TEXT
datasheet frame
Abstract: SYNCHRONIZATION REGISTERS . 5-34 5.8 ERROR CORRECTION REGISTERS , an SCF, frame synchronization circuit, and error correction circuit on a single chip. They allow a , frame memory enables automatic error correction. · Built-in bandpass filter (SCF) · Built-in block , _04) Clock regeneration _SUB Receive RAM after first horizontal error correction _SUB Tuner Block , RAM after first horizontal error correction _MAIN (L1BF) 5-2 Main station Frame memory ... OKI Electric Industry
Original
datasheet

85 pages,
412.04 Kb

QFP44-P-910-0 MSM9563GA MSM9563 MSM9555 MSM9553 TEXT
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Abstract: MITSUBISHI ICS (LSI) M64403FP M64403FP n -p a - so m aP ERROR CORRECTION WITH VARIABLE LENGTH AND , stage, Chen search & error value stage), so it realizes high speed error correction operation. 9 C apable of erasure correcting function and it im proves error correction performance. · W here error , -C MITSUBISHI ICS (LSI) M64403FP M64403FP n -p a - so m aP ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE BLOCK DIAGRAM MITSUBISHI ICS (LSI) p ftE A -V M64403FP M64403FP ERROR CORRECTION WITH VARIABLE LENGTH ... OCR Scan
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17 pages,
367.99 Kb

U22N T22N a2160 M64403FP TEXT
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Abstract: detection and single-burst error correction with ECC polynomial • Programmable correction span of 5,8 or , error detection and correction circuit used to insure data integrity between two serial ports. An , for error correction. The ECC polynomial has a maximum correction span of 11 bits in series and a , hardware correction, error syndrome appears during software correction; and error pattern appears during , end of the receive cycle means that the data read is in error. 16 EOC End of Correction This output ... OCR Scan
datasheet

13 pages,
505.25 Kb

TEXT
datasheet frame
Abstract: SYNCHRONIZATION REGISTERS . 5-34 5.8 ERROR CORRECTION REGISTERS , enables automatic error correction. · Built-in bandpass filter (SCF) · Built-in block synchronization , Section PN Descrambler SÆP Receive RAM FRAME memory Error correction Data processor , regeneration _SUB Receive RAM after first horizontal error correction _SUB Tuner Block , RAM after first horizontal error correction _MAIN (L1BF) 5-2 Main station Frame memory ... OKI Electric Industry
Original
datasheet

90 pages,
431.84 Kb

QFP44-P-910-0 PEUL9567-01 MSM9567 MSM9555 MSM9553 76khz filter TEXT
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Abstract: , 2006 Single Error Correction and Double Error Detection Author: Simon Tam Summary This application note describes the implementation of an Error Correction Control (ECC) module in a VirtexTM-II , . Introduction Error detection and correction is found in many high-reliability and performance applications , .2) August 9, 2006 www.xilinx.com 1 R Single Error Correction and Double Error Detection For , XAPP645 XAPP645 (v2.2) August 9, 2006 R Single Error Correction and Double Error Detection When there is ... Xilinx
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12 pages,
166.09 Kb

vhdl code for 6 bit parity generator vhdl code for transpose memory error correction code D49 transistor vhdl code for 32bit parity decoder hamming encoder decoder hamming code in vhdl block diagram code hamming XAPP645 vhdl code for a 9 bit parity generator 7 bit hamming code error correction code in vhdl vhdl code hamming vhdl code hamming ecc hamming code vhdl code for 8 bit parity generator verilog code hamming hamming code FPGA vhdl code for 9 bit parity generator TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
No abstract text available
/download/0000000-510130ZC/eeprom-boards-parallel-async.xls
Memory 21/03/1997 165 Kb XLS eeprom-boards-parallel-async.xls
operations. The device provides quad-pass error correction for CD-ROM applications (C1-C2-C1-C2) and operates in lock-to-disk, CAV, pseudo CLV and CLV modes. In DVD modes double-pass C1-C2 error correction is pre-amplifier, including analog front-end, PLL data recovery, demodulation and error correction. The spindle , DVD-ROM to n = 1.9, maximum rates (tbf) Matched filtering, quad-pass error correction (C1-C2-C1-C2 to 32 kbytes SRAM for DVD error correction and de-interleave Sub-code/ header processing for DVD
/datasheets/files/philips/pip/saa7335_2.html
Philips 14/02/2002 7.68 Kb HTML saa7335_2.html
requirements are much relaxed over silicon memory due to the inclusion of error correction in the hard disk through two bit/cell (and later three or four bit/cell) technology. The use of error correction, and the solid-state disk goal. The solid-state disk system would include error correction and would generate both the product and the process, allowing removal of the error correction requirement for two bit remove the two major requirements initially envisioned for M.L.C.: error correction and precision
/datasheets/files/intel/techno~1/itj/q41997/articles/art_1g-v2.htm
Intel 31/01/1998 12.37 Kb HTM art_1g-v2.htm
equation could be solved by radicals. FEC  Forward Error Correction,  a methodology that uses  error correction coding to transmission. This is the opposite of ARQ (automatic repeat request) which uses equations. Hamming Codes These are the first class of linear binary codes used for error correction in block responsible for appending extra bits to the digital data before transmitting. Error less than the channel capacity with an arbitrary small bit error rate. Symbol Width  This is the
/datasheets/files/xilinx/docs/rp0000a/rp00a90.htm
Xilinx 29/02/2000 7.82 Kb HTM rp00a90.htm
Digital Error Correction Most modern pipelined ADCs employ a technique called "digital error correction" to greatly reduce the accuracy requirement of the flash ADCs (and thus the correction will not correct for errors made in the final 4-bit flash conversion. However, any error Component Accuracy Digital error correction does not correct gain or linearity errors in , with digital error correction, this works the same way as a regular MDAC stage with 2-bit
/datasheets/files/maxim/0002/appno007.htm
Maxim 04/04/2001 23.21 Kb HTM appno007.htm
recent years, a new error correction technique knows as Turbo Code has been the subject of intense adopt more efficient modulation and error correction schemes. As anyone who has accidentally error correction algorithms. The greater efficiency of Turbo Code technology means that for the same first device to integrate a Zero IF tuner, a multistandard demodulator and a Forward Error Correction
/datasheets/files/stmicroelectronics/stonline/press/magazine/challeng/2ndedi00/chal08.htm
STMicroelectronics 21/08/2000 9.76 Kb HTM chal08.htm
memory due to the inclusion of error correction in the hard disk subsystem, the block transfer of data three or four bit/cell) technology. The use of error correction, and the large block transfer of data solid-state disk system would include error correction and would generate non-standard voltages to interface the process, allowing removal of the error correction requirement for two bit/cells. This data requirements initially envisioned for M.L.C.: error correction and precision external power supplies. The
/datasheets/files/intel/techno~1/itj/q41997/articles/art_1g.htm
Intel 31/10/1998 11.79 Kb HTM art_1g.htm
memory due to the inclusion of error correction in the hard disk subsystem, the block transfer of data three or four bit/cell) technology. The use of error correction, and the large block transfer of data solid-state disk system would include error correction and would generate non-standard voltages to interface the process, allowing removal of the error correction requirement for two bit/cells. This data requirements initially envisioned for M.L.C.: error correction and precision external power supplies. The
/datasheets/files/intel/techno~1/itj/q41997/articles/art_1g-v1.htm
Intel 02/02/1999 11.79 Kb HTM art_1g-v1.htm
NSC: Communications\Residential Broadband Subscriber Equipment\Cable Modem\Fwd Error Correction - Communications - Residential Broadband Subscriber Equipment - Cable Modem Block Diagram - Fwd Error Correction Feedback Copyright © 1996 National Semiconductor Corporation National is ISO 9000 certified .
/datasheets/files/national/docs/wcd00044/wcd044ec.htm
National 03/04/1998 3.29 Kb HTM wcd044ec.htm