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Part Manufacturer Description PDF & SAMPLES
NCP1608BDR2G ON Semiconductor PFC Controller, Critical Conduction Mode, with a Transconductance Error Amplifier, SOIC-8 Narrow Body, 2500-REEL
SN74LS630N Texas Instruments 16-Bit Parallel Error Detection And Correction Circuits 28-PDIP 0 to 70
CX24116-12Z,557 NXP Semiconductors DVB-S2 Demodulator and Forward Error Correction Decoder; Package: SOT638-4 (HTQFP100); Container: Tray Dry Pack, Bakeable, Multiple
CX24116-12Z,518 NXP Semiconductors DVB-S2 Demodulator and Forward Error Correction Decoder; Package: SOT638-4 (HTQFP100); Container: Reel Dry Pack, SMD, 13"
CS1501 Cirrus Logic High Efficiency Digital Power Factor Correction ICs
CS1500-FSZ Cirrus Logic Power Factor Controller, 0.5A, 70kHz Switching Freq-Max, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8

"Error correction"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: . 16 Figure 2.1.5.7 Receive _MAIN After 1st Horizontal Error Correction . 17 Figure 2.1.5.8 Reception After 2nd Horizontal Error Correction . 18 Figure , Figure 2.2.5.10 Reception After 2nd Horizontal Error Correction . 41 Figure , . 44 Figure 2.2.5.14 Receive _SUB After 1st Horizontal Error Correction . 45 , regenerated by error correction. Therefore, by watching for missing packets, simultaneous reception of the OKI Electric Industry
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MSM9562/63/66/67 E2Y0001-29-11 16-PRE
Abstract: bje is not are su is tice:Th metric limits No para Some ERROR CORRECTION WITH VARIABLE , , Euclidean stage, Chen search & error value stage), so it realizes high speed error correction operation. Capable of erasure correcting function and it improves error correction performance. · Where error , is tice:Th metric limits No para Some M64403FP ERROR CORRECTION WITH VARIABLE LENGTH AND , :Th metric limits No para Some M64403FP ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE Mitsubishi
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T22N aRm3 BJE 61 Z65T D181
Abstract: . 16 Figure 2.1.5.7 Receive _MAIN After 1st Horizontal Error Correction . 17 Figure 2.1.5.8 Reception After 2nd Horizontal Error Correction . 18 Figure , Figure 2.2.5.10 Reception After 2nd Horizontal Error Correction . 41 Figure , . 44 Figure 2.2.5.14 Receive _SUB After 1st Horizontal Error Correction . 45 , sub-station reception, missing main station packets can be regenerated by error correction. Therefore, by OKI Electric Industry
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Si 2158 Tuner VICS TUNER PEXL9562-67FLOW-10
Abstract: SYNCHRONIZATION REGISTERS . 5-34 5.8 ERROR CORRECTION REGISTERS , consisting of an SCF, frame synchronization circuit, and error correction circuit on a single chip. They , frame memory enables automatic error correction. · Built-in bandpass filter (SCF) · Built-in block , Vref SG Filter Section PN Descrambler Receive RAM SÆP FRAME memory Error correction , / disconnection _SUB (R_04) Clock regeneration _SUB Receive RAM after first horizontal error correction OKI Electric Industry
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MSM9562 MSM9552 MSM9554 MSM9562GA QFP44-P-910-0 FEUL9562-01 E2Y0002-29-62 MSM9562/9563 MSM9552/9553
Abstract: SYNCHRONIZATION REGISTERS . 5-34 5.8 ERROR CORRECTION REGISTERS , consisting of an SCF, frame synchronization circuit, and error correction circuit on a single chip. They , frame memory enables automatic error correction. · Built-in bandpass filter (SCF) · Built-in block , first horizontal error correction _SUB Tuner Block synchronization _SUB (L1BF_SUB) Receive , automatically accumulate the received data after the first horizontal error correction in the frame memory OKI Electric Industry
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MSM9563 MSM9553 MSM9555 MSM9563GA FEUL9563-02
Abstract: SYNCHRONIZATION REGISTERS . 5-34 5.8 ERROR CORRECTION REGISTERS , an SCF, frame synchronization circuit, and error correction circuit on a single chip. They allow a , frame memory enables automatic error correction. · Built-in bandpass filter (SCF) · Built-in block , _04) Clock regeneration _SUB Receive RAM after first horizontal error correction _SUB Tuner Block , RAM after first horizontal error correction _MAIN (L1BF) 5-2 Main station Frame memory OKI Electric Industry
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Abstract: MITSUBISHI ICS (LSI) M64403FP n -p a - so m aP ERROR CORRECTION WITH VARIABLE LENGTH AND , stage, Chen search & error value stage), so it realizes high speed error correction operation. 9 C apable of erasure correcting function and it im proves error correction performance. · W here error , -C MITSUBISHI ICS (LSI) M64403FP n -p a - so m aP ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE BLOCK DIAGRAM MITSUBISHI ICS (LSI) p ftE A -V M64403FP ERROR CORRECTION WITH VARIABLE LENGTH -
OCR Scan
a2160 U22N 64403FP
Abstract: detection and single-burst error correction with ECC polynomial â'¢ Programmable correction span of 5,8 or , error detection and correction circuit used to insure data integrity between two serial ports. An , for error correction. The ECC polynomial has a maximum correction span of 11 bits in series and a , hardware correction, error syndrome appears during software correction; and error pattern appears during , end of the receive cycle means that the data read is in error. 16 EOC End of Correction This output -
OCR Scan
Abstract: SYNCHRONIZATION REGISTERS . 5-34 5.8 ERROR CORRECTION REGISTERS , enables automatic error correction. · Built-in bandpass filter (SCF) · Built-in block synchronization , Section PN Descrambler SÆP Receive RAM FRAME memory Error correction Data processor , regeneration _SUB Receive RAM after first horizontal error correction _SUB Tuner Block , RAM after first horizontal error correction _MAIN (L1BF) 5-2 Main station Frame memory OKI Electric Industry
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MSM9567 PEUL9567-01 76khz filter MSM9562/9563/9566
Abstract: , 2006 Single Error Correction and Double Error Detection Author: Simon Tam Summary This application note describes the implementation of an Error Correction Control (ECC) module in a VirtexTM-II , . Introduction Error detection and correction is found in many high-reliability and performance applications , .2) August 9, 2006 www.xilinx.com 1 R Single Error Correction and Double Error Detection For , XAPP645 (v2.2) August 9, 2006 R Single Error Correction and Double Error Detection When there is Xilinx
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vhdl code for 9 bit parity generator hamming code FPGA verilog code hamming vhdl code for 8 bit parity generator hamming code vhdl code hamming ecc
Abstract: SYNCHRONIZATION REGISTERS . 5-34 5.8 ERROR CORRECTION REGISTERS , enables automatic error correction. · Built-in bandpass filter (SCF) · Built-in block synchronization , Section PN Descrambler SÆP Receive RAM FRAME memory Error correction Data processor , / disconnection _SUB (R_04) Clock regeneration _SUB Receive RAM after first horizontal error correction , station Data reproduction Receive RAM after first horizontal error correction _MAIN (L1BF) 5-2 OKI Electric Industry
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MSM9566 PEUL9566-01
Abstract: basic input/output curve, raw error, and error after correction for offset and gain. The below data , AN142 4. Average input to output error with correction for offset and gain for each input voltage at , with no correction for offset or gain. It includes error at each temperature with three standard deviations. 5. Worst case input to output error with correction for offset and gain. The term +3 Stdev is , error (expanded - starts at 10mV input). This is the raw error with no correction for offset or gain Xicor
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X3100 X24C16 keithley 2002 7493 7493 pc HP6626 Keithley 160
Abstract: MITSUBISHI ICs (LSI) M64403FP p fV E V -V s mP o ERROR CORRECTION WITH VARIABLE LENGTH , , Euclidean stage, Chen search & error value stage), so it realizes high speed error correction operation. â'¢ C apable o f erasure correcting function and it im proves error correction performance. â , e^ ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE BLOCK DIAGRAM IN PU T l/F SY N D R , S S S - ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE ABSOLUTE MAXIMUM RATINGS Symbol -
OCR Scan
16777216-BIT 4194304-WORD 00SS47L
Abstract: transparent to the user. In addition, complete burst error detection and correction can be done automatically , "no error correction" mode. It is 270 bits in the "error correction" mode, since 256 bits of data and a 14 bit error correction code must be used in this mode of operation. 3-31 AFN-01358A 7242 The , received by the Command Decoder. If a block length other than 272 bits is used in the no error correction , bubble) is written into bad loops. Error Correction Logic â'" The Error Correction Logic contains the -
OCR Scan
intel 8055 BPK70 YC-11
Abstract: Error Correction NONE NONE NONE © Motorola, Inc., 2002. All rights reserved. 1.2 , 's Manual, Rev 1.0. Table B: Chapter 1 Errors Error Location Error Correction NONE NONE , : Chapter 3 Errors Error Location Error Correction Page 4-5 Additional information See Part , . Table E: Chapter 4 Errors Error Location Error Correction Page 4-5, Section 4.3.4, last word , Error Correction NONE NONE NONE DSP56F826/827 Corrections to Rev. 1.0 of User's Manual Motorola
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DSP56F82 DSP56826-827UM/D-R
Abstract: -bit check word from a 16-bit data word. FAST 74F630, 74F631 Error Detection Correction 16-Bit Parallel Error Detection and Correction ('F630 â'" 3-State) ('F631 â'"Open-Collector) Preliminary Specification , Specification Error Detection Correction FAST 74F630, 74F631 LOGIC DIAGRAM This check word is stored along , , and the CPU sends the EDAC through the correction cycle even though the 16-bit word is not in error. The correction cycle will simply pass along the original 16-bit word in this case and produce error -
OCR Scan
N74F630N N74F631N N74F630D N74F631D f630 F631 hamming code-error detection correction DB0-DB15 OC/33
Abstract: Signetìcs FAST Products FAST 74F630, 74F631 Error Detection Correction 16-Bit Parallel Error Detection and Correction (F630 â'" 3-State) (F631 â'"Open-Collector) Preliminary Specification , DESCRIPTION The 'F630 and 'F631 devices are 16-bit parallel error detection and correction circuits (EDACs , Products Preliminary Specification Error Detection Correction FAST 74F630, 74F631 LOGIC DIAGRAM This , -bit word is not in error. The correction cycle will simply pass along the original 16-bit word in this case -
OCR Scan
N74F6300 OC/20 CFS30
Abstract: .5-23 5.6 ERROR CORRECTION REGISTERS . 5-24 , Transfer Port for Error Correction . 5-24 5.6.3 Error , synchronization circuit, and error correction circuit, on a single chip. They allow a system for acquisition of , Error correction, Layer 2 CRC Layer 4 CRC CLR DVDD 1T delay circuit + Data bus Address , tIWRWRE Error correction 250 - - ns WR tIRDRDE Error correction 250 - OKI Electric Industry
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BIC3 MSM9552GS-2K MSM9553GS-2K WR31 E2Y0001-28-30
Abstract: operation. DESCRIPTION The Signetics 2960 Error Detection and Correction Unit (EDC) (Figure 1) contains , Error Detection and Correction (EDC) Unit 2960 2960 PACKAGE AND PIN DESIGNATIONS correct Å' â'¢ 48 1 , Product Specification Error Detection and Correction (EDC) Unit 2960 PIN DESCRIPTION (Continued) PIN NO , detection. Also used to input syndrome bits for error correction in 32 and 64-bit configurations. 36 Vcc + , a powerful 16-bit cascadable slice used for check bit generation, error detection, error correction -
OCR Scan
sc-fr pc cable 61c16 code de hamming N2960I N2960N DATA15
Abstract: . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Principle of the Error Correction by , 11 9 Error Correction With the Mean Value of the Used Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10 Principle of the Error Correction With the , . . . . . . . . . . . . . 14 12 Principle of the Error Correction With the Centers of the Four , Range -4 -6 -8 -10 ADC Steps [0 to 16383] Figure 9. Error Correction With the Mean Value of Texas Instruments
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MSP430 SLAA047 AD7846 ADC calibration msp430 10 bit adc TPC4016 SLAA045 SLAA046 SLAA048 SLAA050
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