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"Dual-Port RAM" for video applications

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: tradeoffs and are best-suited for different applications. These solutions vary from no arbitration , semaphores might be applied involves two processors working together to generate a video display for , Block Diagram of Video Display System for Animation In this particular application, the dual-port RAM , where two processors must synchronize through arbitration for access to a bus which is used to access , RAM IDT7130 IDT7132 IDT71322 IDT7134 IDT71342 Most applications cannot sacrifice data Integrated Device Technology
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M68020 I80386 TMS3020 TMS30 idt7130l55 I80386 cache AN-14 IDT7130/7132
Abstract: Technology to Enable Imaging Applications as FIFOs, caches for High-end video applications require , buffered designs such 1200 as 160 Gbps network switches and high definition video applications. Xilinx , block RAM, and also the 800 Virtex-E 400 Virtex · Support for 20 I/O standards, including , memory resources · 8 DLLs for 311 +MHz clock management © 2000, Xilinx, Inc. All rights reserved. The , distributed RAM for pixel manipulation. If more High Speed External RAM 40 x 60 Logic Cells Xilinx
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XCV812E XCV405E FG676 em 404 JPEG2000 XC4000 OC-192 BG560 FG900
Abstract: issue have different tradeoffs and are best-suited for different applications. These solutions vary , Figure 5B. Software Block Diagram of Video Display System for Animation display for animated images , where two processors must synchronize through arbitration for access to a bus which is used to access , SRAM Most applications cannot sacrifice data integrity and utilize the dual-port memory as a , memory location resolution is required. For example, the IDT7130/7132 use an address comparison mechanism Integrated Device Technology
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arbitration scheme of 8051 processor chart
Abstract: approaches to the arbitration issue have different tradeoffs and are best-suited for different applications , working together to generate a video display for animated images. The "MASTER" processor generates a , through arbitration for access to a bus which is used to access one location at a time in a standard , restricted to certain applications. If arbitration is not required, the IDT7134 can be used. It is a 4K x 8 , arbiter is used for a whole array composed of many IDT7134s. The interrupt handshake mechanism can be Integrated Device Technology
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Application Note AN-14 IDT49C000
Abstract: Block write operation APPLICATION Display equipment for personal computer/work station. Frame memory for digital T V /V C R , Videotex, Teletext, Video printer. High Speed data transmission systems , MITSUBISHI LSIs MH12816AJZ-8,-10 2 0 9 7 1 5 2 -B IT DUAL-PORT DYNAMIC , single in-line package pro­ vides any applications where high densities and large quantities of memory , 5-5 MITSUBISHI LSIs MH12816AJZ 2 0 9 7 1 5 2 -B IT DUAL-PORT DYNAMIC -
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M5M482128AJ
Abstract: approaches to the arbitration issue have different tradeoffs and are best-suited for different applications , to generate a video display for animated images. The MASTER processor generates a picture layout in , 3558 drw 07 Figure 5B. Software Block Diagram of Video Display System for Animation display list , through arbitration for access to a bus which is used to access one location at a time in a standard , restricted to certain applications. If arbitration is not required, the IDT7134 can be used. It is a 4K x 8 Integrated Device Technology
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DUAL-PORT STATIC RAM WITH SEMAPHORE dual port SRAM dual port SRAM PLCC
Abstract: read and write ports. The dual-port structure makes the memory suitable for FIFO applications such as , transferred data between the host bus and the peripheral systems. Some common applications using FIFO buffers are SCSI and IDE interfaces, bus-width conversion applications (e.g., 8-bit to 32-bit conversions , logic implemented in PALs or PLDs. The 3200DX family provides for a system's memory needs by supplying , memory. The block structure of the 3200DX SRAM makes it particularly suitable for data-path designs, in Actel
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AC124 3265DX 32140DX 32x8 SRAM 3265d 32100DX 32200DX 32300DX
Abstract: memory for special applications. Hydra-II has a VME slave-only interface via a 32-kByte bank of , three 8-bit video DACs for 24-bit RGB output plus comm-port interfaces to external TMS320C4x processors , custom designs for a wide range of industrial, commercial, military/government, educational, and research applications. In its 15-year history, Ariel has developed more than 30 new DSP-based-off-theshelf , TMS320C40 dual-bus processor. The HydraPlus is a 6U VME board with four 50-MHz processors for peak Ariel
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VME32 DSP-C40 ariel 656 Series TMS320C80 TMS320C44 16-MB 12-MB TMS320C4 50-MFLOPS
Abstract: read and write ports. The dual-port structure makes the memory suitable for FIFO applications such as , transferred data between the host bus and the peripheral systems. Some common applications using FIFO buffers are SCSI and IDE interfaces, bus-width conversion applications (e.g., 8-bit to 32-bit conversions , logic implemented in PALs or PLDs. The 3200DX family provides for a system's memory needs by supplying , memory. The block structure of the 3200DX SRAM makes it particularly suitable for data-path designs, in Actel
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Abstract: valid. Applications Designed for use in multiprocessor systems, the AT&T DPRAM can be used in a , contention for either port: ATT7C310J-55 - 110 ns ATT7C310J-75 - 150 ns Minimum cycle time for either port , Vcc and Vss pins must be connected for proper operation. Figure 2. Pin Function Diagram Table 1 , numerical order and do not necessarily coincide with the symbol names as shown. See Figure 2 for correct pin numbers, t All Vcc and Vss pins must be connected for proper operation. X Letter "A" or " B " follows the -
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ATT7C310J M79018DX-15
Abstract: for higher video compression in applications such as videoconferencing, digital storage media , enable the coded video representation in a flexible manner for a wide variety of network environments. 1 , real-time video processing. We achieved the necessary performance for a reduced frame rate using the Nios , performance target. However, 27 fps is good enough for today's mobile video streaming service. Design , Introduction H.264/AVC is a video standard of the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Altera
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h264 decoder Dual-Port RAM television block diagram 90-MH
Abstract: , enable-slave low to data valid. Applications Designed for use in multiprocessor systems, the AT&T DPRAM can , uncontested access time of 55 ns Maximum cycle time for either port of 130 ns CMOS, six-transistor memory , Vss pins must be connected for proper operation. Figure 2. Pin Function Diagram Table 1. Pin , in num erical order and do not necessarily coincide with the symbol names. S ee Figure 2 for correct pin numbers, t All Vcc and Vss pins must be connected for proper operation. $ Letter "A" or " B " -
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ATT7C314J
Abstract: Applications: Digital communications systems, digital audio and video broadcast systems, and data storage , discrete, streaming, and continuous Reed-Solomon encoders/decoders Optimized for APEX 20K and FLEX 10K , ) functions used in many digital communications systems. Applications that store or transmit digital data , are needed for transport channels that require a low bit-error ratio (BER). Therefore, interleaving , function as well as a MAX+PLUS® II Vector File (.vec) that you can use to simulate the function. For Altera
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interleaver block convolutional interleaving Convolutional
Abstract: developed for high-resolution color graphics in such applications as CAE/CAD/CAM, image processing, and video reconstruction. The architecture provides for the display of 1280 x 1024 bit-mapped color graphics , -word x 24-bit RAM used as a lookup table with three 8-bit, video, D/A converters. On-chip features such , -C 110 MHz 135 MHz 110 MHz t For the complete data sheet, refer to the Graphics and Imaging Data Book -
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RS-343-A TLC34058 XLAS050 135-MH SMJ340 TMS340XX
Abstract: MITSUBISHI LS Is , as a W rite Transfer. The mounting of S O J on a single in-line package pro vides any applications , L IC A T IO N Display equipment for personal computer/work station. Frame memory for digital TV/VCR, Videotex, Teletext, Video printer, High Speed data transmission systems. -3/49- A MITSUBISHI ELECTRIC 5-5 MITSUBISHI LSIs -
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M5M482128A mitsubishi split ac 482128AJ VIH12816AJZ 12816AJZ
Abstract: -bit organization (AL5DS9069V/79V/89V/99V) Supports byte write/read for 16/18 bit devices Separate upper-byte and lower-byte controls for bus matching (16/18 bit devices only) 3 modes supported: -Pipelined -Flow-Through , Supports depth and width expansion 0.25-micron CMOS for optimum speed / power High speed clock to data , control signals for each port to access a common SRAM array. A dual-port RAM is generally classified with , of data between processors, processes and systems. Each port contains an internal counter for fast AverLogic Technologies
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3.3v counter sram with address counter 4K/8K/16K/32K/64K/128K 4K/8K/16K/32K/64K AL5DS9349V/59V/69V/79V/89V 16K/32K/64K AL5DS9269V/79V/89V 8K/16K/32K/64K/128K
Abstract:  description The TLC34058 color-palette integrated circuit is specifically developed for high-resolution color graphics in such applications as CAE/CAD/CAM, image processing, and video reconstruction. The architecture provides for the display of 1280 x 1024 bit-mapped color graphics (up to eight bits , used as a lookup table with three 8-bit, video, D/A converters. On-chip features such as high-speed , -135FN - â'"55°C to 125°C 110 MHz 8 Bits TLC34058-110MGA - TLC34058-110MHFG t For the complete data -
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B1458 TLC34058-80FN TLC34058-110FN TLC34058-135FN bt458 RS-343A XLAS050-APRIL SLAD002
Abstract: assigned to any side of the chip. Three types of power lines are assigned on the chip-one for the core power line, one for the standard 3.3 V interface power line, and one for the optional high-speed , Gates SRAM SRAM SRAM APLL (Phase shift) VDD33 SRAM SRAM VDD Applications Designs suitable for CMOS-12M are those that require: - Large-size memory blocks - High performance - Low power consumption - Small area - Reduction in cost APLL (Phase shift) VDDQ1 VDD33: Power line for standard NEC
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A1742 LCD panel timing control nec b 708 nec gate drive panel nec gate drive panel lcd PD66208 PD66201 PD66206
Abstract: New Products FPGAs New Spartan-IIE FPGA Family for Digital Consumer Convergence Applications Spartan-IIE FPGAs offer significant performance improvements for nextgeneration consumer products. by Ashok , at digital consumer convergence applications where video, audio, communication, and data technologies , . Distributed RAM Distributed RAM is an ideal solution for designs that require multiple, small, fast, and , . These memories can even be cascaded for various data widths or depths. The competing FPGA families do Xilinx
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LVCMOS18
Abstract: - Programmable Background Color for Inactive Area - Glueless Interface for Most Digital Video , Section 19 Video Controller for more information. 1.2.4.2 THE LCD CONTROLLER. The LCD controller provides , display capabilities. Specifically, it supports the universal serial bus and video display systems and , embedded PowerPCTM core with a communication processor module that uses a specialized RISC processor for , functions for image compression and decompression and supports six serial channels-one serial Motorola
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MPC823 MPC821 F98S CCIR-656 powerpc 601 advanced information PowerPC 601 interface circuit 66MIPS
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