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ISL59923IRZ-EVALZ Intersil Corporation Evaluation Board for ISL59923 Video Delay Line
ISL59922IRZ-EVALZ Intersil Corporation Evaluation Board for ISL59922 Video Delay Line
ISL59921IRZ-EVALZ Intersil Corporation Evaluation Board for ISL59921 Video Delay Line
EL9115ILZ-T13 Intersil Corporation Triple Analog Video Delay Line; QFN20; Temp Range: -40° to 85°C
ISL59920IRZ Intersil Corporation Triple Analog Video Delay Line; QFN20; Temp Range: -40° to 85°C
EL9115ILZ-T7 Intersil Corporation Triple Analog Video Delay Line; QFN20; Temp Range: -40° to 85°C

"Digital Delay Lines"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: DIGITAL DELAY LINES S423 Series, 5 tap S422 Series, 10 tap PASSIVE DELAY LINES A446 and 0446 Series , delay generator CMOS DIGITAL DELAY LINES 0450-XXXX-02 14 pin DIP, 5 tap ECL 10K DIGITAL DELAY , bit programmable 0454-XXXX-01 16 pin DIP, pulse generator ECL 100K DIGITAL DELAY LINES 0461 , defining a degree of excellence DELAY LINES TABLE OF CONTENTS GENERAL CHARACTERISTICS Considerations for specifying delay lines 4 5 6-7 8 9 10 11 12 13 13 14 15 16 17 18 19 20 21 22 22 23 24 25 26 27 -
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Delay Lines Digital Delay Lines 0438 Series digital delay generator A447-XXXX-08 A447-XXXX-09 A447-XXXX-A3 0462-XXXX-02 A463-XXXX-02 A447-XXXX-02
Abstract: Active Delay Lines Testing DEFINITION & TEST "Actives" are " Digital Delay Lines" which incorporate a delay line and an integrated circuit The use of logic gates, packaged with passive delay lines, allows the use of digital or logic signals. As a consequence of function, the descriptions such a s ' ` Digital Delay Lines" , ``Digital Delay Units" , ``Digital Delay M odules" , " Digital Program m able Delay Lines" , etc., have becom e some of the titles give to this type of ACTIVE DELAY LINE These units are -
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Abstract: Active Delay Lines Testing DEFINITION & TEST "Actives" are `Digital Delay Lines which incorporate a delay line and an integrated circuit. The use of logic gates, packaged with passive delay lines, allows the use of digital or logic signals As a consequence of function, the descriptions such as `'Digital Delay Lines", " Digital Delay Units", " Digital Delay M odules", "D ig ital Program m able Delay Lines", etc., have becom e some of the titles give to this type of ACTIVE DELAY LINE. These units are -
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Abstract: demonstration program written in QuickBASIC. Features 16 programmable digital I/O lines CMOS/TTL compatible , configuring the module: set module address, set communication turn-around delay, define I/O lines, set output , Set Turn-around Delay Define I/O Lines Set Powerup States !{addr}SO{I/O msb}{I/O lsb} !{addr}RD , Address Set Turn-around Delay Define I/O Lines Set Powerup States Read Configuration no response , . Digital I/O Lines The 485SDD16 has 16 programmable I/O lines. As inputs they are CMOS/TTL compatible. As B&B Electronics
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485SDD16-1712 RS-485 RS-422/485 DB25S
Abstract: the early stages of delay line development by supplying distributed parameter delay lines to the television industry. When computers and peripheral equipment manufacturers needed special delay lines bel intro duced lumped parameter and digital delay lines. Today bel supplies delay lines to major computer , digital as well as passive lumped constant delay lines. In terms of semiconductor fami lies we supply digital delay lines utilizing TTL, CMOS, ECL 10K, ECL 10KH and ECL 100K. Packaging is provided as single -
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432-0463/TWX 710-730-5301/FAX
Abstract: for short delay lines both analog and digital types, but ESC is still the most chosen source for delay , GENERAL D ELAY LINE INFORMATION ESC 's extensive series of LC delay lines in the , . Standard Lumped Constant Delay Lines Bulletin M IL Programmable Delay Lines Bulletin PR Series of hermetically sealed steel cased delay lines for chassis mounting, built to M IL-D -2 3 85 9 . , of adjustable delay lines at constant input to output impedance. Delay ranges from 25 nsec to 1000 -
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Abstract: SmartRelayOutside.pdf 1 9/24/12 1:35 PM Altech Universal Digital Multi-Timer Altechâ'™s AMT-Series of Universal Digital Multi-Timers comprises 4 models featuring 8 or 18 timer functions , Time and Run Time DIN Rail Mounted 17.5mm Width LISTED Digital Timers Cat. No. Output , 1) ON Delay [A] 2) Cyclic OFF/ ON [b] 3) Cyclic ON/ OFF [C] 4) Signal ON/ OFF [d] 5) Signal OFF Delay [E] 6) Interval [F] 7) Signal OFF/ ON [G] 8) One Shot Output [H] Functions / [setting mode Altech
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E351145 AMT12-S1 ASR-B120AC 94-V0
Abstract: Application Report SLEU047 ­ OCTOBER 2003r TVP5146 and TVP5150A VBI Raw Data Mode HPA Digital , systems where VBI data slicing and processing is handled in the digital backend receiver instead of the , being replaced with the luma samples. The default VBLK interval for Field 1 is defined as lines 1 through 20 for 525-line video formats and lines 623 through 23 for 625-line video formats. This interval may be adjusted to include additional lines. Support for NTSC line 21 closed caption data, for Texas Instruments
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itu 656 converter video blanking interval 22H-23H bt.656 ti 06h TVP514
Abstract: ) delay lines with digital circuitry, active (digital) delay lines have been developed to provide design , quality or delay accuracy. Rhombus Industries offers an array of digital delay lines designed to provide , 's output has the edge rate characteristic of the respective logic family. Thus, active delay lines can be , -202. Certain families available as MILGRADE by adding "M" suffix. Active delay lines are available in a wide , · FAX: (714)896-0971 EDGE-TO-EDGE RELATIONSHIP Typically, active delay lines are specified and -
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TRAILING TTL ACTIVE DELAY LINE 100KECL ACTIVE-6/93
Abstract: calibration Digital I/O 8 bidirectional lines Counter/timers Two 24-bit resolution 20 MHz maximum source , with voltage outputs. Both models include eight lines of TTL-compatible digital I/O and two 24-bit 20 , outputs, eight TTL-compatible digital I/O lines, two 24-bit 20 MHz up/down counter timers and analog , , two 16-bit analog outputs, eight TTL-compatible digital I/O lines, two 24-bit 20 MHz up/down counter , analog outputs as variable voltage sources. The digital I/O lines can interface to external digital National Instruments
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WIN95 VXI-MIO-64XE-10 ACH55 777141-01 ACH25 ACH36 ACH59 digital voltmeter application GWIN95 VXI-MIO-64E-1 TBX-96 SCXI-1356
Abstract: High-Speed Digital I/O Module PXI-6533 PXI-6533 Digital I/O 32 lines Transfer rates up to 20 , 32 digital I/O lines individually for input or output or as four 8-bit ports. The ports can be , handshaking, triggering, and clock lines may be used as multipurpose Digital I/O Connector I/O lines. The CPULL and DPULL lines determine the power-on All digital I/O is through a 68-pin cable connector. The , recognition/generation Electronic and logic testing Board and chip verification Digital comparison testing National Instruments
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8255 PPI INTEL DAQDIO 8255 PPI Chip Peripheral interface 8255 8255 pci or dma PPI 82C55 430FX
Abstract: Maxim > App Notes > OSCILLATORS/DELAY LINES/TIMERS/COUNTERS Keywords: delay line, ST&C, STC , Tech Brief 37: Replacing Passive Hybrid Delay Lines with All-Silicon Delay Lines Abstract: Dallas Semiconductor's all-silicon delay lines provide a low-cost alternative to the traditional delay line , types of delay lines and covers some of the issues required when designing an all-silicon delay line in as a replacement for a modular delay line. As the availability of hybrid delay lines continues to Maxim Integrated Products
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DS1100 DS1135 DS1020 DS1021 DS1023 DS1004 AN983
Abstract: Tech Brief 37 Replacing Passive Hybrid Delay Lines with All-Silicon Delay Lines www.maxim-ic.com Replacing Passive Hybrid Delay Lines with Silicon Delay Lines As the availability of hybrid delay lines , . Dallas Semiconductor does not offer direct replacements for any passive delay lines. However, in many , are purely digital. Some passive delays are used in purely analog applications, in which case no replacement option exists. In other applications, passive delays are used in digital fashion but with reduced Dallas Semiconductor
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Direct Replacement DALLAS analog delay line Analog Delay Lines
Abstract: Delay The digital outputs, DB[11:0] and OVER, are synchronized to ADCLK. When ADCLKpol=0 (default), the digital outputs change on the rising edge of ADCLK. Figure 14 shows the pipeline delay (latency) from , Clipper DNS Filter Removes Black Level Digital Noise Programmable Black Level, up to code 255 Black Level , Current · Three-state Digital Outputs · 3,000V ESD Protection · 48-pin TQFP Package APPLICATIONS · · · · · · · · · · Mega pixel Digital Still Cameras Digital Camcorders 3 CCD Professional/Broadcast Camera Exar
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XRD98L63 XRD98L63AIV-F TQFP48
Abstract: with skew control for enterprise and network servers. â'¢ Filters, delay lines, pulse compression , . SAW filters, dispersive delay lines, pulse compression systems, compressive receiver subsystems and , : 508-852-8456 mvmwjnicronetworks.com Introduction Industrial Instrumentation M arket Delay Lines Micro , ) and BAW (Bulk Acoustic Wave) designs. â'¢ SAW Delay Lines â'¢ BAW Delay Lines â'¢ Dispersive Delay , '¢ Delay Lines â'¢ Data Conversion Products â'¢ Custom Microelectronics Data Conversion Products -
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MIL-PRF-38534 ISO-9000 ISO-14000 1300MH
Abstract: , min.Gain 400 uVrms Gain Code = 0 (6dB) Latency Pipeline Delay 7.5 cycles Digital , . Unit 20 27 ns Conditions Digital I/O Timing tDL Data Valid Delay 10 pF load , Calibration Figure 15. Clock Polarity & Aperture Delays Pipeline Delay The digital outputs, DB[11:0] and , Pixel Averager and Hot Pixel Clipper DNS Filter Removes Black Level Digital Noise Programmable Black , Power for Battery Operation 100uA Stand-by Mode Current · Three-state Digital Outputs · 3,000V ESD Exar
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DB10 XRD98L63AIV
Abstract: Delay The digital outputs, DB[11:0] and OVER, are synchronized to ADCLK. When ADCLKpol=0 (default), the digital outputs change on the rising edge of ADCLK. Figure 14 shows the pipeline delay (latency) from , Clipper DNS Filter Removes Black Level Digital Noise Programmable Black Level, up to code 255 Black Level , Current · Three-state Digital Outputs · 3,000V ESD Protection · 48-pin TQFP Package APPLICATIONS · · · · · · · · · · Mega pixel Digital Still Cameras Digital Camcorders 3 CCD Professional/Broadcast Camera Exar
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pga11
Abstract: separate accumulators for even and odd lines. Calibration Options Digital Noise Suppression (DNS) Filter , Logic AFE ADC Calibration Figure 15. Clock Polarity & Aperture Delays Pipeline Delay The digital , and Hot Pixel Clipper DNS Filter Removes Black Level Digital Noise Programmable Black Level, up to , Operation 100uA Stand-by Mode Current · · · Three-state Digital Outputs 2,000V ESD Protection 48-pin TQFP Package APPLICATIONS · · · · · · · · · · Mega pixel Digital Still Cameras Digital Exar
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Abstract: with various colour decoder ICs (e.g. TDA8466, TDA8391). The device incorporates two delay lines with a , signals and clock drivers for the delay lines which are driven from an internal voltage controlled , , preamplifier and clamp circuit to the delay lines. The delayed and direct signals are added in the matrix , delay lines are driven by the internal clock drivers at half on the PLL frequency. The outputs from the delay lines are applied to the sample-and-hold low-pass filter output stages which are used to reduce -
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TDA8451A TDA8451 TDA8490 CCD matrix matrix CCD TDA8453 7110A5L T-47-21 T0A8453A CV831
Abstract: Delay The digital outputs, DB[11:0] and OVER, are synchronized to ADCLK. When ADCLKpol=0 (default), the digital outputs change on the rising edge of ADCLK. Figure 14 shows the pipeline delay (latency) from , with Pixel Averager and Hot Pixel Clipper DNS Filter Removes Black Level Digital Noise Programmable , to 100mW Low Power for Battery Operation 100uA Stand-by Mode Current · Three-state Digital , Mega pixel Digital Still Cameras Digital Camcorders 3 CCD Professional/Broadcast Camera Line Scan Exar
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panasonic ccd dsp Color Filter Array CFA
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