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Part Manufacturer Description PDF & SAMPLES
CS5506-BSZR Cirrus Logic Converters - Analog to Digital (ADC) IC 20-Bit 4-Ch ADC
CS5531-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC 16-Bit ADCs w/UltraLw Noise PGIA
CS5507-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC 16-Bit 4-Ch ADC
CS5525-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC 16Bit Delta Sigma Multi-Range ADC
CS5534-BSZR Cirrus Logic Converters - Analog to Digital (ADC) IC 24-Bit ADCs w/UltraLw Noise PGIA
CS5505-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC 16-Bit 4-Ch ADC

"Digital Delay Line"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: .470 line timing and shows how Intersil digital video encoders (HMP8154, HMP8156A, HMP8170-73, and HMP8190 , ) 52.0 ± 0.3us 12.0 ± 0.3us The overscanned portions of the line in the digital data allow for , 3. TABLE 3. DIGITAL OVERSCAN AMOUNTS Digital Overscan TABLE 1. BT.601 DIGITAL VIDEO LINE , through the part. The pipeline delay is constant throughout the line. Sync delay is the number of clocks , Understanding Video Timing with Digital Video Encoders TM Technical Brief July 1998 Intersil
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ITU-R BT.470 BT-601 BT.601 BT-470 ITU-R BT.601 TB368 HMP8190-91 ISO9000
Abstract: The overscanned portions of the line in the digital data allow for slight errors in any digital , % point of the horizontal sync tip. This positions the digital data with respect to the analog line and , .601 DIGITAL VIDEO LINE TIMING VIDEO STANDARD TOTAL SAMPLES ACTIVE SAMPLES BLANKED SAMPLES , through the part. The pipeline delay is constant throughout the line. Sync delay is the number of clocks , Understanding Video Timing with Digital Video Encoders Technical Brief July 1998 TB368 Intersil
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Abstract: counter of memory only for 2 line delay data are then initialized. MITSUBISHI , M66259FP 8192 x 8-BIT x 2 LINE MEMORY n-bit delay 2 (Slides input timings of WRES and , MITSUBISHI M66259FP 8192 x 8-BIT x 2 LINE MEMORY DESCRIPTION PIN , x 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the , direct connection allowable Output : 3 states Q00 - Q07 : 1 line delay Q10 - Q17 : 2 line delay Mitsubishi
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M66259
Abstract: MITSUBISHI {DIGITAL ASSP) M66257FP 5120 x 8-BIT x 2 LINE MEMORY (FIFO) PIN CONFIGURATION , simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction oyer , MITSUBISHI {DIGITAL ASSP) M66257FP 5120 x 8-BIT x 2 LINE MEMORY (FIFO) FUNCTION _ _ When write enable input WE is â'Lâ', the contents of data inputs Do to D7 are written into 1-line delay data only , counter of 1-line delay data only memory is also incremented simultaneously. The write functions given -
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M66257
Abstract: delay data only memory are initialized. MITSUBISHI DIGITAL ASSP M66257FP 5120 × 8-BIT × 2 LINE , MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP M66257FP M66257FP 5120 × 8-BIT 2 LINE MEMORY , high-performance silicon gate CMOS process technology. It allows simultaneous output of 1-line delay data and 2-line , . 3 states · Q00 to Q07 . 1-line delay · Q10 to Q17 . 2-line delay PIN CONFIGURATION Mitsubishi
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Abstract: 28 29 30 31 32 33 DELAY LINE MEASURING TECHNIQUES DEFINITIONS DELAY LINE APPLICATIONS TTL DIGITAL , DIGITAL DELAY LINES S423 Series, 5 tap S422 Series, 10 tap PASSIVE DELAY LINES A446 and 0446 Series 14 pin DIP, 10 tap 0401 Series, 8 pin single in line, fixed delay 0438 Series, 14 pin single in line, 10 tap 0402 Series, 3 pin single in line, fixed delay 0432 Picoline 3 pin single in line, fixed , delay generator CMOS DIGITAL DELAY LINES 0450-XXXX-02 14 pin DIP, 5 tap ECL 10K DIGITAL DELAY -
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Delay Lines Digital Delay Lines 0438 Series digital delay generator A447-XXXX-08 A447-XXXX-09 A447-XXXX-A3 0462-XXXX-02 A463-XXXX-02 A447-XXXX-02
Abstract: interpolation by the control of a built-in 2H delay line Zoom operation dependent upon Y, R-Y, B-Y signal input , READ/WRITE ADDRESS for 1H LINE MEMORY CONTROLLER DELAY LINE for horizontal image expansion and 1H delay line for vertical interpolation TIMING GENERATION Generates time signals for controls , LINE SKIP to decide TGM (KS7213) Entered into vertical Digital ZOOM(KS7314) interpolation coefficient part TGM (KS7213) Horizontal zoom INTERFACE Generate line hold signal Digital Zoom Samsung Electronics
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KS7306 CXD81120 micom PD78014 80-QFP-1212
Abstract: RenesasTechnologyCorp. MITSUBISHI (DIGITAL ASSP) M66257FP 5120 x 8-BIT x 2 LINE MEMORY (FIFO) DESCRIPTION The , of 1 -line delay data and 2-line delay data, and is most suitable for data correction over multiple , .3 states ♦ Qoo to class="hl">line delay ♦ class="hl">line delay APPLICATION Digital photocopiers, high-speed facsimile, laser beam printers. PIN CONFIGURATION , 1-LINE DELAY DATA ONLY MEMORYA I 2-LINE DELAY DATA ONLY MEMORY I DC UJ 1â'" iâ'" 3 A z> O o CO -
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MITSUBISHI delay line 8 MITSUBISHI delay line
Abstract: ­ Q07 1 line delay Q10 ­ Q17 2 line delay APPLICATION · Digital copying machine, laser beam , M66281FP 5120 x 8-BIT x 2 LINE MEMORY VARIABLE LENGTH DELAY BIT · 1 line (5120 , MITSUBISHI M66281FP 5120 x 8-BIT x 2 LINE MEMORY When write reset input WRESB is set to "L", the write address counter of memory only for 1 line delay data is initialized. When read enable input REB is set to "L", the contents of memory only for 1 line delay data are output to Mitsubishi
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MITSUBISHI M M66281
Abstract: KS7314 DIGITAL ZOOM 6. Vertical interpolation LHLD 1H DELAY LINE ADDR BETA 9 x to , interpolation by the control of a built-in 2H delay line. - Zoom operation dependent upon Y, R-Y, B-Y signal , DELAY LINE for horizontal image expansion and 1H delay line for vertical interpolation. TIMING , Zoom (KS7314) zoom Digital Zoom (KS7314) INTEGER TGM (KS7213) CCD LINE SKIP to decide , (KS7213) Horizontal zoom INTERFACE Generate line hold signal Digital Zoom(KS7314) Vertical Samsung Electronics
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12MHZ d003 zoom b1 circuit VID-97-D003
Abstract: MITSUBISHI (DIGITAL ASSP) M66257FP 5120 X 8-BIT X 2 LINE MEMORY (FIFO) DESCRIPTION , simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over , . 3 states · Qoo to Q 0 7 .1 -line delay · Q 10 to 0 1 7 .2-line delay Qo7 , INPUT A m ftsubishi ELECTRIC 1 MITSUBISHI (DIGITAL ASSP) M66257FP 5120 X 8-BIT X 2 LINE -
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Abstract: delay circuits etc. LT 4 I Digital loop back. During digital 'High' any data sent on the XD , the CC line status and not on RS1. CC 5 I During digital loopback, the data on this pin , using the delay time within the device, the data on the TS1 or TS2 is not a digital 'High'), this pin , , digital 'High' should be applied to TS1 and TS2 pins and the external delay circuits used to obtain the , telephone line, and vice versa. A data signal (digital signal) from a data terminal is converted into an RS Components
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Abstract: delay circuits etc. LT 4 I Digital loop back. During digital 'High' any data sent on the XD , the CC line status and not on RS1. CC 5 I During digital loopback, the data on this pin , using the delay time within the device, the data on the TS1 or TS2 is not a digital 'High'), this pin , , digital 'High' should be applied to TS1 and TS2 pins and the external delay circuits used to obtain the , telephone line, and vice versa. A data signal (digital signal) from a data terminal is converted into an RS Components
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Abstract: Absolute maximum ratings l TTL compatible digital interface. Power supply voltage + 112V (V A , Digital input voltage _-0.3 to VD + 0.3V Storage temperature range _-55 to + 150 , ELECTROSTATIC SENSITIVE DEVICES Electrical characteristics dc and digital interface (VA = 12V ± 10%, VD = 5V , to DG 4.75 5.00 5.25 V Digital VD +5V AG,DG 0 Operating temperature T 0 70 °C OP CRYSTAL , values are typical. 2 H5982 Receive filter ORIG. 1600 800 MODE ~1900Hz Group delay D DL ANS. 930 RS Components
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Abstract: generator Digital! delay line Digital volume control L - jTM I 1 1 1 Digital delay line 1 1 , Digital delay line Digital volume control 4 1 1 i i i Digital volume control Digital delay line Parameter Delay time Register Volume Microcomputer interface i MD 0 MD1 _._i SCI i , C-MOS L SI, permits to implement digital surround sound capabilities realized by Yamaha's digital audio technology. As the L SI includes A/D and D/A converters, you can easily implement digital surround func tions -
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digital of signal generator Yamaha oversampling filter yamaha ym YM3411
Abstract: Digital Wrapper Features s Versatile IC supports single 2488 Mbits/s (16 bits at 155 Mbits/s , interleaved frames in single 9952 Mbits/s payload rate (2666 Mbits/s and 10663 Mbits/s line rate , / SDH frame with provisionable check bit allocation. s Section/RS and line/MS termination and , optionally generate an AIS signal under user control. Supports a digital wrapper (OCh) superframe with , /terminal loopback capabilities at both the line and system interfaces. Internal loopbacks for diagnostic Agere Systems
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TFEC0410G STM-16 STM-64 Internal diagram of ic 7495 OTN SWITCH regenerator in optical 0936A STS-48/ STS-192/STM-64 STS-48/STM-16 STS-192/
Abstract: to implement external delay circuits etc. LT 4 I Digital loop back. During digital 'High' , phone line depends on the CC line status and not on RS1. CC 5 I During digital loopback , (when using the delay time within the device, the data on the TS1 or TS2 is not a digital 'High'), this , , digital 'High' should be applied to TS1 and TS2 pins and the external delay circuits used to obtain the , line, and vice versa. A data signal (digital signal) from a data terminal is converted into an RS Components
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511-Bit
Abstract: MITSUBISHI (DIGITAL ASSP) M66257FP 5120 x 8-BIT x 2 LINE MEMORY (FIFO) DESCRIPTION PIN , delay â'¢ Q io to 0 1 7 . 2-line delay , CMOS process technology. It allows sim ultaneous output of 1-line delay data and 2-line delay data , ', the contents of data inputs Do to D7 are written into 1-line delay data only memory in syn , delay data only memory is inhibited and the write address counter of 1-line delay data only memory is -
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66257FP
Abstract: Leading Edge Delay SPD2 0 15 ns programmable from 0 to 15 ns in 1 ns steps Line Timing (See Fig. 15 & 16 , overdriving the CDS input. When the "RST pulse" bit is low, the switches are always on. Pipe Line Delay , edge of SBLK, if SBLK pol=1). "SBLK delay 1" adds delay to the end of the ADC track time. The digital output pins, DB[11:0], change after the trailing edge of SPIX. "SPIX delay 1" adds delay to the digital , completed (approximately 10ns delay). Digital Output Bus Over, DB[11:0] ? s> ? ? T DVDD o â'¢rfH T -
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XRD98L61 XRD98L61AIV CA94538 DB10 schematic diagram of aoc monitor
Abstract: to change w ith o u t notice. SAD7630 _ TIME BASE CORRECTION DELAY LINE (TBC) G EN ERA L DESCRIPTION The SAD7630 is a charge-coupled device (CCD) dual variable delay line. It is , ground external clock input digital ground Fig. 1 Block diagram. Time base correction delay , registers form one delay line. Each register is clocked by two clock pulses and ip2 which have a phase , V| VO lM 'OM >SS IDD ^tot Ü) < / ) 1 - Tamb Time base correction delay line (TBC) SAD7630 -
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tbc ccd 7Z24446
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