500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Direct from the Manufacturer

Part Manufacturer Description PDF & SAMPLES
CS4335-KSZR Cirrus Logic D/A Converter, 24-Bit, 2 Func, Bipolar, PDSO8
CS4339-KSZR Cirrus Logic D/A Converter, 24-Bit, 2 Func, Bipolar, PDSO8
CS4344-DZZ Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PDSO10, 3 MM, PLASTIC, MO-187, TSSOP-10
CS4350-DZZR Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PDSO24, 4.40 MM, LEAD FREE, MO-153, TSSOP-24
CS4365-CQZR Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PQFP48, LEAD FREE, MS-022, LQFP-48

"Data Conversion"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: mode after the A/D conversion ends: (1) Reading A/D conversion data, (2) Clearing interrupt factors, (3) Starting the next A/D conversion. *1 Data protection function: When the A/D conversion is consecutively executed, if the process to read the A/D conversion result (data register) is not executed until , read the A/D conversion result (data register) is not executed until the next A/D conversion ends, the , flag is cleared, an unnecessary A/D conversion completion interrupt occurs and dummy data is acquired Fujitsu
Original
MB90F038 MB90F038S MB90F367 MB90F0 ADRX MB90823 CI-300003-E-V11-16LX F2MC-16LX 16-BIT MB90340 MB90350 MB90360
Abstract: reference voltages (ANA1 to 5). · Make the microcontroller retain the conversion result as correction data , correction data and correct the conversion result. These operations are executed by using conversion A , point of temperature correction data is measured before starting A/D conversion. The inclination of , in the 5-point correction data (code1) measured immediately after conversion A2 mode has been , identification Stop processing Temperature correction data (code1') measurement A/D conversion processing 5 NEC
Original
DAC-IC DAC-IC 0-5 output voltage P153 P151 P150 P142 G0706
Abstract: easily, and also serial data can be managed. â'¢ Conversion Mode Selectable: A to D or D to A â'¢ High , interrupt request as conversion completion â'¢ Serial Data Port Available â'¢ On-chip Sample and Hold , . Aim 26 Analog Input for A/D Conversion: During STRT = H, this input data is sampled. During D/A , 1 to 16 Parallel Data Input/Output: Can transmit A/D conversion data output or D/A conversion data , the completion of previous conversion. RD 3B Data Read Input: When RD is low, the stored data in -
OCR Scan
MB87020 LT 7232 LT 7238 LC 7258 cd 7231 MB87064 DIP-40P-M01 27-SAMPLING 28-SAMPLING 30-SIGNAL 40-LEAD
Abstract: A/D conversion are stored in 16-bit data registers corresponding to the respective input channels , Group A/D Conversion in Single-cycle Scan Mode · The A/D data registers (ADDRm and ADDRn) are 16 , conversion on all the channels (0 to 3), the converted data are stored in bits 15 to 6 of the corresponding , ADST A/D converter Standby A/D conversion Standby ADF A/Dconverted data (AN0 , ) (6) (8) Third round of A/D conversion A/Dconverted data (AN1) Second round of A/D Renesas Technology
Original
R5F70865 SH7080 SH7086 REJ06B0699-0100/R
Abstract: ) Data of ADDR0 1st conversion data 2 bytes Data of ADDR1 2 bytes Data of ADDR2 2 bytes Data of ADDR3 Data of ADDR0 A/D data registers 0 to 3 (ADDR0 to ADDR3) 2nd conversion data Data of ADDR1 Data of ADDR2 2 bytes for each Data of ADDR3 Data of ADDR0 3rd conversion data , results of conversion for the corresponding analog input channels. The converted data is stored in bits , conversion on analog input channels 0, 1, 2, 3 in this order. Store A/D-converted data to ADDR registers Renesas Technology
Original
SH7145 SH7145F REJ06B0391-0100Z/R
Abstract: .7 Representation of conversion data , for triggering, data handling and storage. The conversion result handling is shown in Figure 2 , read. Figure 5 Result data valid flag checking In the above example, channel 0 conversion is , correct data has been read for the conversion requested through a particular channel (incase same result , Channel number bitfield of result register for the latest data 2.1 Representation of conversion data Infineon Technologies
Original
AP16155 memtool C166 XC2267 XE166 c166 memtool C166 XC2000/XE166
Abstract: ) Data of ADDR0 1st conversion data 2 bytes Data of ADDR1 2 bytes Data of ADDR2 2 bytes Data of ADDR3 Data of ADDR0 A/D data registers 0 to 3 (ADDR0 to ADDR3) 2nd conversion data Data of ADDR1 Data of ADDR2 2 bytes for each Data of ADDR3 Data of ADDR0 3rd conversion data , conversion for the corresponding analog input channels. The converted data is stored in bits 15 to 6 of ADDR , order. Store A/D-converted data to ADDR registers. Set the ADF flag to 1 when A/D conversion for all Renesas Technology
Original
addr3 REJ06B0390-0100Z/R
Abstract: format. Consequently, endianess conversion is required for certain data transfers between these two , is called endianess conversion. 1.1 Data Accesses in Mixed-Endian Systems In this section, the , big-endian processor accessing data stored in little-endian format. Whether endianess conversion is , of these conditions are met, endianess conversion is required. The effect of using different data access sizes on the required endianess conversion can be demonstrated using a data item stored as a 32 Texas Instruments
Original
OMAP5910 TI925T C55X omap1610 0x34127856 OMAP1510 SWPA027 OMAP5910TM TI925TTM TMS320C55
Abstract: channels 0 to 3 (AN0 to AN3). Converted data are stored in the on-chip RAM. Since A/D conversion is in , bytes ADDR2 data 2 bytes ADDR3 data Three rounds of consecutive conversion A/D data registers , data ADDR3 data Figure 1 Overview of A/D Conversion REJ06B0698-0100/Rev.1.00 January 2008 , conversion repeated on up to 4 channels for the SH7083/84/85 or up to 8 channels for the SH7086 Data register Results of A/D conversion are stored in 16-bit data registers corresponding to the respective Renesas Technology
Original
REJ06B0698-0100/R
Abstract: the previous conversion using the internal serial clock; a HIGH input here will transmit serial data , hold state and starts a conversion. With CS LOW, a rising edge on R/C enables the output data bits if , conversion. With R/C HIGH, a falling edge on CS will enable the output data bits if PAR/SER HIGH, or starts , conversion is started; remains LOW until the conversion is completed and the data is latched into the output , be used to latch the data. 25 CONTC I Continuous Conversion Input. If LOW, conversions Burr-Brown
Original
ADS7825 ADS7824 ADS7825P ADS7825PB ADS7825U ADS7825UB 12-BIT 28-PIN
Abstract: input here will transmit serial data on SDATA from the previous conversion using the internal serial , edge on CS will initiate a conversion. With R/C HIGH, a falling edge on CS will enable the output data , Output. Falls when conversion is started; remains LOW until the conversion is completed and the data is , that the rising edge can be used to latch the data. Continuous Conversion Input. If LOW, conversions , initiate a conversion and output valid data from the previous conversion on SDATA (pin 16) synchronized to Burr-Brown
Original
Abstract: ] [Variables] ad_port_set, ad_set, ad_start, ad_stop unsigned short int buf [ ]: Conversion data storing , ] Stores A/D conversion result data to buffer. [SFR used] AD0CR0 [call function] None [Variable] unsigned short int buf [ ]: A/D0 conversion result register 0 Convert data storing , ] ad_port_set, ad_set, ad_start, ad_stop unsigned short int buf[ ]: Conversion data storing buffer unsigned short int buf_1[ ]: Conversion data storing buffer unsigned short int buf NEC
Original
PD70F3452 PD70F3454 uPD70F3451 uPD70F3453
Abstract: the previous conversion using the internal serial clock; a HIGH input here will transmit serial data , hold state and starts a conversion. With CS LOW, a rising edge on R/C enables the output data bits if , conversion. With R/C HIGH, a falling edge on CS will enable the output data bits if PAR/SER HIGH, or starts , conversion is started; remains LOW until the conversion is completed and the data is latched into the output , be used to latch the data. 25 CONTC I Continuous Conversion Input. If LOW, conversions Burr-Brown
Original
ADS7824P ADS7824PB ADS7824U ADS7824UB
Abstract: the previous conversion using the internal serial clock; a HIGH input here will transmit serial data , hold state and starts a conversion. With CS LOW, a rising edge on R/C enables the output data bits if , conversion. With R/C HIGH, a falling edge on CS will enable the output data bits if PAR/SER HIGH, or starts , conversion is started; remains LOW until the conversion is completed and the data is latched into the output , be used to latch the data. 25 CONTC I Continuous Conversion Input. If LOW, conversions Burr-Brown
Original
Abstract: into the hold state and starts a conversion. With CS LOW, a rising edge on R/C enables the output data , will initiate a conversion. With R/C HIGH, a falling edge on CS will enable the output data bits if , conversion and output valid data from the previous conversion on SDATA (pin 16) synchronized to 12 clock , conversion â'˜nâ'™, serial data from conversion â'˜n â'" 1â'™ will be output on SDATA (pin 16) following the start of conversion â'˜nâ'™. See Internal Data Clock in the Reading Data section. To reduce the Burr-Brown
Original
Abstract: and the converted data is saved into the RAM area. A/D conversion operation is stopped after the same , converted data. Furthermore, power consumption can be reduced by stopping A/D conversion operation when , Setting the analog input channel to ANI0 Reading the 10-bit A/D conversion data Wait of 4 clocks Adding the A/D conversion data read Starting A/D conversion operation Clearing the INTAD , conversion data Number of additions < 4 Setting the next address to be read Number of additions = 4 NEC
Original
LIB78K0S a006
Abstract: remaining bits in order. The 3-state serial output for the A/D conversion result. DATA OUT is in the , conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the , conversion is complete and the data is ready for transfer. Ground. GND is the ground return terminal for the , bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4 , 1100 DATA INPUT = 1101 t(conv) Conversion time See Figure 9 - Figure 14 See Figure 9 - Figure 14 and Texas Instruments
Original
TLC2543Q1 12BIT SGLS218C AEC-Q100 AIN10 TLC2543
Abstract: remaining bits in order. The 3-state serial output for the A/D conversion result. DATA OUT is in the , conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the , conversion is complete and the data is ready for transfer. Ground. GND is the ground return terminal for the , bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4 , 1100 DATA INPUT = 1101 t(conv) Conversion time See Figure 9 - Figure 14 See Figure 9 - Figure 14 and Texas Instruments
Original
Abstract: the previous conversion using the internal serial clock; a HIGH input here will transmit serial data , hold state and starts a conversion. With CS LOW, a rising edge on R/C enables the output data bits if , conversion. With R/C HIGH, a falling edge on CS will enable the output data bits if PAR/SER HIGH, or starts , conversion is started; remains LOW until the conversion is completed and the data is latched into the output , be used to latch the data. 25 CONTC I Continuous Conversion Input. If LOW, conversions Burr-Brown
Original
Abstract: into the hold state and starts a conversion. With CS LOW, a rising edge on R/C enables the output data , will initiate a conversion. With R/C HIGH, a falling edge on CS will enable the output data bits if , conversion and output valid data from the previous conversion on SDATA (pin 16) synchronized to 12 clock , conversion â'˜nâ'™, serial data from conversion â'˜n â'" 1â'™ will be output on SDATA (pin 16) following the start of conversion â'˜nâ'™. See Internal Data Clock in the Reading Data section. To reduce the Burr-Brown
Original
ISO/TS16949
Showing first 20 results.