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FLINK3V10BT-TX Texas Instruments Evaluation board for DS90C3201 Dual Pixel FPD- Link Serializer
FLINK3V10BT-RX Texas Instruments Evaluation board for DS90C3202 Dual Pixel FPD- Link Deserializer
TC213-50 Texas Instruments 1024- X 512-Pixel CCD Image Sensor 24-CDIP SB
TC213-30 Texas Instruments 1024- X 512-Pixel CCD Image Sensor 24-CDIP SB
HIP1013CB Intersil Corporation DUAL SWITCHING CONTROLLER, PDSO14
EL7232CS Intersil Corporation DUAL LINE DRIVER, PDSO8

"DUAL pixel"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Te x a s DS90C187 In s tr u m e n ts Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer , Serializer is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA 2048x1536@60Hz resolutions. The transmitter con­ verts up to 48 bits (Dual Pixel 24 bit color , to one channel of 4D+C LVDS data stream. In single pixel in / dual pixel out mode, the device can , pixel clock rate. In dual pixel in / dual pixel out mode, the device can drive up to QXGA -
OCR Scan
Abstract: DS90C187 Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer April 25, 2012 DS90C187 Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer General Description The DS90C187 is a Low Power , host GPU and the Display. The DS90C187 Serializer is designed to support dual pixel data transmission , 48 bits (Dual Pixel 24 bit color) of 1.8V LVCMOS data into two channels of 4 data + clock (4D , converts one bank of 24 bit RGB data to one channel of 4D+C LVDS data stream. In single pixel in / dual Texas Instruments
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LVDS display tcon old ferrite ER6 SIZE AN-1187 AN-1108 AN-905 LFA92A
Abstract: DS90C187 Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer April 25, 2012 DS90C187 Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer General Description The DS90C187 is a Low Power , host GPU and the Display. The DS90C187 Serializer is designed to support dual pixel data transmission , 48 bits (Dual Pixel 24 bit color) of 1.8V LVCMOS data into two channels of 4 data + clock (4D , converts one bank of 24 bit RGB data to one channel of 4D+C LVDS data stream. In single pixel in / dual Texas Instruments
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T-CON BOARD diagrams B27 QFN INA27 lcd 7" 18-bit digital lvds switch tcon with lvds input
Abstract: monochrome LCD, EL, Plasma and Color TFT LCD panels. The panel types supported are: Dual panel-Double drive (DD) - 8 pixels/clock, 1 bit/pixel Dual panel-Single drive (PS) -1 pixel/clock, 6 bits/pixel - 2 , panel-Single drive (DS) Dual panel-Double drive (DD) Flat Panel Pixel Timing The 65525 can be programmed , = 11 2) Dual Panel-Single Drive 640x480 Monochrome LCD Panel 4 pixels/shift clock, 2 bits/pixel CD = , ·UH M · IHM H · ·· ·····MM · ·· ··· · m u n ir a Flat Panel Pixel Timing This section -
OCR Scan
plasma 640x480
Abstract: DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA PRELIMINARY September 1999 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color , tolerance of 300ps n Dual pixel architecture supports interface to GUI and timing controller; optional National Semiconductor
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112MH 170MH
Abstract: July 2000 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data , (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data , intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total , time of pair-to-pair skew at receiver inputs; intra-pair skew tolerance of 300ps n Dual pixel National Semiconductor
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FLM G12 AN-1059 DS90C387 DS90CF388 Programmable LVDS Receiver 24-Bit RGB
Abstract: In, Single Pixel Out (SISO), 105MHz max ­ Single Pixel In, Dual Pixel Out (SIDO), 185MHz ­ Dual Pixel In, Dual Pixel Out (DIDO), 105MHz Supports 24 bit RGB, 48 bit RGB Optional low power mode supports 18 , the Display. The DS90C187 Serializer is designed to support dual pixel data transmission between Host , bits (Dual Pixel 24 bit color) of 1.8V LVCMOS data into two channels of 4 data + clock (4D+C) reduced , one bank of 24 bit RGB data to one channel of 4D+C LVDS data stream. In single pixel in / dual pixel Texas Instruments
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ina26 t-con lvds 24BPP 2560x2048 LVDS Serializer SNLS401B 105MH 185MH ISO/TS16949
Abstract: April 1999 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data , (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data , intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total , time of pair-to-pair skew at receiver inputs; intra-pair skew tolerance of 300ps n Dual pixel National Semiconductor
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Abstract: May 2000 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data , (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data , intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total , time of pair-to-pair skew at receiver inputs; intra-pair skew tolerance of 300ps n Dual pixel National Semiconductor
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Abstract: communicate with the host system. The dual high speed LVDS channels supports single pixel in-single pixel out, single pixel in-dual pixel out, and dual pixel in-dual pixel out transmission modes. The DS90C2501 , to 130 MHz clock in single pixel in to dual pixel out Support 24bit/48bit color TFT LCD with , DUAL VIM DUAL VIL DUAL High Level Input Voltage (for dual pixel in to dual pixel out). PD = VCC3V 2.0 , Level Input Voltage (for PD = VCC3V single pixel in to dual pixel out). High Level Input Voltage (for National Semiconductor
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dual pixel lvds scaler LVDS SNLS136G FPD8531 DS90CF364/ DS90CF384A/DS90CF384/DS90CF384A DS90C387R
Abstract: clock in single pixel in to single pixel out operation 50 to 130 MHz clock in single pixel in to dual , supports single pixel in-single pixel out, single pixel in-dual pixel out, and dual pixel in-dual pixel out , SPECIFICATIONS for DUAL pin, pin35 VIH DUAL High Level Input Voltage (for dual pixel in to dual pixel out) High Level Input Voltage (for single pixel in to dual pixel out) High Level Input Voltage (for single pixel , D0­D11 correspond to LVDS ports A0­A3. When DUAL pin = ½VCC, 1st pixel from D0­D11 corresponds to LVDS Texas Instruments
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E3-D10 SNLS136H TIA/EIA-644
Abstract: DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA PRELIMINARY November 2000 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color , pair-to-pair skew at receiver inputs; intra-pair skew tolerance of 300ps n Dual pixel architecture supports National Semiconductor
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AN-1163 DS90CF388VJD DS90CF388AVJD DS90CF388VJDX AN-1127
Abstract: November 2000 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA General Description Features The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel , 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling , blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a , ; intra-pair skew tolerance of 300ps n Dual pixel architecture supports interface to GUI and timing National Semiconductor
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Abstract: used to communicate with the host system. The dual high speed LVDS channels supports single pixel in-single pixel out, single pixel in-dual pixel out, and dual pixel in-dual pixel out transmission modes , single pixel in to dual pixel out operation. n Support 24bit/48bit color TFT LCD with Conventional and , VIH DUAL High Level Input Voltage (for dual pixel in to dual pixel out). PD = VCC3V VIM DUAL High Level Input Voltage (for single pixel in to dual pixel out). PD = VCC3V VIL DUAL National Semiconductor
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DS90CF364 FPD-link receiver chip IC A7p rgb 8 bit to lvds SCALER
Abstract: with the host system. The dual high speed LVDS channels supports single pixel insingle pixel out, single pixel in-dual pixel out, and dual pixel in-dual pixel out transmission modes. The DS90C2501 , single pixel in to dual pixel out operation. n Support 24bit/48bit color TFT LCD with Conventional and , Level Input Voltage (for dual pixel in to dual pixel out). PD = VCC3V VIM DUAL High Level Input Voltage (for single pixel in to dual pixel out). PD = VCC3V VIL DUAL High Level Input Voltage National Semiconductor
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CSP-9-111C2 CSP-9-111S2
Abstract: communicate with the host system. The dual high speed LVDS channels supports single pixel in-single pixel out, single pixel in-dual pixel out, and dual pixel in-dual pixel out transmission modes. The , pixel in to dual pixel out operation. n Support 24bit/48bit color TFT LCD with Conventional and , VIH DUAL High Level Input Voltage (for dual pixel in to dual pixel out). PD = VCC3V VIM DUAL High Level Input Voltage (for single pixel in to dual pixel out). PD = VCC3V VIL DUAL National Semiconductor
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DS90CF366 DS90CF364A scaler lcd 128pin
Abstract: . Dual Link mode may operate across a pixel frequency of 25 MHz to 330 MHz. Below 165 MHz, the second , automatically configure to either Single or Dual Link operation (two or one pixel per clock mode, respectively , is always configured for Dual Link (one pixel/clock) operation, by tying the S_D pin to HIGH. The , 165MHz. 0 Slave Dual Link Slave (One Pixel/Clock) Mode. This is the mode that the Slave receiver will always be in for pixel clock frequencies greater than 165MHz and less than 330MHz. 1 Master Dual Link Silicon Image
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SiI 163b dvi dual link schematic sata hot plug CIRCUIT diagram I-DS-0055-B I163BCTU I163BCT100
Abstract: ), this pin selects 1-pixel/clock mode (LOW) or 2pixel/clock mode (HIGH). When S_D pin is HIGH (Dual Link , Master receiver. Slave ­ The Slave receiver is always configured for Dual Link (one pixel/clock , pixel clock frequencies less than or equal to 165MHz. 0 Slave Dual Link Slave (One Pixel/Clock) Mode , 165MHz and less than 330MHz. 1 Master Dual Link Master (One Pixel/Clock) Mode. This is the mode that the Master receiver will be in when in Dual Link mode for pixel clock frequencies greater than 165MHz and Silicon Image
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DVI to vga CABLE CONNECTION DIAGRAM SiI-DS-0055-C SiI143 SiI-DS-0055-B 163B I-DS-0055-C I163BCTG100
Abstract: used to communicate with the host system. The dual high speed LVDS channels supports single pixel in-single pixel out, single pixel in-dual pixel out, and dual pixel in-dual pixel out transmission modes , single pixel in to dual pixel out operation. n Support 24bit/48bit color TFT LCD with Conventional and , VIH DUAL High Level Input Voltage (for dual pixel in to dual pixel out). PD = VCC3V VIM DUAL High Level Input Voltage (for single pixel in to dual pixel out). PD = VCC3V VIL DUAL National Semiconductor
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Abstract: CCD shift register Pixel array CCD shift register Dual side read method (1 output) CCD shift register Pixel array CCD shift register Dual side read method (2 outputs) Pixel array CCD , uPD3747D 2660 5000 5150 7400 200/B4 300/A4 400/A3 600/A4 600/A3 Pixel size , ) Pixel size (um) uPD8861CY*1 uPD3799CY uPD3798CY 5,400 x 3 5,400 x 3 5,300 x 3 5,348 , 44 (22 x 2) Dual side, 2 outputs Dual side, 1 output Dual side, 2 outputs 5 V single -
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nec CCD LINEAR IMAGE SENSOR CCD linear image sensor 22-pin scanner CCD linear array linear CCD-Sensor linear CCD 12 line ccd scanner PD3753CY PD3734ACY PD3739D PD3737D PD3747D PD3794CY
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