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DDR1327SDFC Tripp Lite TV DESK MNT
DDR1327NBMSC Tripp Lite TV DESK MNT
DDR1013SC Tripp Lite FULL-MOTION UNIVERSAL TABLET DES
DDR1326SD Tripp Lite TV DESK MNT
DDR1327S Tripp Lite TV DESK MNT
DDR1327DCS Tripp Lite TV DESK MNT

"DDR1 SDRAM"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: RapidReadyTM DDR-1 SDRAM Physical Layer Core (CW761041 & CW000722) OVERVIEW FEATURES LSI , . RapidChip Platform ASIC DDR-I SDRAM DDR-1 PHY-Core DDR-1 Controller (CW761030) Address/CMD , plug-nplay solution for the DDR-1 Memory RapidReadyTM DDR-1 SDRAM Physical Layer Core (CW761041 & , a complete DDR-1 SDRAM interface solution, enabling significant reductions in ASIC development , Office Locations www.lsilogic.com/contacts Figure 2. LSI Logic's RapidChip DDR-1 SDRAM PHY core LSI Logic
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ddr phy DDR PHY ASIC LSI Rapidchip g12 DDR lsi 166MH C20057
Abstract: DDR-SDRAM memory controller supports JEDEC-compatible DDR1 SDRAM memories up to 166 MHz (333 MHz data rate , controller and specifically JEDEC-compatible DDR1 SDRAM memories. Table 1 lists the devices covered in this , . Contents 1. DDR1 SDRAM Overview . . . . . . . . . . . . . . . . . . . . . 2 2. Software Considerations . , DDR1 SDRAM Overview 1 DDR1 SDRAM Overview During the 1990s, the PC market shifted towards , power consumption levels. Table 2 summarizes the main differences between DDR1 and SDRAM. Table 2 Freescale Semiconductor
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AN2583 MPC8540 MPC8349 MPC8560 MPC8347 MPC8343 BA 5810 MPC8548 uboot freescale mpc8313 MPC85xxEC mpc8379 MPC8560ADS MPC8555E1
Abstract: now uses DDR1 instead of SDRAM, which was used in the previous generation of Maxim's TDM over Packet , Maxim > Design Support > App Notes > T/E Carrier and Packetized > APP 5120 Keywords: DDR1, DDR3, jitter, buffer, TDMoP, TDM over packet, DDR, SDRAM, PDV, PSN, double data rate APPLICATION NOTE 5120 , uses an external double data rate (DDR) synchronous DRAM (or DDR1) device to buffer data. The memory , -port TDM-over-packet IC, uses an external double data rate (DDR) synchronous DRAM (also referred to as "DDR1") device Maxim Integrated Products
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DS34S132 MT41J128M8 AN5120 APP5120 micron ddr3 DDR3 timing diagram DDR3 model verilog codes Verilog DDR3 memory model micron memory model for ddr3
Abstract: DDR-SDRAM memory controller supports JEDEC-compliant DDR1 SDRAM memories up to 166 MHz (333 MHz data rate , controller and specifically JEDEC-compliant DDR1 SDRAM memories. Table 1 lists the devices covered in this , reserved. Contents 1 DDR1 SDRAM Overview . . . . . . . . . . . . . . . . . . . . . .2 2 Software , . . . . . .20 DDR1 SDRAM Overview 1 DDR1 SDRAM Overview During the 1990s, the PC market , at reduced power consumption levels. Table 2 summarizes the main differences between DDR1 and SDRAM Freescale Semiconductor
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MPC8555E MPC8541E MPC8568 MPC8558 001B mpc837
Abstract: to 24 GP I/Os DMA controller 32-bit PCI controller IIC controller 10/100 2 UARTs DDR1/2 SDRAM controller DDR1/2 SDRAM controller External Bus Master Interface External Bus Master Interface External Bus , PCIe PCIe Int Handler 100MHz Max. DDR1/2 SDRAM Controller HSS x1 HSS x1 4 External , and Bus Architecture On-Chip Peripheral Bus (OPB) · 32-bit DDR1/2 SDRAM controller with ECC , Controller PCIe PCIe Int Handler 100MHz Max. DDR1/2 SDRAM Controller HSS x1 4 External Channels Applied Micro Circuits
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PPC460EX PPC440EPx-SUA667T SGMII PCIE bridge powerpc 464 PPC460SX ppc460 460SX 10/100/1G 32KI/32KD 256KB 440GX 440SP
Abstract: DDR1 & DDR2 SDRAM Controller IP Cores User's Guide August 2010 ipug35_04.7 Table of , SDRAM devices and modules · High-performance DDR1 400/333/266/200/133 operation for LatticeECP3 , change without notice. IPUG35_4.7, August 2010 2 DDR1 & DDR2 IP Cores User's Guide Lattice , . 49 IPUG35_4.7, August 2010 3 DDR1 & DDR2 IP Cores User's Guide Lattice Semiconductor , . 55 IPUG35_4.7, August 2010 4 DDR1 & DDR2 IP Cores User's Guide Chapter 1 Lattice Semiconductor
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modelsim 6.3f LFXP2-5E-5TN144C LFE3-17E-6FN484CES LFE3-17EA6FN484C LFE3-17EA LFE3-17E- LFSC3GA25E-6F900C
Abstract: IBM Title Page DDR1/2 MC (16/32b) to PLB4 (DDR2MC1632B2PLB4) Functional Specification SA14 , www.ibm.com/chips SA14-2759-07 March 15, 2010 IBM Functional Specification Revision 6 DDR1/2 MC , physical design requirements, and the performance and operating environment of the DDR1/2 MC (16/32b) to , for hardware, software, and application developers who need to understand the DDR1/2 MC (16/32b) to , March 15, 2010 Revision 7 Updated Section 3.1.4.12 SDRAM Timing Register 1 (SDRAMx_SDTR1). IBM
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SA14-2759-06 SA14-2759-05 dram verilog model vhdl code for memory controller for mic 0x29 plb4
Abstract: 4Mx16 SDRAM 4Mx16 SDRAM 2Mx32 128Mb DDR1 SDRAM 8Mx16 2.5V 256Mb DDR1 SDRAM 16Mx16 2.5V SRAM Low , ~3.6 Volts SRAM 128Kx8, 2.5~3.6 Volts SRAM 256KX8, 2.5~3.6 Volts 128Mb DDR1 SDRAM 8Mx16 2.5V 256Mb DDR1 SDRAM 16Mx16 2.5V DRAM EDO 1Mx16, 3.3V, 1K refresh SDRAM 1Mx16, 166Mhz SDRAM 8Mx16 SDRAM 16Mx , Description SDRAM 2Mx32 SDRAM 2Mx32 SDRAM 2Mx32 256Mb DDR1 SDRAM 16Mx16 2.5V 128Mb DDR1 SDRAM 8Mx16 2.5V , SDRAM 4Mx16 SDRAM 8Mx16 SDRAM 8Mx16 SDRAM 4M x 32 SDRAM 4M x 32 256Mb DDR1 SDRAM 16Mx16 2.5V SRAM AMIC Technology
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um61256 hynix hy57v281620 hy57v641620 cross reference UM611024 WINBOND Serial flash cross reference 256k x8 SRAM PD4218165 PD424260 PD431000A PD43256B PD441000L-B PD442000L-B
Abstract: integration DDR1/2 SDRAM DDR1/2 SDRAM DDR1/2 SDRAM DDR1/2 SDRAM DDR1/2 SDRAM x64/x72 FPGA/ASIC , SDRAM MCPs Size 1GB 1GB 2GB 4GB Organization 128M x 64 128M x 72 256M x 72 512M x 72 Part , 22mm 13mm x 22mm 14mm x 17mm 14mm x 17mm C, I, M C, I, M C, I, M C, I, M DDR2 SDRAM MCPs , 128M x 72 128M x 64 Registered DDR2 SDRAM MCPs Size Organization Part Number 1GB 128M x 72 W3H128M72ER-XNBX DDR SDRAM MCPs Size 128MB 128MB 128MB 128MB 256MB 256MB 256MB White Electronic Designs
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W3J128M64G-XPBX W3J128M72G-XPBX W3J2256M72-XPBX W3H32M64E-XSBX W3H32M72E-XSB2X W3H128M72E-XSBX DDR1 512M 256mb EEPROM Memory W3H128M72 W3J256M72G-XPBX
Abstract: 4KB · DDR1/2 · External SDRAM controller Bus controller Flash controller · DDR1/2 · External , Bus Architecture · 32-bit DDR1/2 SDRAM controller with ECC, supports both x16 or x32, up to 2GB memory , Purpose processing 16/32-bit w/ECC 1 Lane PCI Express 1 Lane PCI Express DDR1/2 SDRAM Controller PCIe , 32-bit DDR1/2 SDRAM controller with ECC, supports both x16 or x32, up to 2GB memory bank · External , processing 16/32-bit w/ECC 1 Lane PCI Express DDR1/2 SDRAM Controller PCIe PCIe Int Handler DMA Applied Micro Circuits
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PPC460GT-SUB1000T PPC460EX-SUB1000T PPC440EP-3JC533C PPC460GT PPC440EPX-NUA400T PPC440GX-3RF533C 405EP 405EX 405GP 440EP 440GP 460EX
Abstract: Agilent U7233A DDR1 Compliance Test Application with LPDDR and mobile-DDR Support for Infiniium Series Oscilloscopes Data Sheet Test, debug and characterize your DDR1 designs quickly and easily The Agilent Technologies U7233A DDR1 compliance test application provides a fast and easy way to test, debug and characterize your DDR1 designs. The tests performed by the U7233A software are based on the JEDEC1 JESD79E Double Data Rate (DDR) SDRAM Specification and JESD209A Low Power Double Agilent Technologies
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ddr ram repair JESD209 DDR1 Ram Jedec JESD209 E2678A DDR 2 RAM REPAIR 5989-7366EN
Abstract: frequency. The figure below shows a simple DDR1 SDRAM architecture example. Figure 2. DDR1 SDRAM , external DDR SDRAM Introduction The SPEAr600 embedded MPU features a multi-port memory controller for , . . . . . . . . . . . . . . . . . . . . . 5 2.1 DDR2 vs. DDR1 . . . . . . . . . . . . . . . . . , used for interfacing DDR (double data rate) synchronous dynamic RAM (SDRAM). It is also responsible , of the SPEAr600, showing the connections between the SDRAM controller AHB data ports (M0,.,M6) and STMicroelectronics
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AN3132 DDR2 pcb layout DDR1 pcb layout MT47H64M16-3 DDR2 sdram pcb layout guidelines ddr2 ram slot pin detail MT47H64M16* pcb
Abstract: 7 8 9 10 Swissbit AG SDRAM DDR1 184 Pin unbuffered 2.6V Depth (1GB) Width PCB-Type , Data Sheet Rev. 1.0 SDU12872H1BF2MT-50R 07-Apr-08 184-pin DDR1 PC3200 ECC DDR-SDRAM , -bit DDR1 Dual In-line Memory Module for desktop applications. DDR1-400 3.0-3-3 (CL-tRCD-tRP), 64Mx8 , and functional compatible to the JEDEC DDR1 specifications (www.jedec.org) 5.250 ( 133.35 ) â , AG Industriestrasse 4 - 8 CH-9552 Bronschhofen, Switzerland Parts DDR SDRAM, 2.5V, TSOP 400mil Swissbit
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DDR400 DDR1-400 1GB-DDR400PC3200-333 MT46V64M8P-5B MT-50R 512MB
Abstract: SDRAM DDR1/2 SDRAM DDR1/2 SDRAM DDR1/2 SDRAM DDR1/2 SDRAM Data I/O Control , SDRAM MCPs Size 1GB 1GB 1GB 1GB Organization 256M x 32 128M x 64 128M x 72 2 x 256M x 16 , DDR2 SDRAM MCPs Size 256MB 256MB 512MB 512MB 1GB 1GB Organization 32M x 64 32M x 72 64M x 64 64M x 72 128M x 72 128M x 64 Registered DDR2 SDRAM MCPs Size 1GB Organization 128M x 72 DDR SDRAM MCPs Size 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 512MB White Electronic Designs
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W3J128M72G-XNBX ddr sram 256mb w3j128m72 DDR2 128M x 32 NAND Flash Qualification Reliability 2.5 pata W3J256M32G-XNBX W3J128M64G-XNBX W3J2256M16G-XNBX W3H64M64E-XSBX W3H64M72E-XSBX
Abstract: synchronous one. The majority of memory makers now use Synchronous Dynamic Random Access Memory (SDRAM). What was once only considered as an interim technology, SDRAM has made a significant impact on the , PC100/133 DDR1 DDR2 Clock Frequency 100 / 133 100 / 133 / 166 / 200 200 / 266 / 333 , from DDR1. The first and most obvious feature is higher operating frequency while operating at lower supply voltage. With an initial clock speed of 400MHz, it continued where DDR1 has left off. With that Pericom Semiconductor
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JESD65-A SO-DIMM 100-pin dimm 240 pin 100-pin dimm ELPIDA PC2700 PC25300 PC100 PC133 100MH 133MH PC2-3200/PC24300 PC2700
Abstract: , but the data bus effectively doubles in frequency. The figure below shows a simple DDR1 SDRAM architecture example. Figure 2. DDR1 SDRAM architecture In general, a DRAM (non synchronous) address is , external DDR SDRAM Introduction The SPEAr3xx embedded MPU family (SPEAr300, SPEAr310 and SPEAr320 , vs. DDR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , for interfacing DDR (double data rate) synchronous dynamic RAM (SDRAM). It is also responsible for STMicroelectronics
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pcb layout design mobile DDR SPEAr310 ddr2 ram ddr pcb layout ARM926E SPEAr3* AN2674 AN3100
Abstract: 1 GigaBit Stacked DDR1 SDRAM DD54E, DD54ER Features 256M x 4 · Low Profile 66 Ball Two-High , T37Z 128M x 4 DDR1 SDRAM Layer 2 Layer 1 DQ[0:3] DQS VCI reserves the right to change , DDR SDRAM during READs and by the memory controller during WRITEs. The DDR SDRAM operates from a , registered on the positive going edge of CK. Read and Write accesses to the DDR SDRAM are burst oriented , bit) high speed DDR1 Double Data Rate Synchronous DRAM organized as 4 banks x 64M x 4 bits in a 66 Vertical Circuits
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DD256M T37Z TSOP 66 Package thermal resistance DD256M42U3BA
Abstract: slaves and external bus, UARTs, and devices on the EBC · DDR1/2 SDRAM interface operating up to 400 , . . . . . . . . 10 DDR1/2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Supply Requirements with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 , . . . . . . . . . . 49 Table 13. DC Power Supply Loads with DDR1 SDRAM . . . . . . . . . . . . . . , Processor Local Bus (PLB4)-128 bits Arbiter DDR1/2 SDRAM Controller EIP-94 Security Feature Applied Micro Circuits
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GCM-AES-128 power pc 460ex PPC405EX-SSA667T 16750 UART MACsec powerpc 405 333MH 667MH 200MH
Abstract: % 20% Feature/Category DDR1 DDR2 DDR3 Package TSOP BGA only BGA only , Feature/Category DDR1 DDR2 DDR3 Burst Length BL= 2, 4, 8 (2-bit prefetch) BL= 4, 8 (4 , bank at any given time â' DDR1 â'¢ Concurrency â' Can be opening or precharging a row in , '¢ Supports most JEDEC standard x8, x16, x32 DDR1 & 2 & 3 devices Memory device densities from 64Mb â'" through 4Gb Data rates up to: 333 Mb/s for DDR1, 800 Mb/s for DDR2 and 1600 Mb/s DDR3 Devices with Freescale Semiconductor
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jesd79-3d T1040
Abstract: SDRAM Controller Coherency Module A OpenPIC 32 KB I-Cache DM Local Bus 32 KB , GHz 1.2, 1.33 GHz 1.2, 1.0 GHz 800M, 1 GHZ for battery-backed 64-bit DDR1/2 scaling to , rate, 64-bit PCI-X, 4-bit PCI Key Advantages 512 KB 512 KB 512 KB 256 KB DDR1/DDR2/ FCRAM1/FCRAM2 DDR1/DDR2 DDR1/DDR2 DDR1/DDR2 Integrated Security Engine Yes Yes Yes , x8 Serial RapidIO® x4 - features include 512 KB L2 cache, 64-bit DDR1/2 scaling up to Freescale Semiconductor
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MPC8548FS MPC8548 tsec MPC8545 MPC8547 MPC8548 dhrystone powerpc dhrystone MPC8548/E
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