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Part Manufacturer Description PDF & SAMPLES
CS61584A-IL3 Cirrus Logic PCM Transceiver, 2-Func, CMOS, PQCC68, PLASTIC, MS-047, LCC-68
5962-89620012A Intersil Corporation 1 CHANNEL, VIDEO AMPLIFIER, CQCC20, CERAMIC, LCC-20
CS80C86-2 Intersil Corporation 16-BIT, 8MHz, MICROPROCESSOR, PQCC44, PLASTIC, LCC-44
84065023A Intersil Corporation 3 TIMER(S), PROGRAMMABLE TIMER, CQCC28, CERAMIC, LCC-28
HA4-5002/883 Intersil Corporation BUFFER AMPLIFIER, CQCC20, CERAMIC, LCC-20
HI4P0539-5 Intersil Corporation 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PQCC20, PLASTIC, LCC-20

"D J Z" LCC

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: D,T,S LCC C LDCC J DIP D,S,T LCC C LDCC J DIP K,S,T LCC C,Z LDCC J DIP D,P,S,T LCC C LDCC J DIP D,P,S,T LCC C LDCC J DIP D,T LCC C LDCC J,L DIP D,T LCC C LDCC J,L DIP D,T LCC C LDCC J,L DIP D,P,Y LCC C,Z LDCC J DIP K,S,T DIP D,P,Y LCC C,Z LDCC J , DIP D LCC C LDCC J DIP D LCC C DIP D LCC C LDCC J DIP D LCC C LDCC L,J DIP D LCC C LDCC L DIP D,P,T LCC C LDCC J,L DIP D,P,T LCC C LDCC L,J DIP D,P,T LCC C WaferScale Integration
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57C43B 57C45 57C49B 57C51B 57C71C 57C191B 57C256f WSI 57C191C 57C64F 57C291B magicpro III 57C43C 57C49C
Abstract: , D4 ), S O J (J 4 ), SOIC (S 4 ) TOP VIEW See Selection Guide Page for LCC j t p M eans , -Pin 300 mil DIP, SOIC, SOJ - 24-Pin Rectangular LCC (300 x 400 mils) - 28-Pin Square LCC (450 x 450 mils , nanoseconds are available, The P4C116 is also available in 24-pin rectangular and 28-pin square LCC , A, C 2 a2 c 3 23 c 4 J A10 22 3 a 9 21 H WE c 5 20 3 OÃ' 5 C 6 Ag C 7 , M BIT â  47 . P4C116 j * - MAXIMUM RATINGS*1 â -
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5L28M
Abstract: . P Plastic DIP S Plastic SOIC J Plastic SOJ D Ceramic DIP L Ceramic LCC (300 x 400 mils) 24 Id , Pinout (JEDEC Approved) - 24-Pin 300 mil DIP, SOIC, SOJ - 24-Pin Rectangular LCC (300 x 400 mils) - 28-Pin Square LCC (450 x 450 mils) -DESCRIPTION The , oper ate from a single 5V±10% tolerance power supply. Cur rent drain is typically 10 |j A from a 2.0V , densities. The P4C116 is also available In 24-pin rectangular and 28-pin square LCC packages -
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SMD-5962-89690
Abstract: Surface Mount Package Options â'¢ Ceramic DIP, 400 mils Wide, No. 101 â'¢ 28 Pad Ceramic LCC, No 76 â , Recommended DC Operating Conditions - r U j Absolute Maximum Ratings* Vollage on any pin relative to V S S , Junction Temperature, T J . 175°C Sym VIL -0.3 - , Max Unit LCC Address Lines Data Lines CSOJ, DIP Cl 6 12 PF CD/Q 8 14 , ) : I AVEL T ^ .* J . i TELEH : 7 m f TEHAX TAVEH -
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256KX4 EDI84256CS EDI84256LPS MIL-STD-883 EDI84256CS25LB EDI84256LPS25LB
Abstract: 8M Hz System Clock) 24J vcc 23J X1 S J X2 aT] ASYNC CSYNC [7 RDY1 READY 2Ã"| EF1 t . %j>: v 19] F /C is] ose 1 7 ] RES ,« * E [T CLK50 Q Ã" START [ÃT Ã'n d 16 , -Lin e or 2 8 Pad Square LCC Package Options â'¢ Single 5V Power Supply . -5 5 ° C t o + , 1- 1_ L. ! . 1 4 J< L 3 J> 1 2 J* 1 l_l l_ J u s. 1 ! i2& L . J *2& > »27* R i a ! s , à f i r i ! NC NC j j ] . \ [1 ST For static system designs, separate signals are -
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43DES71 82C85/883
Abstract: Approved) ­ 24-Pin 300 mil DIP, SOIC, SOJ ­ 24-Pin Solder Seal Flat Pack ­ 24-Pin Rectangular LCC (300 x 400 mils) ­ 28-Pin Square LCC (450 x 450 mils) ­ 32-Pin Rectangular LCC (450 x 550 mils) ­ 40-Pin Square LCC (480 x 480 mils) Low Power Operation Output Enable Control Function Single 5V±10% Power , SOIC packages, a solder seal flatpack and 4 different LCC packages (24, 28, 32, and 40 pin). DIP (P4, C4), SOJ (J4), SOIC (S4) SOLDER SEAL FLAT PACK (FS-1) SIMILAR LCC configurations at end of Pyramid Semiconductor
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P4C116L 25L40 P4C116/P4C116L SRAM110
Abstract: -Pin Rectangular LCC (300 x 400 mils) â'" 28-Pin Square LCC (450 x 450 mils) â'" 32-Pin Rectangular LCC (450 x 550 mils) â'" 40-Pin Square LCC (480 x 480 mils) Low Power Operation Output Enable Control , LCC packages (24, 28, 32, and 40 pin). DIP (P4, C4), SOJ (J4), SOIC (S4) SOLDER SEAL FLAT PACK (FS-1) SIMILAR LCC configurations at end of datasheet 1 P4C116/P4C116L MAXIMUM RATINGS(1) Symbol , P4C116/P4C116L LCC PIN CONFIGURATIONS 24-Pin LCC (L8) 28-Pin LCC (L5-1) 32-Pin LCC (L6) 40 Pyramid Semiconductor
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Abstract: DIP, SOIC, SOJ ­ 24-Pin Solder Seal Flat Pack ­ 24-Pin Rectangular LCC (300 x 400 mils) ­ 28-Pin Square LCC (450 x 450 mils) ­ 32-Pin Rectangular LCC (450 x 550 mils) ­ 40-Pin Square LCC (480 x 480 mils , mil DIP, SOJ and SOIC packages, a solder seal flatpack and 4 different LCC packages (24, 28, 32, and , ) SOLDER SEAL FLAT PACK (FS-1) SIMILAR LCC configurations at end of datasheet 1 P4C116/P4C116L , series with DOUT to match 166 (Thevenin Resistance). 6 P4C116/P4C116L LCC PIN CONFIGURATIONS Pyramid Semiconductor
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Abstract: resistance from junction to case is denoted by JC , and defined by JC = ( T j ­ T c ) / P d ; here, T c , temperature and maximum power dissipation can be calculated using the same equation in different forms: T j , operation. P d = ( T j ­ T a ) / JA . Values for JA are available for most packages. However, JC and , denoted by JA , and defined by JA = ( T j ­ T a ) / P d , where: · T j is the junction temperature of , JLDCC 68 46/38/32 36/27/19 35/26/20 JLDCC 84 47/37/32 33/26/22 30/26/18 LCC 28 -
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tqfp 44 thermal resistance tqfp 64 thermal resistance CPGA MQUAD PQFP-128 CQFP 240
Abstract: ?B78B; 37I> J?=>J 7D: , LEBJe` >SWLV2 0>; C7Ne 7BBEM78B; LEBJ7=; ?D J>; u+{} vs0s ?I 9E?B EL;H:H?L; LEBJ7=;c ?J ?I J>; ?DIJ7DJ7D;EKI C7Ne LEBJ7=; M>?9> J>; H;B7O 9E?B 9EKB: ;D:KH; ?D 7 L;HO I>EHJ J?C;e oCI C7Ne 0;CF , ] .z sC8?;DJ J;CF;H7JKH; dkg JE ol 0;HC?D7J?ED ,ut 1D?J M;?=>J sFFHENe hjel= uEDIJHK9J?ED 37I> J?=>Jc xBKN FHEESWLV2 h` 0>; :7J7 I>EMD 78EL; 7H; ?D?J?7B L7BK;Ie i` a {D:;N ?I -
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C7NE A67A 9EDJ79JI 799EH EDJ79J BBEM78B 3A35C7A 9EDJ79J
Abstract: , 400 mils Wide, No. 102 â'¢ 32 Pad LCC, No. 141 â'¢ 32 Lead Ceramic SOJ, No. 140 â'¢ 32 Lead , Temperature, T J . 175°C VIL -0.3 - 0.8 V 'Stress , ¥ Parameter 322 EDI88130CS Rev. 1.0 A/92 Sym Max Unit LCC Address Lines Data Lines , 20 30 35 40 ns TWLE1H TWP 20 30 35 40 ns TWLE2L TWP . â  j s i , Write Cycle± Late Write ,W Controlled TAVAV TAVWH TWLWH TAVWL TWHAX W F J- SS k -
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EDI88130LPS 0LPS20LB EDI88130LPS25LB EDI88130CS35LB EDI88130LPS35LB EDI88130CS45LB
Abstract: , T J . 175°C VIL -0.3 - 0.8 V AC Test , Parameter Sym Max LCC FP Address Lines Data Lines Military DIP Cl 6 10 10 PF , , TDVWH , DATA VALID TWLQZ HIGH Z JVr/fe Cycle 2 E Controlled TAVAV ): TAVEL J â  ^ L . _ _ J : TEHAX TAVEH TWLEH ^ WWWWWWWWWWY c II _ , 150 28 0.3 DIP 2 EDI8832C70LB 70 32 LCC 12 EDI8832LP70LB 70 32 LCC -
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EDI8832C EDI8832LP EDI8832LP70CB EDI8832LP85CB EDI8832LP100CB EDI8832LP120CB
Abstract: Pad Ceramic LCC, No. 14 · 28 Lead Flatpack, No. 79 Single +5V (±10%) Supply Operation Pin , A 1 7 3 2 1 28 27 rn NC 4 z j A3 5 u A4 6 Z J A5 7 Z2 A6 8 =3 A7 9 ZD A8 10 Z3 Q 11 Z3 NC 12 Z , 28 28 28 28 Package Style 0.3 DIP 0.3 DIP LCC LCC Flatpack Flatpack No. 3 3 14 14 79 79 Low Power , EDI81256LP55FB Speed (ns) 45 55 45 55 45 55 Leads 24 24 28 28 28 28 Package Style 0.3 DIP 0.3 DIP LCC LCC , Dual-in-line Package 300 Mils Wide Pin 1 Indicator Max / 0.320 0.290 j Package No. 14(C-11) 28 Pad -
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256Kx1 bit EDI81256C EDI81256LP A0-A17 EDI81256C45QB EDI81256C55QB EDI81256C45LB
Abstract: J. 175°C `Stress greater than those isted under 'Absolute , Mode Output Power Parameter Sym LCC Max FP DIP L i. a_ X H L X Unit Standby Output , Note 1: Parameter guaranteed, but not tested. Read Cyc[e± W High; G,E Low L _ [ A V A V - J , TWHAX .TW HDX, » » » » ; Write Cycle 2 E Controlled _ A TAVAV _ ); ^ - TAVEL J L .- " TAVEH TOLEH 1 5 ® _ J i TEHAX )- T "¥ I D Q r _ ' \AAA3|T HIGHZ TDVEH n n -
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EDI8832 A0-A14 EDI8832C70CB EDI8832C85CB EDI8832C100CB EDI8832C120CB EDI8832C150CB
Abstract: ) ,:2 Z /O j ' 2 = /0 1 3 2 C /o 1 = /o 9 2 J o â'" /n 1 â'1 /o / i¡ 3 1 ; /o 1 Z /0 r. 3 1 3 /0 4 1 Z / clk:â'™ .) J ^ â'¢ 2 H vc 4 ec 2 ^>I/O 3L 2 2 I/o 2= 1 tDI/o 2 0 V , ns tAL Array input to LCC 9 12 16 ns tLC LCC input to LCC output10 1 1 1 ns tLO LCC output to output pin 3 5 6 ns tOD, tOE Output Disable, Enable from LCC output7 3 5 6 ns to x Output Disable, Enable from input pin7 15 -
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PA7024 22V10 10-TYP
Abstract: J Lead 3: 6 J Lead 4: 4 pad LCC solder coated 5: 6 pad LCC solder coated Temperature Stability , -VECTRON-1 â'¢ http://www.vectron.com 3 of 7 Outline Drawing / Enclosure Type LCC (ACMOS or TTL , Ground (Case) 3 Output 4 Supply Type LCC (LVPECL or LVDS) Package Code Height â'Hâ , ://www.vectron.com 4 of 7 Outline Drawing / Enclosure J leads are tinned with Alpha Pb/Sn 63/37 solder. Pin Connections Type J LEAD (ACMOS or TTL) Package Code Height â'Hâ' 1 2 3.40 mm Vectron International
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PX-700 MIL-PRF-55310 C1250 EAR99 D-74924 1-88-VECTRON-1
Abstract: DIP, 400 mils Wide, No. 102 â'¢ 32 Pad LCC, No. 141 â'¢ 32 Lead Ceramic SOJ, No. 140 â'¢ 32 Lead , . 40 mA Junction Temperature, T J . 175°C VIL -0.5 - , 23Û â  H i Sym Unit Max LCC Address Lines Data Lines CSOJ, DIP, Flatpack Cl , 32 Flatpack 142 EDI88130CS20LB 20 32 LCC 141 EDI88130LPS20LB 20 32 LCC 141 EDI88130CS25LB 25 32 LCC 141 EDI88130LPS25LB 25 32 LCC 141 -
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EDI88130CS25CC EDI88130CS17CC EDI88130CS25CI EDI88130CS17FC EDI88130CS17LC EDI88130CS17NC
Abstract: mils Wide, No. 9 · 32 Lead Ceramic ZIP, No. 100 · 32 Lead Ceramic SOJ, No. 140 · 32 Pad Ceramic LCC, No , * EDI88128LPS25ZB EDI88128LPS35ZB EDI88128LPS45ZB EDI88128LPS55ZB 25 35 45 55 32 32 32 32 LCC LCC LCC LCC t 32 32 32 , ?!1Flatpack 32 32 32 32 Flatpack Flatpack Flatpack Flatpack îH É S H i iW " '" LCC LCC LCC LCC CSOJ CSOJ , 140 140 140 :j#.1 25 35 45 55 .: î :2 0 ! 25 35 45 55 ïiÉt! 102 102 102 102 `; : 32 32 32 -
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EDI88128LPS EDI88128CS45CB EDI88128CS55CB EDI88128LPS45NB EDI88128CS20CC EDI88128CS25NB EDI88128CS I88128LP EDI88128LPS25CB EDI88128LPS35CB EDI88128LPS45CB
Abstract: ïïi'ïiïiMCc) -40-+85 -40-+85 I 8P-DIP. SOP, S /> "''r x j 20Lead-LCC TO-99, 8P-DIP, S 16P-SOP, 20Lead-LCC , (^ï±lgv) mini, 125ns (f;:-.1^.0-01*-) /Av=- 1, ±0.1%, \ 'h ij 1 !i i! â  ; f 60mA j IA= â'" 15 , (P-Suffix) 8| DISABLE â'"1 8-pin cerdip T] V* (Z-Suffix) -t]0ut 8-pin so J]voshull (S-Suffix) u z < in O 20-CONTACT LCC (RC-Suffix) ZHHrMMX N.C. 3 m N.C. N.C. ±J m N.C. -IN U [Ts V + N.C. T\ m , -99 (J-Sutfix) EPOXY MINI-DIP (P-Suffix) z o z > z 16-PIN SOL (S-Suftix) 20-CONTACT HERMETIC LCC (RC-Sufflx) -
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20Lead-LCC P160A 500C OP260A/E/G P160A/F/G B/60/
Abstract: logic cell - D ,T and J K registers with special fe a tu res - In d ep end en t or global clocks, resets , »2 4 1 40 7 e 9 10 39 u 37 36 35 34 33 12 31 30 ] CNO ] i/o } I/O ]l/0 J l/0 H /o 3 i/o 3 i/o 3 i/o J , < _ I/OKI - 1 rp n n n n n 2 1 44 43 42 41 40 39 ]NC I'/O 37 J'/O 36 J l/o 35 ] I/O 34 J l/o 33 J l/0 32 ] l / 0 35 J l/o 3 C J l/o 29 3 1/0 22 21 24 25 26 27 28 u u u u u u u I/O c 3 I/O 35|=3 I/ O 3 I/ O 3|=J I/ O I/ o I/o t C=|7 I/O C I/o c I/O I/o I/O c c c I/O C 1 I/o C l -
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PA7140J-20 PA7140 04-02-019F PA7140P-20 PA7140F-20 PA7140JN-20
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