500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Direct from the Manufacturer

Part Manufacturer Description PDF & SAMPLES
SSTUA32864BHLF Integrated Device Technology Inc D Flip-Flop
74SSTUBF32868ABKG Integrated Device Technology Inc D Flip-Flop
HCF4013YM013TR STMicroelectronics Dual D Flip-Flop
CD40175BW Texas Instruments CMOS Quad D-Type Flip-Flop 0-WAFERSALE
SN74HCT273ANSRG4 Texas Instruments Octal D-Type Flip-Flops With Clear 20-SO
SN74HCT273ANSRE4 Texas Instruments Octal D-Type Flip-Flops With Clear 20-SO

"D Flip Flops"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: within the 6121 IOC. Each controller has a set of control and status flip flops which are defined below , to be programmed as discussed above. Also, all five flag flip flops are cleared as are the flag sample and interrupt sample flip flops. The interrupt enable flip flops are all set. The strobe flip , flag, flag sample, interrupt sample, interrupt inhibit and strobe flip flops are not disturbed by the , and strobe flip flops. It does not set up the IOC for programming, nor does it disturb the state of -
OCR Scan
T flip flop IC T flip flop IC no T flip flop IC CMOS 6121 6121 harris D flip flop IC HD-6121
Abstract: TTL INTEGRATED CIRCUITS DUAL JK MASTER/SLAVE FLIP FLOP GENERAL DESCRIPTION The flip flops described herein are TTI, (Transistor-Transistor Logic) dual ]K Master/Slave flip flops. Asynchrorous CLEAR inputs are provided on the flip flops The device is totally monolithic and designed for use in high speed , after clock pulse. DUAL D FLIP FLOP GENERAL DESCRIPTION The 7474 is designed for use where the flexibility of 2 inputs is not required. It has only a single DATA (D) input. The logical level applied to -
OCR Scan
ic D flip flop 7474 JK flip flop IC ic 7474 features of ic 7474 7474 j-k flip flop pin IC 7474
Abstract: 0.38 0.48 0.45 1.63 1.63 1.63 0.30 0.34 0.34 0.35 0.30 0.30 Flip Flops & Registers 74ACT74SC Dual D , -Input OR Gate 74AC86SC Quad 2-input Exclusive-OR Gate Flip Flops & Registers 74AC74SC Dual D Flip-Flop , Trigger Input Flip Flops & Registers 74ACTQ273SC Octal D Flip-Flop with Clear 74ACTQ16374SSC 16-Bit D , -Input OR Gate 74VHC86M Quad 2-Input Exclusive OR Gate Flip Flops & Registers 74VHC74M Dual D Flip-Flop with , Series Gate CD4093BCM Quad 2-Input NAND Schmitt Trigger Flip Flops & Registers CD4013BCM Dual D Flip-Flop -
Original
MM74HC00M MM74HC04M MM74HC14M MM74HC74AM MM74HC273WM octal Bilateral Switches MM74HC138M MM74HC125M CD4025BCM MM74HC MM74HC02M MM74HC08M
Abstract: met, so the only roadblock is the clock to output time for the T flip flop. Toggle flip flops have , the logic attached to the input of the flip flops, with a single product term being needed for simple , the sum of products logic and simply show the overall result of tying consecutive flip flops together , attaching to the fast input sites on the entry flip flops. Note that each is clocked by the opposite phase , flip flops operating in the "dual edge triggered" mode. Note that the T flops are initialized out of Xilinx
Original
XAPP379 XAPP375 XAPP376 XAPP377 XAPP378 t flip flop COOLRUNNER-II 7 segment verilog code for johnson counter
Abstract:  SN54ALS29825, SN74ALS29825, SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS , 655012 â'¢ DALLAS. TEXAS 75265 SN54ALS29825, SN74ALS29825, SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS , '¢ DALLAS, TEXAS 75265 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS FUNCTION TABLE , Instruments POST OFFICE BOX 656012 â'¢ DALLAS. TEXAS 75265 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH , SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS switching characteristics PARAMETER FROM -
OCR Scan
D2829 AM29825 1N916 1N3064 Flip Flops JD 1801 AM29826 SDAS147B
Abstract: Function H 1)7', Series HD74S Series Dual 4-input Expanders 60 â'" â'¢ FLIP FLOPS Function HD74 Series HD74S Series J-K Master-Flip Flop (AND Inputs) 72 â'" Dual J-K Flip Flops 73 - â'" Dual D-type Edge-triggered Flip Flops 74 74 Dual J-K Flip Flops (with PR and CLR) 76 â'" Dual J-K Flip Flops 107 " â'" Dual J-K Negative-edge-triggered Flip Flops (wi th PR and CLR) â'" 112 - Dual J-K Negative-edge-triggered Flip Flops ( wi th PR) â'" 113 Dual J-K Negative-edge-triggered Flip -
OCR Scan
16-LINE TO 4-LINE PRIORITY ENCODERS 74 series logic gates 4-bit even parity checker 4-bit shift register 74 194 J-K Flip flops 74 series 7 segment decoders HD74/HD74S HD74/74S DP-16 DP-20 DP-24 DG-14
Abstract: is used to keep track of bit position within the J2 frames. D flip flops are used to control the , clocks passed to the FREEDM-8. Reset of the counter and D flip flops occur every J2 frame boundary. The , flip flops, respectively. Feedback is used by each D flip flop to sustain gating signals until the , single 10 bit counter is used to keep track of bit position within the J2 frames. D flip flops are used , [4:1] and TD[4:1] are signals for the FREEDM-8's four ports. Reset of the counter and D flip flops PMC-Sierra
Original
PM7366 ts5667 D Flip Flops TS7798 PM7346 rfpo PMC-971136 PM-971136
Abstract: HD74 Series HD74S Series Dual 4-input Expanders 60 â'" â'¢ FLIP FLOPS Function HD74 Series HD74S Series J-K Master-Flip Flop (AND Inputs) 72 â'" Dual J-K Flip Flops 73 " â'" Dual D-type Edge-triggered Flip Flops 74 ^ 74 ' Dual J-K Flip Flops (with PR and CLR) 76 â'" Dual J-K Flip Flops 107 " â'" Dual J-K Negative-edge-triggered Flip Flops (with PR and CLR) â'" 112 - Dual J-K Negative-edge-triggered Flip Flops (with PR) â'" 113 Dual J-K Negative-edge-triggered Flip Flops (with PR, Common CLR -
OCR Scan
DP-14 NAND Gates Synchronous 8-Bit Binary Counters HD74 synchronous binary counter with latch 4 inputs positive OR gates
Abstract: 8 8 0 2 2 2 S-R Latches 29 29 29 29 29 72 21 21 21 D Latches 28 28 28 28 28 72 32 32 32 D Flip Flops 8 10 10 10 10 76 12 12 12 Scannable Flip Flops 17 17 17 17 17 8 8 8 8 JK Flip Flops 18 18 18 18 18 0 4 4 4 Toggle Flip Flops 8 8 7 7 7 0 2 2 , IrDA1.1 Controller D/A Converter A/D Converter ARMARM7TDMIARM POWERED Advanced RISC Machines OKI Electric Industry
Original
MSM13Q MSM98Q MG73Q MG113P 32-768K FJXLSC-MACROLIB-04 MSM10S MSM38S MSM12R MSM13R MSM32R
Abstract: HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs Preliminary Description The H D 74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition o f the clock (CLK) input, the , components. The output enable (OE) input does not affect the internal operations o f the flip flops. Old data , were established. Output Q CLK t t H o rL X D H L X X H L Qo'' z 352 HD74ALVCH162821 -
OCR Scan
LYCHI62821
Abstract: 6 5 5 5 10 5 8 8 8 8 8 0 2 D Latches 29 29 29 29 29 72 21 D Flip Flops 28 28 28 28 28 72 32 8 10 10 10 10 76 12 JK Flip Flops 17 17 17 17 17 8 8 Toggle Flip Flops 18 18 , S-R Latches Scannable Flip Flops I/O1 Input Buffers Input Buffers with Pull Up/Pull Down I/O OKI Electric Industry
Original
MSM98S 44k1 642k 64512 J2N0015-38-82 MSM98R MSM30R MSM14Q MSM99Q
Abstract: -bit parallel output serial shift register 8-bit serial/parallel input shift register Hex D-type flip flops Quad D-type flip flops Synchronous up/down counter binary 74191 Synchronous up/down counter BCD , -input exclusive-NOR gates with open collector outputs Octal D-type flip flops Quad SR latches 9-bit odd/even , 4-bit data. Octal D-type latches Octal D-type flip flops 4-bit bistable latches Hex D-type flip , Quad D flip flop Synchronous decimal counter with set and reset inputs and N-input Synchronous 4 Electro Value
Original
FZH115B fzh261 FZH131 FZK105 FZJ111 FZH115 74INTEGRATED 16-DIL
Abstract: Dual 4-input Expanders _ â'¢ FLIP FLOPS Function HD74 Series IID74S Series J-K Master-Flip Flop , Dual J-K Flip Flops (with FR and CI.RJ 76 Dual J-K Flip Flop* 107 /S Dual J-K Negiitivc-cd*e-triggered Flip Flops (with PR and CI.R) _ 112 - Dual J-K Ncgative-rdge-trigger«! Flip Flops (wich PR) â'" 113 DmI J-K Nefahte-edgr-tr^ered Flip Flops (with PR. Common CLR. and CnDM CK) 1U - Monostable MuJtivibrator 121-^ Dual Retrifctferable Monnstable Muhivibrators 123 w â'" Hex D-type Flip Flops {with CI.R -
OCR Scan
2 input nand gate 24v H183 quad jk flip flop
Abstract: MITSUBISHI LSTTLs M74LS374P OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOPS W ITH 3 , DESCRIPTION Since the 8 D -type ege-triggered flip -flo p circuits use a pnp transistor input fo r the ou tp , POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOPS W ITH 3-STATE OUTPUTS FUNCTION TABLE (N otei) OC L L L H L X T , POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOPS W ITH 3-STATE OUTPUTS SWITCHING CHARACTERISTICS Symbol fm a x , POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOPS W ITH 3-STATE OUTPUTS APPLICATION EXAMPLE 8-B it shift register -
OCR Scan
0013S 14-PIN 16-PIN 20-PIN
Abstract: PSoC CreatorTM Component Datasheet ® D Flip Flop w/ Enable 1.0 Features Enable input allows d input to be selectively captured. Configurable width for array of D Flip Flops with a single enable. General Description The D Flip Flop w/ Enable selectively captures a digital value. When to Use a D Flip Flop w/ Enable Use the D Flip Flop w/ Enable to implement sequential logic. Input , provides the following parameters. ArrayWidth You can create an array of D Flip Flops with a single Cypress Semiconductor
Original
Abstract: SN54LS112A, SN54S112, SN74LS112A, SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH , SN54LS112A, SN54S112, SN74LS112A. SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR , SN54LS112A, SN54S112, SN74LS112A, SN74S112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR , â'¢ DALLAS. TEXAS 75265 SN54S112, SN74S112A DUAL J K NEGATIVE EDGE TRIGGERED FLIP FLOPS WITH , FLIP FLOPS WITH PRESET AND CLEAR switching characteristics, Vcc ~ 5 V, Ta " 25 °C (see Note 4 -
OCR Scan
LS112A SN54LS112 SN74
Abstract: Flops with 3-State Outputs. 10-bit D-type Flip Flops with Dual Outputs. 10-bit Bus Interface Flip Flops with 3 , Bus Transceivers with 3-State Outputs. 20-bit D-type Flip Flops with 3-State Outputs. 10-bit D-type Flip Flops with Dual Outputs. 10-bit Bus Interlace Flip Flops with 3-State Outputs. 18 -
OCR Scan
HD74LVC/LV
Abstract: SN54ALS564A, SN74ALS564A OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS D2661 , , SN74ALS564A OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS logic diagram (positive logic) V , Respective Manufacturer SN54ALS564A, SN74ALS564A OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE , SN54ALS564A, SN74ALS564A OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS switching , D L t H L L T L H L L X Qo H X X z OC â'" CLK â  ID-2D-3D-4D-5D-6D-7D 8D- (111 (2) (3 -
OCR Scan
ALS564A SN54AL5564A SNS4ALS564A
Abstract: 5 to r > SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS d2829 , SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS description (continued) PUU , By Its Respective Manufacturer SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 , SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS switching characteristics , Respective Manufacturer SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS -
OCR Scan
NT 101 ALS29825 ALS29826 4ALS29825
Abstract: HD74ALVCH16821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs HITACHI ADE-205-171 (Z) Preliminary, 1st. Edition January 1997 Description The HD74ALVCH16821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the , affect the internal operations of the flip flops. Old data can be retained or new data can be entered , Function Table Inputs Output Q OE CLK D L t H H L t L L L H or L -
OCR Scan
HD74AL CH16821 TTP-56D
Showing first 20 results.