500 MILLION PARTS FROM 12000 MANUFACTURERS

Part | Manufacturer | Description | Samples | Ordering |

HPA00022RGQ8 | Texas Instruments | D FLIP-FLOP | |||

HPA00025S8 | Texas Instruments | D FLIP-FLOP | |||

HPA00022RGQR | Texas Instruments | D FLIP-FLOP |

Catalog Datasheet | MFG & Type | Document Tags |

Abstract: within the 6121 IOC. Each controller has a set of control and status flip flops which are defined below , to be programmed as discussed above. Also, all five flag flip flops are cleared as are the flag sample and interrupt sample flip flops. The interrupt enable flip flops are all set. The strobe flip , flag, flag sample, interrupt sample, interrupt inhibit and strobe flip flops are not disturbed by the , and strobe flip flops. It does not set up the IOC for programming, nor does it disturb the state of ... | OCR Scan |
8 pages, |
harris 6121 D flip flop IC 6121 harris 6121 T flip flop IC CMOS T flip flop IC no T flip flop IC HD-6121 TEXT |

Abstract: ï»¿TTL INTEGRATED CIRCUITS DUAL JK MASTER/SLAVE FLIP FLOP GENERAL DESCRIPTION The flip flops described herein are TTI, (Transistor-Transistor Logic) dual ]K Master/Slave flip flops. Asynchrorous CLEAR inputs are provided on the flip flops The device is totally monolithic and designed for use in high speed , after clock pulse. DUAL D FLIP FLOP GENERAL DESCRIPTION The 7474 is designed for use where the flexibility of 2 inputs is not required. It has only a single DATA (D) input. The logical level applied to ... | OCR Scan |
1 pages, |
D flip flop IC 7474 d flip ic for jk flip flop IC 7474 flipflop 7474 flip flops master slave jk flip flop 7474 flip flop features of ic 7474 d flip flop 7474 ic 7474 D flip flop 7474 truth table 7474 jk flip flop ic d flip flop 7474 pin IC 7474 7474 j-k flip flop features of ic 7474 ic 7474 JK flip flop IC T flip flop IC ic D flip flop 7474 TEXT |

Abstract: 0.38 0.48 0.45 1.63 1.63 1.63 0.30 0.34 0.34 0.35 0.30 0.30 Flip Flops & Registers 74ACT74SC 74ACT74SC Dual D , -Input OR Gate 74AC86SC 74AC86SC Quad 2-input Exclusive-OR Gate Flip Flops & Registers 74AC74SC 74AC74SC Dual D Flip-Flop , Trigger Input Flip Flops & Registers 74ACTQ273SC 74ACTQ273SC Octal D Flip-Flop with Clear 74ACTQ16374SSC 74ACTQ16374SSC 16-Bit D , -Input OR Gate 74VHC86M 74VHC86M Quad 2-Input Exclusive OR Gate Flip Flops & Registers 74VHC74M 74VHC74M Dual D Flip-Flop with , Series Gate CD4093BCM CD4093BCM Quad 2-Input NAND Schmitt Trigger Flip Flops & Registers CD4013BCM CD4013BCM Dual D Flip-Flop ... | Original |
3 pages, |
tristate 74ACT399SC cd4046bcm cd4052bcm 74AC04SC MM74HC273WM MM74HC04M MM74HC00M MM74HC74AM CD4025BCM MM74HC125M MM74HC138M MM74HC14M octal Bilateral Switches MM74HC MM74HC00M MM74HC MM74HC MM74HC00M MM74HC02M MM74HC08M MM74HC32M MM74HC86M MM74HC132M MM74HC174M MM74HC175M MM74HC123AM MM74HC221AM MM74HC423AM MM74HC4538M MM74HCT/U TEXT |

Abstract: met, so the only roadblock is the clock to output time for the T flip flop. Toggle flip flops have , the logic attached to the input of the flip flops, with a single product term being needed for simple , the sum of products logic and simply show the overall result of tying consecutive flip flops together , attaching to the fast input sites on the entry flip flops. Note that each is clocked by the opposite phase , flip flops operating in the "dual edge triggered" mode. Note that the T flops are initialized out of ... | Xilinx Original |
9 pages, |
XAPP379 CoolRunner-II CPLD flip flop T Toggle FLIP FLOP toggle COOLRUNNER-II XAPP375 XAPP377 XAPP378 XAPP376 verilog code for johnson counter COOLRUNNER-II 7 segment t flip flop TEXT |

Abstract: ï»¿ SN54ALS29825 SN54ALS29825, SN74ALS29825 SN74ALS29825, SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS , 655012 â¢ DALLAS. TEXAS 75265 SN54ALS29825 SN54ALS29825, SN74ALS29825 SN74ALS29825, SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS , ¢ DALLAS, TEXAS 75265 SN74ALS29826 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS FUNCTION TABLE , Instruments POST OFFICE BOX 656012 â¢ DALLAS. TEXAS 75265 SN54ALS29825 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH , SN54ALS29825 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS switching characteristics PARAMETER FROM ... | OCR Scan |
8 pages, |
SN74ALS29826 1N3064 1N916 AM29825 D2829 JD 1801 SN54ALS29825 SN74ALS29825 Flip Flops AM29826 TEXT |

Abstract: Function H 1)7', Series HD74S HD74S Series Dual 4-input Expanders 60 â â¢ FLIP FLOPS Function HD74 Series HD74S HD74S Series J-K Master-Flip Flop (AND Inputs) 72 â Dual J-K Flip Flops 73 - â Dual D-type Edge-triggered Flip Flops 74 74 Dual J-K Flip Flops (with PR and CLR) 76 â Dual J-K Flip Flops 107 " â Dual J-K Negative-edge-triggered Flip Flops (wi th PR and CLR) â 112 - Dual J-K Negative-edge-triggered Flip Flops ( wi th PR) â 113 Dual J-K Negative-edge-triggered Flip ... | OCR Scan |
4 pages, |
J-K latches HD74 H183 2 input nand gate 24v 74 series 7 segment decoders J-K Flip flops Flip Flops 4-bit shift register 74 194 4-bit even parity checker 74 series logic gates 16-LINE TO 4-LINE PRIORITY ENCODERS HD74/HD74S TEXT |

Abstract: is used to keep track of bit position within the J2 frames. D flip flops are used to control the , clocks passed to the FREEDM-8. Reset of the counter and D flip flops occur every J2 frame boundary. The , flip flops, respectively. Feedback is used by each D flip flop to sustain gating signals until the , single 10 bit counter is used to keep track of bit position within the J2 frames. D flip flops are used , [4:1] and TD[4:1] are signals for the FREEDM-8's four ports. Reset of the counter and D flip flops ... | PMC-Sierra Original |
19 pages, |
TS977 TS56 rfpo PM7366 PM7346 "D Flip Flops" TS7798 D Flip Flops ts5667 PMC-971136 TEXT |

Abstract: HD74 Series HD74S HD74S Series Dual 4-input Expanders 60 â â¢ FLIP FLOPS Function HD74 Series HD74S HD74S Series J-K Master-Flip Flop (AND Inputs) 72 â Dual J-K Flip Flops 73 " â Dual D-type Edge-triggered Flip Flops 74 ^ 74 ' Dual J-K Flip Flops (with PR and CLR) 76 â Dual J-K Flip Flops 107 " â Dual J-K Negative-edge-triggered Flip Flops (with PR and CLR) â 112 - Dual J-K Negative-edge-triggered Flip Flops (with PR) â 113 Dual J-K Negative-edge-triggered Flip Flops (with PR, Common CLR ... | OCR Scan |
4 pages, |
H183 4-bit even parity checker 8 bit multiplier with shift register 8 bit ttl encoder hd74 series DP-14 4 inputs positive OR gates synchronous binary counter with latch HD74 HD74S Synchronous 8-Bit Binary Counters J-K Flip flops HD74/HD74S NAND Gates HD74/HD74S "J-K Flip flops" HD74/HD74S Flip flops HD74/HD74S 74 series logic gates HD74/HD74S 16-LINE TO 4-LINE PRIORITY ENCODERS HD74/HD74S HD74/HD74S HD74/HD74S TEXT |

Abstract: 8 8 0 2 2 2 S-R Latches 29 29 29 29 29 72 21 21 21 D Latches 28 28 28 28 28 72 32 32 32 D Flip Flops 8 10 10 10 10 76 12 12 12 Scannable Flip Flops 17 17 17 17 17 8 8 8 8 JK Flip Flops 18 18 18 18 18 0 4 4 4 Toggle Flip Flops 8 8 7 7 7 0 2 2 , IrDA1.1 Controller D/A Converter A/D Converter ARMARM7TDMIARM POWERED Advanced RISC Machines ... | OKI Electric Industry Original |
5 pages, |
MSM98Q MSM13Q MG73Q MG113P 32-768K "Single-Port RAM" D Flip Flops FJXLSC-MACROLIB-04 TEXT |

Abstract: HD74ALVCH162821 HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs Preliminary Description The H D 74ALVCH162821 74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition o f the clock (CLK) input, the , components. The output enable (OE) input does not affect the internal operations o f the flip flops. Old data , were established. Output Q CLK t t H o rL X D H L X X H L Qo'' z 352 HD74ALVCH162821 HD74ALVCH162821 ... | OCR Scan |
10 pages, |
HD74ALVCH162821 TEXT |

Abstract | Saved from | Date Saved | File Size | Type | Download |

redundancies and maximizing resource utilization. Registers specified as JK, SR, T or D flip flops are synthesized to either D or T flip flops so that the number of product terms used is minimized. The logic
/datasheets/files/waferscale/html/relpsf5.html |
Waferscale | 11/02/2000 | 14.11 Kb | HTML | relpsf5.html |

ments. The IS Logic block comprises mainly two D flip- flops. When a conduction signal arrives, the ratio ns np = ( V OUT + V D ) x T DM V IN ( min ) x T ON ( max ) Reflected voltage V R = 1 T T ON ( max CEsat + V D 3 2V Remark : The mains of the TEA2260/61 TEA2260/61 must be provided through an isolation transformer voltage filtering capacitor 376-39A.EPS / 376-39B 376-39B.EPS Figure 39 Hypothesis : D V : ripple on the filtering power of the power supply h : efficiency of the power supply C = T 2 p x p 2 + ArcSin ( 1 - D V V IN AC
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1614-v2.htm |
STMicroelectronics | 14/06/1999 | 49.53 Kb | HTM | 1614-v2.htm |

ments. The IS Logic block comprises mainly two D flip- flops. When a conduction signal arrives, the ratio ns np = ( V OUT + V D ) x T DM V IN ( min ) x T ON ( max ) Reflected voltage V R = 1 T T ON ( max CEsat + V D 3 2V Remark : The mains of the TEA2260/61 TEA2260/61 must be provided through an isolation transformer voltage filtering capacitor 376-39A.EPS / 376-39B 376-39B.EPS Figure 39 Hypothesis : D V : ripple on the filtering power of the power supply h : efficiency of the power supply C = T 2 p x p 2 + ArcSin ( 1 - D V V IN AC
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1614-v1.htm |
STMicroelectronics | 02/04/1999 | 49.57 Kb | HTM | 1614-v1.htm |

ments. The IS Logic block comprises mainly two D flip- flops. When a conduction signal arrives, the ratio ns np = ( V OUT + V D ) x T DM V IN ( min ) x T ON ( max ) Reflected voltage V R = 1 T T ON ( max CEsat + V D 3 2V Remark : The mains of the TEA2260/61 TEA2260/61 must be provided through an isolation transformer voltage filtering capacitor 376-39A.EPS / 376-39B 376-39B.EPS Figure 39 Hypothesis : D V : ripple on the filtering power of the power supply h : efficiency of the power supply C = T 2 p x p 2 + ArcSin ( 1 - D V V IN AC
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1614.htm |
STMicroelectronics | 20/10/2000 | 55.18 Kb | HTM | 1614.htm |

power transistor safety require- ments. The IS Logic block comprises mainly two D flip- flops. When ( min ) I P ( max ) x T ON ( max ) Transformer ratio ns np = ( V OUT + V D ) x T : 1V 3 V CEsat + V D 3 2V Remark : The mains of the TEA2260/61 TEA2260/61 must be provided through an Figure 39 Hypothesis : D V : ripple on the filtering voltage V IN.AC(min) : minimal value of A.C. : efficiency of the power supply C = T 2 p x p 2 + ArcSin ( 1 - D V V IN AC ( min ) x
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1614-v3.htm |
STMicroelectronics | 25/05/2000 | 51.51 Kb | HTM | 1614-v3.htm |