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"Clock and Data Recovery"

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Abstract: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the , recovery PLL and to provide a clock reference in the absence of serial input data. The device supports a , generation and clock recovery ICS Output: clock signal (622.08MHz or 155.52MHz) and retimed data , -01 REV. C OCTOBER 15, 2008 ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE Integrated Device Technology
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OC-12/STS-12 ICS894D115BGI-01
Abstract: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the , recovery PLL and to provide a clock reference in the absence of serial input data. The device supports a , . · Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3) · · Input: NRZ data , , 2008 ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE Functional Integrated Device Technology
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ICS894D115I ICS894D115I-04 tube OC3 OC3 Tube vsc8115
Abstract: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the , recovery PLL and to provide a clock reference in the absence of serial input data. The device supports a , generation and clock recovery â'¢ See ICS894D115I-01 for a clock/data recovery circuit with LVPECL , ICS894D115AGI-04 REV. C OCTOBER 15, 2008 ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY Integrated Device Technology
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Abstract: XRT91L33 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT AUG 2008 REV. V1.0.0 FEATURES · Performs clock and data recovery for selectable data of 622.08 Mbps (STS-12/STM-4) or 155.52 , Equipment GENERAL DESCRIPTION The XRT91L33 is a fully integrated multirate Clock and Data Recovery (CDR , provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled , biasing 0 CDR STS-12/3 or STM-4/1 Clock and Data Recovery LVDS/LVPECL Output Drivers Exar
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GR-253 XRT91L33IG STS-12
Abstract: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the , recovery PLL and to provide a clock reference in the absence of serial input data. The device supports a , . · Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3) · · Input: NRZ data , ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE Functional Description The Integrated Device Technology
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led clock circuit diagram
Abstract: ). Clock recovery procedure 1. Connect both data and reference inputs to the device. The reference , ) High (or 0 V). Clock recovery procedure 1. Connect both data and reference inputs to the device. The , ) High (or 0 V). Clock recovery procedure 1. Connect both data and reference inputs to the device. The , Agilent N4982A Clock Recovery Unit Data Sheet For 100GE or SONET/ SDH Applications â'¢ Low , reference selector between input data and reference clock Selects between two VCOs for lower/upper band Agilent Technologies
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N4982A-R19 MC19R26M N4982A-R25 MC25R32M N4982A-R28 MC28R36M
Abstract: Agilent N4877A Clock Data Recovery and Demultiplexer 1:2 Agilent N1075A Optical Pick-Off , optical clock data recovery solution consisting of N4877A clock data recovery and demultiplexer 1:2 and N1075A optical pick-off/converter Electrical and Optical Clock Data Recovery Solutions up to 32 Gb/s , computer, datacom as well as communication standards. The N4877A clock data recovery (CDR) and , transfer. A hardware clock data recovery like the N4877A, N1070A and 83496B can be configured as a jitter Agilent Technologies
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5990-9949EN
Abstract: option) CR175A and CR286A offer Optional Higher-sensitivity Data Inputs with Clock Recovery on Signals , in phase between data input and clock recovery output. View and Measure SSC Modulation The , G, 5 G and 8 G ) HS Add High-sensitivity Clock Recovery (This option has no data outputs.)*3 , Clock Recovery under High ISI Input Conditions Data Measurement Capability Edge Density Measurement â , Benefits Instrumentation Quality Clock Recovery 150 Mb/s to 28.6 Gb/s with Continuous Data Rate Coverage Tektronix
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10GBASE-KR 100GBASE-LR-4/100GBASE-ER-4
Abstract: XRT91L33A STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT JUNE 2010 REV. 1.0.1 FEATURES Performs clock and data recovery for selectable Enhanced Jitter performance Meets both Jitter , Equipment GENERAL DESCRIPTION The XRT91L33A is a fully integrated multirate Clock and Data Recovery (CDR , provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled , CDR STS-12/3 or STM-4/1 Clock and Data Recovery RXDOP RXDON 1 RECVDCLKOUT RXCLKOP Exar
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XRT9
Abstract: specified rate and clock recovery is performed on the incoming data stream. An external oscillator is , from the data. The chip outputs a differential bit clock and retimed data. The S3050 utilizes an , input data. Retimed data and clock are output from the S3050. Figure 2. S3050 Functional Block , -12, or OC-3 serial data links. The chip extracts the clock from the serial data inputs and provides retimed clock and data outputs. A 155.52 MHz reference clock is required for phase locked loop start up Applied Micro Circuits
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OC-48 OC-24 OC-12
Abstract: PRELIMINARY OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE ICS894D115I-01 Features · , with LVDS outputs General Description The ICS894D115I-01 is a clock and data recovery circuit. The , , 2008 ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE PRELIMINARY Table 1 , -12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE PRELIMINARY Table 3. Pin Characteristics Symbol , -4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE PRELIMINARY Table 4E. BYPASS Mode Configuration Table Integrated Device Technology
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Nippon capacitors
Abstract: XRT91L33A STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT MARCH 2010 REV. 1.0.0 FEATURES Performs clock and data recovery for selectable Enhanced Jitter performance Meets both , Equipment GENERAL DESCRIPTION The XRT91L33A is a fully integrated multirate Clock and Data Recovery (CDR , provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled , CDR STS-12/3 or STM-4/1 Clock and Data Recovery RXDOP RXDON 1 RECVDCLKOUT RXCLKOP Exar
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XRT91L33AIG-F
Abstract: rate. Differential serial data is input to the chip at the specified rate, and clock recovery is , -3, Fibre Channel or Gigabit Ethernet scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential bit clock and retimed data. The S3056 utilizes an on-chip PLL which consists of a , provide a stable output clock source in the absence of serial input data. Retimed data and clock are , data links. The chip extracts the clock from the serial data inputs and provides retimed clock and Applied Micro Circuits
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s3067 GR-253-CORE prescaler 120 ghz S3057 STS-48 TA-NWT-000253 D151/R293
Abstract: data stream Bellcore jitter compliance (tolerance and transfer) Supports clock recovery for 51.84 , ICS1884 supports clock and data recovery for either OC/STS-1 or OC/STS-3/STM-1 line rate. ECL , recovery is performed on this incoming data stream. Regenerated serial data and recovered clock are output , clock recovery mode, input from which receive bit clock is recovered and receive data is regenerated , recovery mode, input from which transmit bit clock is recovered and transmit data is regenerated when Integrated Circuit Systems
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ICS1884M gigaBERT-1400Tx PM5345 SJ-300 TRNWT-000253 ICS1884R I022996
Abstract: emulation using unstructured data transfer (UDT). 2.0 Clock Recovery Techniques 2.1 Adaptive , known as adaptive clock recovery. It is not necessary to use the actual data packet arrival rate, since , result to control a DCO. The output of the DCO is used to clock the TDM data out of the MT90880, and , network for use with both adaptive and differential clock recovery methods. Where there is no common , 8). Using this hardware it is possible to implement both adaptive and differential clock recovery Zarlink Semiconductor
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MSAN-198 remote controlled real time clock MPC8260 MT9045 MT90869 AN5789 MSAN-199 DS5568
Abstract: AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet 1.0 Introduction , , Sniff ModeTM signal acquisition, and data clock recovery, the AMIS-52150 is ideally suited for a wide , threshold o Data slice · Clock and data recovery (Reduced data jitter) 2 · I C interface: Control bus · , AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet Figure 1: AMIS , 3 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Table 4: Electrical AMI Semiconductor
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AMIS-52050 350MH 448MH 300MH 768MH M-20535-005
Abstract: minimum timing for SpaceWire clock recovery circuit was achieved in an RTAX-S device and will provide , flow, explaining how the user can design and import a SpaceWire clock recovery circuit into a main , data into Data and Strobe so that the clock can be recovered by simply XORing the Data and Strobe , to the host system. The Rx clock is recovered by simply XORing the received Data (Din) and Strobe (Sin) signals together. The RX Clock Recovery blocks generates the receiver clock and provides all the Actel
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AC305 RTAX-S lvds SpaceWire SpaceWire cable Signal Path Designer telemetry block diagram
Abstract: specified rate, and clock recovery is performed on the incoming data stream. An external oscillator is , transfer and jitter generation On-chip high frequency PLL with internal loop filter for clock recovery , -48, OC-24, GBE, OC12, or OC-3 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential bit clock and retimed data. Figure 1 shows a typical network application. The , serial input data. The retimed data and clock are output from the S3050. Sumitomo OC-48 Optical Applied Micro Circuits
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S3041 S3042 S3044 S3045
Abstract: -48 Receiver The S3050 supports clock recovery for the OC-48, OC-24, Gigabit Ethernet, OC-12, or OC-3 data rate. Differential serial data is input to the chip at the specified rate and clock recovery is , frequency of the clock recovery PLL and also used as a standby clock in the absence of data, during reset or , -12, or OC-3 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential bit clock and retimed data. The S3050 utilizes an on-chip PLL which consists of a phase detector, a Applied Micro Circuits
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Abstract: clock recovery is performed on the incoming data stream. Retimed data and clock are output from the , function for SONET OC-48 serial data links. The chip extracts the clock from the serial data inputs and provides retimed clock and data outputs. Clock Recovery Clock Recovery, as shown in the block diagram in , filter for clock recovery Supports clock recovery for OC-48/STM-16 (2488.32 Mbit/s) NRZ data Low-jitter , recovers the clock from the data. The chip outputs a differential bit clock and retimed data. The S3047 -
OCR Scan
OC-48/ STM-16
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