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LMK01801BISQ/NOPB Texas Instruments LMK01801 Dual Clock Distribution 48-WQFN -40 to 85
LMK01801BISQX/NOPB Texas Instruments LMK01801 Dual Clock Distribution 48-WQFN -40 to 85
LMK01801BISQE/NOPB Texas Instruments LMK01801 Dual Clock Distribution 48-WQFN -40 to 85
LTC6954IUFF-4#PBF Linear Technology LTC6954 - Low Phase Noise, Triple Output Clock Distribution Divider/Driver; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C
LTC6950IUHH#TRPBF Linear Technology LTC6950 - 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution; Package: QFN; Pins: 48; Temperature Range: -40°C to 85°C
LTC6954IUFF-2#PBF Linear Technology LTC6954 - Low Phase Noise, Triple Output Clock Distribution Divider/Driver; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C

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"Clock Distribution"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: distribution portion of the clock methodology beginning with test insertion. Features Features supported , · Hierarchical clock distribution composed of global, intermediate, and local clocking levels · , anytime. · Include a core clock distribution module The general requirement is to use a temporary clock distribution module for buffering all core clocks that are to be implemented using the standard clock distribution methodology. The primary purpose of such a module includes: a. For clocks that are Avago Technologies
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DesignWare AVAGO TECHNOLOGIES
Abstract: DATASHEET IDT6P30006A CLOCK DISTRIBUTION CIRCUIT Description Features The IDT6P30006A is a low-power, eight output clock distribution circuit. The device takes a TCXO or LVCMOS input , TCXO_INA ±100mVpp OUT7 OUT8 MUX 3 SEL IDT® CLOCK DISTRIBUTION CIRCUIT GND 1 IDT6P30006A REV D 061711 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS OE4 OE1 , ground. IDT® CLOCK DISTRIBUTION CIRCUIT Pin Description 2 IDT6P30006A REV D 061711 Integrated Device Technology
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IDT TOP SIDE package marking p36AG p36agi
Abstract: EB 216E Clock Signal Distribution in Systems without PLL Clock Drivers Author: Peter Forstner , distribution, but does not cover the different aspects arising with PLL clock drivers. After an explanation , distribution system are examined. The Report then presents methods of implementing an effective clock , approaches to clock distribution are covered, with a presentation of the various clock driver circuits in , ?. . . . 5 3. Problems with Clock Distribution Texas Instruments
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SN74ABT244 CDC351 CDC341 CDC340 CDC328
Abstract: -05-0131-0334-1.00 Keywords nanoNET TRX transceiver, clock supply, 16 MHz, 32.768 kHz, Local Oscillator, clock distribution , the internal clock distribution can be enabled or disabled. A Feature Clock provides a clock signal , oscillator and the internal clock distribution can be enabled or disabled over the user interface. If , and the internal clock distribution are disabled by default after the transceiver has been powered up (or at power-up-reset). The internal clock distribution can be enabled and disabled without glitches Nanotron Technologies
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crystal oscillator 32.768 4 mhz crystal oscillator 4 MHz crystal Quartz Clock crystal 32.768 khz crystal apply nanotron NA-05-0131-0334-1
Abstract: DATASHEET CLOCK DISTRIBUTION CIRCUIT I DT 6 T 3 9 0 0 7 A Description Features The IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or 1.8 V to 2.5 , IDT® CLOCK DISTRIBUTION CIRCUIT 1 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION , disabled. IDT® CLOCK DISTRIBUTION CIRCUIT 2 IDT6T39007A REV H 022212 IDT6T39007A CLOCK , Connect to TCXO input. 24 VDDO1 Power Connect to +3.0 V. IDT® CLOCK DISTRIBUTION CIRCUIT Integrated Device Technology
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Abstract: TECHNICAL DATA AN1405 ECL Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications , placed an even greater emphasis on the design of low skew clock generation and distribution networks , or for the first level device of a nested clock distribution tree. In these two situations the only , supply levels and the stability of the power busses within the chip. Clock distribution trees by , distribution devices. However even with this strategy TTL and CMOS clock distribution devices are limited to Freescale Semiconductor
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AN1405/D
Abstract: DATASHEET CLOCK DISTRIBUTION CIRCUIT I DT 6 P3 0 0 0 6 A Description Features The IDT6P30006A is a low-power, eight output clock distribution circuit. The device takes a TCXO or LVCMOS input , OUT6 TCXO_INA ±100mVpp OUT7 OUT8 MUX 3 SEL IDT® CLOCK DISTRIBUTION CIRCUIT GND 1 IDT6P30006A REV D 061711 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS , GND Power Connect to ground. IDT® CLOCK DISTRIBUTION CIRCUIT Pin Description 2 Integrated Device Technology
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Abstract: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL , TIMING SOLUTIONS BR1333 - REV 4 AN1405 ECL Clock Distribution Techniques INTRODUCTION The ever , low skew clock generation and distribution networks. Clock skew, the difference in time between , or for the first level device of a nested clock distribution tree. In these two situations the only , large. For designs whose clock distribution networks lie on a single board which utilizes power and -
OCR Scan
Abstract: DATASHEET IDT6P30006A CLOCK DISTRIBUTION CIRCUIT Description Features · · · · · The IDT6P30006A is a low-power, eight output clock distribution circuit. The device takes a TCXO or , ±100mVpp OUT7 OUT8 MUX 3 SEL IDTTM CLOCK DISTRIBUTION CIRCUIT GND 1 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS OE4 OE1 SEL Pin , ground. IDTTM CLOCK DISTRIBUTION CIRCUIT Pin Description 2 IDT6P30006A REV C 111009 Integrated Device Technology
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Abstract: DATASHEET IDT6T39007A CLOCK DISTRIBUTION CIRCUIT Description Features The IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or 1.8 V to 2.5 V , MUX VDDO1 PWRCTRL_CLK1 VDDO2 PWRCTRL_CLK2 2 GND IDT® CLOCK DISTRIBUTION CIRCUIT 1 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Primary Input , DISTRIBUTION CIRCUIT 2 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT Integrated Device Technology
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Abstract: Distribution (>10GHz) 1:4 Ultra High Performance Clock Distribution (>10GHz) 1:10 Ultra High Performance Clock Distribution (>6GHz) Differential D Flip-Flop/÷2 Clock Driver with Output Level Select (>10GHz , easy task with a large range of clock distribution, generation and skew management devices. We address , at operating frequencies to 10 GHz and beyond. Our clock distribution portfolio boasts fan-out , . Circuit Diagram for the NBSG111 Advanced Clock Management Products Clock Distribution Device NBSG11 ON Semiconductor
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MC10xxx 10GHz clock oscillator 500MHz Frequency Counter Using MECL MC12095 laser driver, STM-64 NBSG16VS BRD8017/D
Abstract: ECL Clock Distribution Techniques By: Todd Pearson ECL Applications Engineering ABSTRACT This , and distribution networks. Clock skew, the difference in time between "simultaneous" clock transitions , or for the first level device of a nested clock distribution tree. In these two situations the only , propagation delay is relatively large. For designs whose clock distribution networks lie on a single board , the stability of the power busses within the chip. Clock distribution trees by definition always Freescale Semiconductor
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Abstract: Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This , and distribution networks. Clock skew, the difference in time between "simultaneous" clock transitions , large. For designs whose clock distribution networks lie on a single board which utilizes power and , inadequate for the design of the system. Ideally the data sheets for clock distribution devices should , supply levels and the stability of the power busses within the chip. Clock distribution trees by Motorola
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Abstract: A N 1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL , . 1996 10 REV 1 AN1405 ECL Clock Distribution Techniques INTRODUCTION The ever increasing , clock generation and distribution networks. Clock skew, the difference in time between "simultaneous" , temperature coefficient of the propagation delay is relatively large. For designs whose clock distribution , the data sheets for clock distribution devices should include information which will allow designers -
OCR Scan
Abstract: DATASHEET IDT6T39007A CLOCK DISTRIBUTION CIRCUIT Description Features · · · · · The IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or , MUX VDDO1 PWRCTRL_CLK1 VDDO2 PWRCTRL_CLK2 2 GND IDTTM CLOCK DISTRIBUTION CIRCUIT 1 IDT6T39007A REV G 111009 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Primary Input , DISTRIBUTION CIRCUIT 2 IDT6T39007A REV G 111009 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT Integrated Device Technology
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6T39007ANLGI8
Abstract: OW SKEW, 1-TO-16 Systems, Inc. DISTRIBUTION CHIP DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP , -to-16 Differential-to-LVDS Clock Distribution HiPerClockSTM Chip and a member of the HiPerClock S TM family of High , -TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP 1 nQ14 Q14 nQ15 Q15 GND CLK nCLK GND Q0 nQ0 Q1 nQ1 REV. A JULY 30, 2004 ICS8516I ICS8516I Circuit LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP Integrated ICS8516I Systems, Inc. LOW SKEW, 1-TO-16 TSD DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP Integrated Circuit Systems
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700MH MK1491-14 ICS1890 ICS1527 ICS8302-01 ICS280
Abstract: . MC100ES6226 MC100ES6226 1:9 Clock Distribution Buffer 2.5/3.3V Differential LVPECL 1:9 Clock Distribution , differential clock distribution buffer and clock divider. Designed for most demanding clock distribution , , netw ork i ng and telecommunication systems. 2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION , designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6226 are primary clock distribution systems on Integrated Device Technology
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AN1545 MC100ES6226/D MPC92459 199707558G
Abstract: CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK DRIVERS ® Integrated Device Technology, Inc. APPLICATION NOTE-82 CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK , synchronize the transfer of data between system components the clock distribution system is an essential part of the system design. A clock distribution system design that does not take skew into consideration may result in a system with degraded performance and reliability. Designing a clock distribution Integrated Device Technology
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AN-82 IDT49FCT805 IDT49FCT806 transistor x1 49FCT805A 49FCT806 IDT49FCT805A IDT49FCT805/806 AN-49
Abstract: Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This , and distribution networks. Clock skew, the difference in time between "simultaneous" clock transitions , large. For designs whose clock distribution networks lie on a single board which utilizes power and , inadequate for the design of the system. Ideally the data sheets for clock distribution devices should , supply levels and the stability of the power busses within the chip. Clock distribution trees by Motorola
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Abstract: High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 APPLICATION , . 14 High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 , high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loop , application note will be on Clock Distribution chips specifically designed for use with Synchronous DRAMs , Phase-Lock Loop Clock Distribution for Synchronous DRAM applications Distributes one clock to multiple Texas Instruments
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CDC516 CDC2516 2516 memory abstract for 4g technology CDC2509 CDC2510 CDC509 SLMA003A 500E-12 400E-12 300E-12 200E-12
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