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Part Manufacturer Description PDF & SAMPLES
SCAN92LV090VEHX/NOPB Texas Instruments 9 Channel Bus LVDS Transceiver w/ Boundary SCAN 64-LQFP -40 to 85
SCANSTA111SMX Texas Instruments Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port 49-NFBGA -40 to 85
SCAN92LV090SLC Texas Instruments 9 Channel Bus LVDS Transceiver w/ Boundary SCAN 64-NFBGA -40 to 85
SCANSTA111SM/NOPB Texas Instruments Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port 49-NFBGA -40 to 85
SCANSTA111SMX/NOPB Texas Instruments Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port 49-NFBGA -40 to 85
SCANSTA111SM Texas Instruments Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port 49-NFBGA -40 to 85

"CT scan"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: AS xDS DU R/W CT OR , IN C.2 006 Scan Register contents latched onto processor pins , BOUNDARY SCAN INSTRUCTIONS AND DATA CT OR , IN C.2 006 The JTAG operation itself assumes , Order this document by AN1264/D CT OR , IN C.2 006 Microprocessor and Memory , , simply changing the two scan register input files makes the programmer equally applicable to any (well , CT OR , IN C.2 006 An overview of the JTAG Flash programmer concept is provided in Figure 1 Motorola
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AN1264 AM29F010 74ACT04 motorola ar MC68307 MC68306 LS05 CPU32 MC683 MCF52
Abstract: Q OUT1 TEST_SO CT CLK2 D Scan Testability Figure 3. Design with Scan - Incorrect , CT CT TEST_MODE IN3 D Q OUT3 Figure 12. Design with Embedded Clock­Modified for Scan , Scan Testability Guidelines Introduction This document is intended to provide recommendations for designs where testability is achieved using scan methodology. These recommendations are useful: · to avoid any need for delay lines for scan test purposes Cell-based ASIC Application Note · to avoid Atmel
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SFF2 VHDL 12/99/0M
Abstract: SRAMs 209-Bump BGA Commercial Temp Industrial Temp Features Functional Description ct SCD , /Dual Cycle Deselect selectable · IEEE 1149.1 JTAG-compatible Boundary Scan · ZQ mode pin for , VDD VDDQ VDDQ DQPA DQPE Ne w VSS me nd ed for Rev 10 ct 1 VSS , sco nt inu ed Pr od u ct Symbol Data Input and Output pins Clock Input Signal , I BW I Scan Test Mode Select I Scan Test Data In O Scan Test Data Out I GSI Technology
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GS816272C GS816272 GS816272C-133 GS816272C-150 GS816272C-150I GS816272C-166 209-B
Abstract: ct Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command , Description ct The GS8162Z72C may be configured by the user to operate in Pipeline or Flow Through mode , ZQ mode pin for user-selectable high/low output drive · IEEE 1149.1 JTAG-compatible Boundary Scan · , VDD VDD VDD VDDQ VDDQ DQPA DQPE Ne w VSS me nd ed for Rev 10 ct , (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test GSI Technology
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gs816 GS8162Z72C-200 GS8162Z72C-166I GS8162Z72C-166 GS8162Z72C-150I GS8162Z72C-150 8162Z18
Abstract: inu ed Pr od u ct Boundary Scan Register The Boundary Scan Register is a collection of flip , Update-IR state. nâ'" Di sco nt inu ed Pr od u ct Alternately, the Boundary Scan Register , operation â'¢ Single/Dual Cycle Deselect selectable â'¢ IEEE 1149.1 JTAG-compatible Boundary Scan â'¢ ZQ , applications â'¢ JEDEC-standard 119-bump BGA package â'¢ RoHS-compliant 119-bump BGA package available ct , : 1.04 9/2008 ct 2 nâ'" Di sco nt inu ed Pr od u 1 2/30 Specifications cited GSI Technology
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GS8162 8162V
Abstract: I CMOS Pull-High 11~18 OF7~OF0 O NMOS Drive for key scan 19 CT O CMOS , Drive for key scan 23 CT O CMOS Generates output transmission code 24 VDD I , operation) 3V IOH High-Level Output Current CT 3V VOH=2V ­5 ­10 Low-Level Output Current CT 3V VOL=0.9V 0.3 0.8 Low-Level Output Current DATA 3V VOL=0.9V 1 4 , Description Transmission Code Scan Output 0 0 0 0 0 1 0 1 0 OF3 0 1 1 Holtek
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HT6240-001 HT6240002 HT6240-002 CT scan circuit HT6240 HT6240-001/HT6240-002
Abstract: '" Di sco nt inu ed Pr od u · ct JTAG TAP Block Diagram Boundary Scan Register  , with flow through NtRAMâ"¢, NoBLâ"¢ and ZBTâ"¢ SRAMs â'¢ IEEE 1149.1 JTAG-compatible Boundary Scan â , â'¢ RoHS-compliant 165-bump BGA package available ct Features 5.5 nsâ'"7.5 ns 2.5 V or 3.3 , Pr od u ct 1 De sig 165 Bump BGAâ'"x18 Commom I/Oâ'"Top View (Package D) VSS NC , sco nt inu ed Pr od u NC De sig ct 1 VSS NC NC NC VSS VDDQ NC GSI Technology
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GS8161FZ18/32/36BD 165-B 8161FZ
Abstract: Boundary Scan · 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package · Pin-compatible with future 36Mb , advertised index depth (e.g., the 1M x 18 has a 512K addressable index). ct GS8180Q18/36D-200/167/133 , documentation see http://www.gsitechnology.com. ct NC VDDQ © 2002, GSI Technology GS8180Q18/36D-200 , without notice. For latest documentation see http://www.gsitechnology.com. ct VDDQ NC/SA (36Mb , Supply Input ct Active Low Active Low Active Low Active High Active Low Active High Active Low GSI Technology
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GS818 GS8180Q18/36D-200/167/133/100 GS8180Q18 GS8180Q18D-200 GS8180Q18D-167 GS8180Q18D-133 GS8180Q18D-100
Abstract: output drive strength · IEEE 1149.1 JTAG-compliant Boundary Scan · Pin-compatible with present 9Mb, 18Mb , without notice. For latest documentation see http://www.gsitechnology.com. ct © 2005, GSI Technology , SRAM-Top View ct 10 SA NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 0.5 ns 11 CQ DQ8 , subject to change without notice. For latest documentation see http://www.gsitechnology.com. ct NC , . ct NC VDDQ © 2005, GSI Technology GS8662T08/09/18/36E-250/200/167 8M x 8 SigmaDDR-II GSI Technology
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GS8662T08/09/18/36E GS8662T
Abstract: Boundary Scan · 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package · Pin-compatible with future 36Mb , ://www.gsitechnology.com. ct © 2002, GSI Technology GS8180QV18/36D-200/167/133/100 1M x 18 SigmaQuad SRAM-Top , . ct NC VDDQ © 2002, GSI Technology GS8180QV18/36D-200/167/133/100 512K x 36 SigmaQuad , http://www.gsitechnology.com. ct VDDQ D17 © 2002, GSI Technology GS8180QV18/36D-200/167 , Supply ct Active Low Active Low Active Low Active High Active Low Active High Active Low - - GSI Technology
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GS8180QV18 165-P GS8180QV36GD-200I GS8180QV36GD-167I GS8180QV36GD-133I GS8180QV36GD-100I
Abstract: ://www.gsitechnology.com. ct © 2003, GSI Technology Preliminary GS8182S18D-250/200/167 Boundary Scan Register , mode pin for programmable output drive strength · IEEE 1149.1 JTAG-compliant Boundary Scan · 165 , http://www.gsitechnology.com. ct © 2003, GSI Technology Preliminary GS8182S18D-250/200/167 , are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ct , Input Input Input - - Output Output Input Output Supply Supply Supply Output ct Active Low GSI Technology
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GS8182S18 8182S 333MH
Abstract: Boundary Scan · 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package · Pin-compatible with future 36Mb , to change without notice. For latest documentation see http://www.gsitechnology.com. ct © 2003 , . ct VDDQ SA © 2003, GSI Technology GS8182Q18/36D-200/167/133 512K x 36 SigmaQuad SRAM-Top , http://www.gsitechnology.com. ct VDDQ D17 © 2003, GSI Technology GS8182Q18/36D-200/167 , Input Input Input Output Input Input - Input Output Input Output Output Supply Supply Supply ct GSI Technology
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200MH 133MH GS8182Q18 8182Q
Abstract: inu ed Pr od u ct Symbol I Scan Test Data In O Scan Test Data Out I Scan , ed Pr od u · ct JTAG TAP Block Diagram Boundary Scan Register · 1 · · 2 , selectable · IEEE 1149.1 JTAG-compatible Boundary Scan · ZQ mode pin for user-selectable high/low output , mode of operation using the SCD mode input. ct Features 250 MHz­225 MHz 2.5 V or 3.3 V VDD , w VSS me nd ed for Rev 10 ct 1 No t Re co m 11 x 19 Bump BGA-14 x 22 GSI Technology
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GS816273C GS816273 GS816273C-225 GS816273C-225I GS816273C-250 GS816273C-250I GS816273C-250/225
Abstract: pipelines · ZQ mode pin for programmable output drive strength · IEEE 1149.1 JTAG-compliant Boundary Scan · , without notice. For latest documentation see http://www.gsitechnology.com. ct © 2003, GSI Technology , . For latest documentation see http://www.gsitechnology.com. ct VDDQ SA © 2003, GSI Technology , Supply ct Active Low Active Low Active Low Active High Active Low Active High Active Low - - , . ct © 2003, GSI Technology GS8182D18D-200/167 SigmaQuad-II B4 SRAM DDR Read The status of the GSI Technology
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gs8182d18d200 GS8182D18 36D-300T 8182D
Abstract: inputs · IEEE 1149.1 JTAG-compliant Serial Boundary Scan · 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA , . ct Features 200 MHz­333 MHz 1.8 V VDD 1.8 V I/O n- Di sco nt inu ed Pr od u , inu ed Pr od u 2 De sig 1 ct 512K x 36 Common I/O-Top View (Package C) Note , TDI Test Data In TDO Test Data Out TMS n- Di sco nt inu ed Pr od u ct , -333/300/250/200 Read Operations n- Di sco nt inu ed Pr od u ct Double Data Rate Read GSI Technology
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GS8170DD36 GS8170DD36C-333 GS8170DD36C-300 GS8170DD36C-250 GS8170DD36C-300I GS8170DD36C-333I GS8170DD36C-333/300/250/200 GS8170DD36C-200I
Abstract: 119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features Functional Description ct , JTAG-compatible Boundary Scan â'¢ ZQ mode pin for user-selectable high/low output drive â'¢ 2.5 V +10%/â , me nd ed for ct 1 No t Re co m 11 x 19 Bump BGAâ'"14 x 22 mm2 Bodyâ'"1 mm Bump , for Burst address counter advance enable; active low Re co m MCL ct Symbol Address , Scan Test Mode Select I Scan Test Data In TDO O Scan Test Data Out TCK I Scan GSI Technology
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GS832218 209-P GS832218/36/72 165-BGA
Abstract: Scan Input U A u to Stop In pu t DESCRIPTION The ECONOMEGA Digital Tuning system is a three chip , u t C Load In pu t C in p u t O u tp u t Se lect C 8 12 16 P rogram S e'e ct In pu t C 26 D V , EAROM Control Chip Clock +128 When connected to V Ss selects Band 1 and initiates scan. (Connect to V s s to start scan). When connected to V s s selects Band 2 and initiates scan. (Connect to V s s for , scan. I Connect to V Ss for When connected to V s s selects Band 4 | Auto Bandswitching. and initiates -
OCR Scan
AY-3-8203 AY-5-8203 MEM4956 SAA1025 AY38203 AY3-8203 earom ER1400
Abstract: Boundary Scan · 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package · Pin-compatible with future 36Mb , latest documentation see http://www.gsitechnology.com. ct © 2002, GSI Technology GS8180D18D , documentation see http://www.gsitechnology.com. ct NC VDDQ © 2002, GSI Technology GS8180D18D-250/200 , Input Input - Input Output Supply Supply Supply ct Active Low Active Low Active Low Active , nt inu ed Pr od u Write C Read D C D E C C+1 C+2 ct Write E NOP me nd ed for Ne w GSI Technology
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GS8180D18D-250/200/167/133/100 GS8180D18 18D-200T
Abstract: · nâ'" Di sco nt inu ed Pr od u · ct JTAG TAP Block Diagram Boundary Scan Register , -, & 209-Pin BGA Commercial Temp Industrial Temp Features Functional Description ct SCD and , JTAG-compatible Boundary Scan â'¢ ZQ mode pin for user-selectable high/low output drive â'¢ 1.8 V or 2.5 V core , sco nt inu ed Pr od u De sig Ne w me nd ed for ct 1 No t Re co m , co m MCL ct Symbol Address Strobe (Processor, Cache Controller); active low Sleep Mode GSI Technology
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GS832218/36/72- 8322V
Abstract: Boundary Scan · 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package · Pin-compatible with future 36Mb , documentation see http://www.gsitechnology.com. ct © 2002, GSI Technology GS8180DV18D-250/200/167/133 , documentation see http://www.gsitechnology.com. ct NC VDDQ © 2002, GSI Technology GS8180DV18D-250/200 , Input Input - Input Output Supply Supply Supply ct Active Low Active Low Active Low Active , E C D E C C C+1 C+1 C+2 C+2 A+3 B B+1 B+2 B+3 ct C+3 C+3 NOP K K Address R W BWx D C C Q A GSI Technology
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GS8180DV18D-250/200/167/133/100 GS8180DV18 GS8180DV18GD-200I GS8180DV18GD-167I GS8180DV18GD-133I GS8180DV18GD-100I
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