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Part Manufacturer Description PDF & SAMPLES
TMS380BIU-XTPQ Texas Instruments BUS Interface Unit 100-BQFP
UCC5614Z Texas Instruments 9-LINE 110ohm SCSI BUS TERMINATOR, PZIP16
UCC5622MWP Texas Instruments 27-LINE 110ohm SCSI BUS TERMINATOR, PDSO44
UCC5672BPW883B Texas Instruments 9-LINE 110ohm SCSI BUS TERMINATOR

"Bus Interfaces"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: . A20 (3) Input Address input to flash memory. DQ0 Input/Output Data bus that interfaces with flash memory and the controller. DQ1 Input/Output Data bus that interfaces with flash memory and the controller. DQ2 Input/Output Data bus that interfaces with flash memory and the controller. DQ3 Input/Output Data bus that interfaces with flash memory and the controller. DQ4 Input/Output Data bus that interfaces with flash memory and the controller. DQ5 Input/Output Data bus that interfaces with flash Altera
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100-P
Abstract: . Address input to flash memory. Data bus that interfaces with flash memory and the controller. 100 , interfaces with flash memory and the controller. Data bus that interfaces with flash memory and the controller. Data bus that interfaces with flash memory and the controller. Data bus that interfaces with flash memory and the controller. Data bus that interfaces with flash memory and the controller. Data bus that interfaces with flash memory and the controller. Data bus that interfaces with flash memory and Altera
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flash controller F-A15 C-A15 F-A16 C-A16
Abstract: memory. 47 Address input to flash memory. 46 Address input to flash memory. 36 Data bus that interfaces with flash memory and the controller. 81 Data bus that interfaces with flash memory and the controller. 83 Data bus that interfaces with flash memory and the controller. 86 Data bus that interfaces with flash memory and the controller. 89 Data bus that interfaces with flash memory and the controller. 93 , Description Pin Type DQ5 Input/Output Data bus that interfaces with flash memory and the controller. DQ6 Input Altera
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Abstract: interfaces with flash memory and the controller. DQ1 Input/Output Data bus that interfaces with flash memory and the controller. DQ2 Input/Output Data bus that interfaces with flash memory and the controller. DQ3 Input/Output Data bus that interfaces with flash memory and the controller. DQ4 Input/Output Data bus that interfaces with flash memory and the controller. DQ5 Input/Output Data bus that interfaces with flash memory and the controller. DQ6 Input/Output Data bus that interfaces with flash Altera
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Abstract: Input/Output Data bus that interfaces with flash memory and the controller. DQ1 Input/Output Data bus that interfaces with flash memory and the controller. DQ2 Input/Output Data bus that interfaces with flash memory and the controller. DQ3 Input/Output Data bus that interfaces with flash memory and the controller. DQ4 Input/Output Data bus that interfaces with flash memory and the controller. DQ5 Input/Output Data bus that interfaces with flash memory and the controller. DQ6 Input/Output Altera
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Abstract: ) Input Address input to flash memory. DQ0 Input/Output Data bus that interfaces with flash memory and the controller. DQ1 Input/Output Data bus that interfaces with flash memory and the controller. DQ2 Input/Output Data bus that interfaces with flash memory and the controller. DQ3 Input/Output Data bus that interfaces with flash memory and the controller. DQ4 Input/Output Data bus that interfaces with flash memory and the controller. DQ5 Input/Output Data bus that interfaces with flash Altera
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Abstract: through 3-wire interfaces. The inter-IC (I²C) and System Management Bus (SMBusTM) standards communicate , applications. Two-wire interfaces also allow you to connect multiple slaves on the same bus without needing , interfaces. The I²C bus functions down to DC and does not timeout due to bus inactivity. SMBus interfaces can , resistors, noise, master, slave Jun 21, 2007 APPLICATION NOTE 4024 SPI/I²C Bus Lines Control Multiple Peripherals Abstract: This application note compares two common serial, digital interfaces used Maxim Integrated Products
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MAX5115 MAX6641 MAX7319 MAXQ2000 APP4024 ic 4024 DIN 3967 Serial communication I2C in basics disadvantages of microcontroller CMOS 4024 applications AN4024
Abstract: : bus interfaces This manual describes the ST40 family system architecture. It is split into four , Bus Interfaces - ADCS 7181720. ST40 System Architecture - Volume 3 Video Devices - ADCS 7225754 , Architecture, Volume 2: Bus Interfaces PRELIMINARY DATA iv 1.3.8 1.3.9 1.3.10 1.4 Caution when , STMicroelectronics SH-4, ST40 System Architecture, Volume 2: Bus Interfaces 68 70 72 73 ADCS 7181720G , SH-4, ST40 System Architecture, Volume 2: Bus Interfaces PRELIMINARY DATA vi 2.9.8 2.9.9 STMicroelectronics
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UM0340 ST40 TOOLSET ADCS 7153464 ADCS 7225754 ST40 manual ADCS 7182230 ADCS 7181720
Abstract: PCI, PXI, and ISA CAN interfaces to have their transceivers either internally powered or bus powered , CAN Interfaces CAN Interfaces PCI-CAN Series, PXI-846x Series, AT-CAN Series, PCMCIA-CAN , PXI-846x modules work in PXI real-time systems · RTSI bus for synchronization with National , Software · NI LabVIEW · NI Measurement Studio · C/C+ Software · Bus monitor utility · LabVIEW VIs for - J1939 - Interface to automotive database Overview National Instruments CAN interfaces are -
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80386EX PXI-8461 PXI-8462 ISO 11898 777357 iso 11519 j1939 connector PXI-846 2000/M 2000/NT/M PXI-8460
Abstract: . 56 Bus Interfaces . 57 About Bus Interfaces. 57 Using Bus Interfaces in SmartDesign . 59 4 SmartDesign v8.4 User's Guide Table of Contents Adding Bus Interfaces to , Bus Interfaces to SmartDesign Instances Actel
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grid tie inverter schematic diagram grid tie inverter schematics grid tie inverter schematic off grid inverter schematics grid tie inverter schematic grid tie inverter
Abstract: Bus error logging · Hardware timestamping ­ 1 us resolution CAN Interfaces · Philips SJA1000 CAN controller · Transmit/receive 100 percent bus load at 1 Mb/s · ISO 11898 compliance for standard (11bit , , even under 100 percent bus loads. CAN Interfaces USB-847x CAN interfaces feature the , CAN and LIN Interfaces for Hi-Speed USB NI USB-8472, NI USB-8472s, NI USB-8473, NI USB-8473s, NI USB-8476, NI USB-8476s, · 1-port interfaces for high-speed CAN, low-speed/fault-tolerant CAN, and National Instruments
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ATA6620 TJA1054AT TJA1041 ni 8476 192017-02 ni USB-8476 847X USB-8476s USB-8473s J2602 2008-9328-151-101-D
Abstract: 2­8 Chapter 2: System Interconnect Fabric for Memory-Mapped Interfaces Dynamic Bus Sizing and , 2. System Interconnect Fabric for Memory-Mapped Interfaces QII54003-10.0.0 The system interconnect fabric for memory-mapped interfaces is a high-bandwidth interconnect structure for connecting , less logic, provides greater flexibility, and higher throughput than a typical shared system bus. It is a cross-connect fabric and not a tristated or time domain multiplexed bus. This chapter describes Altera
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QII54003
Abstract: physical interfaces and networking protocols for high bandwidth connectivity and throughput. by Rina Raman , speed of processor but by the limits of the I/O bus. While delivering greater bandwidth, numerous , Virtex-II devices are designed to support many signaling standards, including essential interfaces to high , standards ­ including the traditional switching standards of LVCMOS (Low Voltage CMOS), memory interfaces of , pins and/or larger bus widths. This has made the traditional I/O standards more "pin-intensive." Xilinx
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advanced graphics port OC-192
Abstract: Integrated analog/digital device that interfaces a UTOPIA L2 bus to a serial backplane with optional 1:1 , without UTOPIA bus interfaces: optionally provides cell delineation (I.432) across 16 clock and data , extension" capability. · Interfaces to two S/UNI-DUPLEX devices to create a 1:1 protected bus extension , bandwidth (excludes system overhead) of 186 Mb/s. PHY/FRAMER INTERFACES LVDS TRANSMIT DIRECTION One of three modes can be selected: · 8/16 bit, 33 MHz UTOPIA L2 bus master (also supports expanded PMC-Sierra
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PM7350 PM7351 CRC32 PMC-990147
Abstract: analog station interfaces. The CT Bus ASIC (CT812) delivers full master/slave H.100 capabilities as , station interfaces and resources on which to build highly scalable systems. DISI16R2, DISI24R2, and , connectivity for up to 16, 24, or 32 station interfaces and include conferencing, voice play/record, tone , interfaces available on one board. These boards can be combined with other network interface and resource , Caller ID or Call Waiting Figure 1. Integrated Station Interface Board Configuration CT Bus/H Intel
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DISI32R2 68pin SCSI connector RJ11 patch panel RJ21X CBLTAC0X32 EBZUSA-43111-CE-T fsk arm dtmf
Abstract: Bus O-Bit Interfaces External Alarm Interfaces Control Signals POH Interfaces LINE SIDE , (3) Transmit Interfaces (3) (Rail, NRZ) Add Bus Microprocessor Interface Alarm Indication , STS-3/STS-1 - E3 to/from STM-1/TUG-3 · SDH/SONET bus access: - Byte-wide drop and Add buses - Drop bus timing mode (Add bus timing derived from Drop bus) - Add bus timing mode (independent timing for drop/Add , -1 SPE SDH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an TranSwitch
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TXC-03453 TXC-06103 TXC-02030 TXC-02302B TXC-03001B TXC-03003B
Abstract: ), dual serial peripheral interface (SPI), PCI interfaces and Universal Serial Bus (USB) interface (USB , interfaces and Universal Serial Bus (USB) interface (USB 2.0 full/low speed compatible). Integrated , · TDM Up to 4 TDM interfaces Up to 256 channels at 16 Mbps on a single interface Up to 4 clear channel T3/E3 Up to 8 TDM interfaces Up to 256 channels at 16 Mbps on a single interface Up to 8 , bus Integrated Communications Processors MPC8360E PowerQUICCTM II Pro Family Overview Freescale Semiconductor
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MPC8358E MPC8360 MPC8358 private automatic branch exchange 32-bit microcontrollers powerful pabx systems Multi-Channel hdlc Controller OC-12
Abstract: MachXOTM: Optimized Programmable Devices for Bus Interfaces, Bridges and Control A Lattice , Bus Interfaces, Bridges and Control A Lattice Semiconductor White Paper Requirements for Bus , Strengths of CPLD and FPGA Approaches 3 MachXO: Optimized Programmable Devices for Bus Interfaces , the critical set-up and clock-to-out times often associated with bus interfaces. Clearly, the , Programmable Devices for Bus Interfaces, Bridges and Control A Lattice Semiconductor White Paper fixes Lattice Semiconductor
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14X14 17X17 19X19 Bus Interfaces Lattice MachXO 2 Product Family 100-TQ 144-TQ 20X20
Abstract: SCSI bus protocol. The firmware provides two interfaces to the host system: the command interface and , processor for SCSI initiator and target applications. This device interfaces the PCI bus to two Ultra3 SCSI , 12160A interfaces consist of the 64-bit PCI bus interface, two SCSI interfaces, RISC interface, BIOS PROM , of 528 Mbytes/sec over the PCI bus: 66-MHz, 64-bit PCI host bus interface 33-MHz, 64-bit PCI host bus interface Compliance with PCI Local Bus Specification rev 2.1 Compliance with ANSI draft T10 -
OCR Scan
SCSI Parallel Interfaces QLogic Qlogic Intelligent SCSI Processor qlogic ISP12160A ISP12160A/33 ISP12160A/66 ISP12160A 66-MH 33-MH T10/1302D
Abstract: single-chip, highly integrated, bus master, dual-channel SCSI I/O processor for SCSI initiator and target applications. This device interfaces the 64-bit PCI bus to two Ultra SCSI buses and contains an onboard RISC , 64-bit PCI bus interface, two SCSI interfaces, and the RISC interface. Pins that support these , s s s s s Product Description 64-bit PCI host bus interface, complaint with PCI Local Bus , CHANNEL IOCBS FIFO 512-BYTE DATA FIFO HOST SOFTWARE DRIVER SXP 1 64-BIT PCI BUS -
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ISP1240 block diagram of risc processor qlogic isp1040 QLOGIC isp SCSI controller "external fifo" X3T10/1071D X3T10/855D ISP1040
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