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"Bit Shift Register"

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Abstract: look-up table (LUT) as a 16-bit shift register without using the flip-flops available in each slice , register is needed. Each CLB resource can be configured using the 8 LUTs as a 128-bit shift register. This , register, and each bit is shifted to the next highest bit position. In a cascadable shift register , Q15 Q31 Q15 SRLC16E SRLC16E 32-bit Shift Register MUXF6 D 4 A[3:0] CE Q 4 A B C D Q15 SRLC16E MUXF5 D 4 A[3:0] CE Q Q15 Q63 SRLC16E 64-bit Shift Register UG002_C2 Xilinx
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SRL16 verilog code for 8 bit shift register verilog code for 64 32 bit register verilog code for shift register VHDL of 4-BIT LEFT SHIFT REGISTER vhdl code for 8 bit shift register verilog code for 4 bit shift register SRLC16
Abstract: Bipolar-TTL Bipolar-TTL FACT Dual 8-Bit Shift Register 8-Bit Multiple Port Register 8-Input Universal Shift , HCT CMOS 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear 8-Bit Parallel-Out Serial Shift Register 8-Bit Serial-in/Parallel-out Shift Register 8-Bit Serial-in/Parallel-out Shift , Shift Register 8-Bit Parallel In/Serial Out Shift Register 5 5 MM74C165 MM74HC165 74C CMOS HC CMOS Parallel-Load 8-Bit Shift Register Parallel-in/Serial-out 8-Bit Shift Register 5 other 5 Fairchild Semiconductor
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16 bit universal shift register 16-bit universal shift register 74LCX32646 8bit shift DM93L28 DM93L38 74AC299 74VHC164 DM74LS164 MM74C164
Abstract: for the look-up tables where they are used as 16-bit shift registers. Using this Shift Register LUT , the cascading of any number of 16-bit shift registers to create whatever size shift register is needed. Each CLB resource can be configured using four of the eight LUTs as a 64-bit shift register , as the output, emulating an 8-bit shift register. Note that since the address lines control the mux , associated flip-flop that makes up the overall logic cell. The addressable bit of the shift register can be Xilinx
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vhdl code 16 bit LFSR VHDL 32-bit pn sequence generator verilog code 16 bit LFSR vhdl code for pn sequence generator fpga cdma by vhdl examples vhdl code for rs232 receiver using fpga XAPP465 SRL16E RS232 DS228
Abstract: ) register. TEST DATA IN SELECT MUX A 8-BIT JTAG IR INSTRUCTION (SHIFT) REGISTER B MSB 7 , STATUS (SHIFT) REGISTER, OSR 1 BIT 0 LSB 0 LSB 0 LSB 0 LSB TEST DATA OUT , (OCR). State: Shift-DR Shift 0s into the 32-bit OnCE control register (OCR). The debug request (DR , Figure 1 and Figure 2 show the 8-bit JTAG (Joint Test Action Group) instruction register, the OnCE command register (OCMR), and the OnCE (JTAG) data registers in the MMC20xx. Writing 0x3 to the 8-bit Motorola
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AN1817 MMC2003 M200 motorola application note AN1817/D MMC20 MMX20 MMC2001R
Abstract: PD4990A OE Don't use 8 bit B40 to B47 40 bit Shift Register CLK DATA IN N-ch Open Drain , 52 bit Shift Register48 bit Shift Register 52bit Shift Register 52 bit MSB LSB 48 bit , B0 C'3 C'2 C'1 C'0 48bit Shift Register 48 bit Time Counter Shift Register Time Counter B0 D0 B1 D1 B3 48 bit Time Counter Shift Register BCD , PD4990AShift RegisterLSBB0 48 bit Shift RegisterB40B47 48 bit Shift Register Last Data First NEC
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S12828JJ4V0UM00 TP4096 CI 74ls07 S12828J PD1990 STB-HL PD4990A24 161HCHBCD PD4990AECRPPC 161HCH FAX044548-7900
Abstract: cascading of any number of 16-bit shift registers to create whatever size shift register is needed. Each CLB resource can be configured using the 8 LUTs as a 128-bit shift register. This section provides generic VHDL , register, and each bit is shifted to the next highest bit position. In a cascadable shift register , A[3:0] CE Q15 Q31 Q15 SRLC16E SRLC16E Q 32-bit Shift Register MUXF6 D 4 A[3:0] CE Q Q15 SRLC16E MUXF5 D 4 A[3:0] CE Q Q15 Q63 SRLC16E 64-bit Shift Register Xilinx
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RAM16X1S verilog code for 8 bit fifo register vhdl code for 8 bit register vhdl code for 4 bit shift register SRLC32E SRLC64E vhdl code for shift register UG012
Abstract: buffer between the internal data bus and the transmit shift register. Writing a logic 1 to the TE bit in , shift register. A logic 0 start bit automatically goes into the least significant bit position of the shift register, and a logic 1 stop bit goes into the most significant bit position. When the data in the , SBK bit in SCCR2 loads the shift register with a break character. A break character contains all logic , . After software clears the SBK bit, the shift register finishes transmitting the last break character and -
OCR Scan
10 Bit Shift Register MC68HC05C4A
Abstract: mode 3: Shift register, fixed baud rate (fOSC/12) 8-bit UART, variable baud rate 9-bit UART, fixed , to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags , . One bit time later, DATA is activated, which enables the output bit of the transmit shift register to , shift out to the left. When the start bit arrives at the leftmost position in the shift register, (which in mode 1 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and Siemens
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SBUF
Abstract: Bit PIPO Shift Register 4 Bit PIPO Shift Register 8 Bit PIPO Shift Register (3-State) 8 Bit PIPO Shift Register (3-State) 8 Bit Shift Register Latch (3-State) 8 Bit Latch Shift Register 4 Word x 4 Bit Register File (3-State) 8 Bit SIPO Shift Register Latch (3-State) 4034B 4094B LS164 HC164 HCT164 , SELECTION GUIDE REGISTER Type Number M54/74 HC164 HCT164 HC165 HCT165 HC166 HC173 HC194 HC195 HC299 HC323 HC595 HC597 HC670 HC4094 8 8 8 8 8 Bit Bit Bit Bit Bit SIPO PISO PISO PISO PISO Shift Shift -
OCR Scan
LS165 LS173 4021B CMOS 4000B shift register sipo LS166 LS194 LS195 LS299
Abstract: static shift register Dual 4-bit static shift register Quadruple bilateral switches 5-stage Johnson , universal shift register 4-bit universal shift register 14-stage binary counter Triple 3-input NAND gate 7 , Programmable timer Dual 1-of-4 decoder/demultiplexer 1-to-64 bit variable length shift register 4-bit magnitude , -stage static shift register 18-stage static shift register Dual Dual Dual 4-bit 4-bit complementary pair and , flip-flop Dual D-type flip-flop Dual D-type flip-flop 8-bit static shift register 8-bit static shift -
OCR Scan
HEC4047BDB hef4071bp HEC4051B HEF4752 7-stage frequency divider HEF4059BP HEF40374BD HEC4001BDB HEC40 HEC4007UBDB HEC40097BDB HEC40098BDB HEC4011BDB
Abstract: Shift Register Start Bit Detect Parity Check Transmitter Shift Register Char Detect , input to the Shift Register and the start bit detection circuitry. (R) RCVR Data Shift Clock , start bit into the Receiver Shift Register at the center of the bit time. Before the shift actually , pin one bit per master clock cycle. Loading data into the shift register initiates the transfer. In , Mode Register bit 6 is set to 1, the UART is enabled and T0 automatically becomes the bit rate ZiLOG
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UM97Z8X0104
Abstract: : Serial mode 1: Serial mode 2: Serial mode 3: Shift register mode, fixed baud rate 8-bit UART , bit position of the transmit shift register and tells the TX control block to commence a transmission , later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first , out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX control block to do one last shift. The signal to load Siemens
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515S
Abstract: of bits shifted. In general usage, the Shift Register component functions as a 2- to 32-bit shift , the Shift Register interrupts. None Bit field containing the status for the selected interrupt sources , PSoC CreatorTM Component Datasheet ® Shift Register (ShiftReg) 2.20 Features Adjustable shift register size: 2 to 32 bits Simultaneous shift in and shift out Right shift or left shift Reset input forces shift register to all 0s Shift register value readable by CPU or DMA Shift register value Cypress Semiconductor
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74597 psoc example projects 74166 applications 74166 universal shift register
Abstract: machine decodes 8-bit commands specified in the OnCE Command Register (OCR) and controls the interaction , indicating that the core has halted. The 24-bit OnCE Status and Control Register (OSC) enables trace mode , the OCR and Table 2 shows the selected OCR registers. Table 1. OnCE Command Register (OCR) Bits Bit , . Table 3. OnCE Status and Control Register (OSCR) Bits Bit Name Description 23­8 Reserved , . Table 4. OnCE Breakpoint Control Register (OBCR) Bits Bit Name 23­12 11­10 Breakpoint 0 and 1 Event Freescale Semiconductor
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AN1839 DSP56300
Abstract: 4-2 4-3 4-4 4-5 4-6 5-1 5-2 Title Page 52 bit Shift Register , bit Shift Register Construction , COMMAND Register 48 Bit Shift Register MPX N-ch OPEN DRAIN DATA OUT CLK DATA IN CS C3 C2 C1 C0 , of register is 52 bit. Fig. 1-1 52 bit Shift Register MSB Command register Tens of years Unit of , of Unit of hours minutes minutes seconds seconds C3' C2' C1' C0' 52 Bit Shift Register D3 D2 D1 NEC
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87AD UPD74HC02 uCOM-87 what is 74LS07 uCOM-75 TTL 74ls07 IEU-1210
Abstract: the input clock shifts each bit, MSB first, of the input data stream through the Shift register , 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 CRC16_MSB: Shift Register DR0 Bit Value 7 6 5 4 3 2 1 0 Shift , API. 8 September 7, 2004 16-Bit CRC Generator CRC16_LSB: Shift Register DR0 Bit Value 7 6 , 14 2 1 X X X X 1 X 0 15 14 13 Shift Register 15 14 2 1 0 Input Data , blocks as a single 16-bit CRC User Module. The Polynomial, Shift, and Seed registers refer to the Cypress Semiconductor
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CRC-CCITT 0xFFFF crc generator CRC-16-CCIT CY8C29/27/24/22 CY8C26/25 CRC-16
Abstract: 7 6 5 4 3 2 1 0 SHIFT REGISTER BITS Notes: 1. When shitting out. bit 7 is the first bit out and , towards bit 7. 7 6 5 4 3 2 1 0 FT SHIFT REGISTER MODE CONTROL 4 3 2 Operation 0 0 0 Disabled 0 0 1 , Counter does not stop the shifting operation. Since Shift Register bit 7 (SR7) is recirculated back into bit 0, the eight bits loaded into the Shift Register will be clocked onto the CB2 line repetitively , . Serial data transfers are provided by a serial-to-parallel/parallel-to-serial shift register. Application -
OCR Scan
G65SC22 65SC22 tns-3 G65SC22-2 G65SC22-1 G65SC22-3 G65SCXXX
Abstract: consists of a 34-bit shift register, a 33-bit latch, and a 33-bit VF tube driver. FEATURES â'¢ Complete , bit read-in stored in a shift register #1, the last data bit read-in is stored in a shift register , bit set to logic 1 ). At the 34th clock pulse, the data is transferred from the shift register to the , Acquisition Terminal 3 Clock Input Clock Terminal 4 Output 1 Output Shift Register 32 5 Output 2 Output Shift Register 21 6 Output 3 Output Shift Register 22 7 Output 4 Output Shift Register 23 8 Otuput 5 -
OCR Scan
MSM5328 33-BIT DIP40-P-600 QFP44-P-910-VK QFJ44-P-S650 0014S77
Abstract: '§ 594 8 bit shift register with 8 bit storage register ï'§ 595 8 bit shift register with 8 bit , SN74AHC138PWR 74AHC138PW MC74VHC138DTR2G 74VHC138MTCX 8-Bit Shift Register 8-Bit Output Register SN74AHC594DR 74AHC594D SN74AHC594PWR 74AHC594PW 8-Bit Shift Register 8-Bit Output Register with 3-state outputs 3-to-8 Line Decoder Demultiplexer TTL compatabile 8-Bit Shift Register 8-Bit Output Register TTL compatabile 8-Bit Shift Register 8-Bit Output Register with 3-state outputs TTL compatabile Diodes
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74HCT 74AHC 74AHCT SO-16 TSSOP-16 74HC/HCT
Abstract: mode 3: Shift register, fixed baud rate (fOSC/12) 8-bit UART, variable baud rate 9-bit UART, fixed , register. The "WRITE to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift , shift register to TXD. The first shift pulse occurs one bit time after that. As data bits shift out to , shift out to the left. When the start bit arrives at the leftmost position in the shift register, (which in mode 1 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and Siemens
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