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Part Manufacturer Description PDF & SAMPLES
EP9312-IBZ Cirrus Logic RISC Microprocessor, 32-Bit, 184MHz, CMOS, PBGA352, 27 X 27 MM, LEAD FREE, PLASTIC, BGA-352
EP9312-CBZ Cirrus Logic RISC Microprocessor, 32-Bit, 200MHz, CMOS, PBGA352, 27 X 27 MM, LEAD FREE, PLASTIC, BGA-352
EP9315-IBZ Cirrus Logic RISC Microprocessor, 32-Bit, 200MHz, CMOS, PBGA352, 27 X 27 MM, LEAD FREE, PLASTIC, MO-151BAL-2, BGA-352
WM8350GEB/RV Cirrus Logic Consumer Circuit, CMOS, PBGA129, 7 X 7 MM, 0.94 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-195, BGA-129
WM8310CGEB/V Cirrus Logic Microprocessor Circuit, CMOS, PBGA169, 7 X 7 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, BGA-169
WM8350GEB/V Cirrus Logic Consumer Circuit, CMOS, PBGA129, 7 X 7 MM, 0.94 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-195, BGA-129

"BGA Rework Practices",

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: , "BGA Rework Practices", Precision PCB Services Inc, 2001 Appendix Top of Package Upper Right , , rework process, and thermal management will be discussed. Note that the reflow and rework guidelines contained in this application note is applicable to standard packages only. For reflow and rework , rework of flip-chip BGAs. www.xilinx.com XAPP426 (v1.3) March 3, 2006 R Implementing Xilinx , sensitive, one should always bake the PCBs and the BGA devices prior to any rework operations. The Xilinx
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XAPP427 WS609 BGA heatsink compressive force solder paste alpha WS609 pcb warpage after reflow BGA PROFILING Alpha WS609
Abstract: temperature cycles from 0 °C to 100 °C for a component sample size of 32+10 (re-work) as defined in IPC , were achieved with void levels less than 25%. c) Rework: Using the worst-case locations from the Xray , black ink for rework. The originally soldered part was de-soldered and replaced with a new part. Table 2: Rework Locations for Lead-Free Assemblies Board # Side Comp Type Rework Location , No Rework 35 CA PolarPAK U10, U12 Rework setup: AirVac DRS24 - BGA rework machine Xilinx
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UG112 XILINX/part marking Hot SMT, FPGA FINE PITCH BGA 456 BALL diode MARKING A1 v34 PC84/PCG84 xilinx part marking xilinx topside marking UG072 UG075
Abstract: Rework Device removal Generally, it is recommended to preheat the PCB to prevent board warp. However , package. A forced air rework tool such as systems offered by Metcal and Hakko, is used to heat all sides , PCB. Identify the proper package orientation and use an automated, or semi-automated, rework system if , placement. Using automated rework equipment is highly recommended. Follow the reflow profile for the paste Xilinx
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pcb footprint FS48, and FSG48 CF1752 smd code v36 reballing XC2VP7 reflow profile BGA reflow guide
Abstract: Grid Array (LGA) Package Rework 1 Introduction This application note describes rework , . . . . . 1 What is LGA? . . . . . . . . . . . . . . . . . . . . . . . . . 3 LGA Rework . . . . . , Surface Mount Technology Land Grid Array (LGA) Package Rework Application Note, Rev. 1.0 2 , . Land Grid Array (LGA) Package Rework Application Note, Rev. 1.0 Freescale Semiconductor 3 What , Rework Application Note, Rev. 1.0 4 Freescale Semiconductor LGA Rework Freescale wirebonded Xilinx
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qfn 3x3 tray dimension HQG160 FGG484 top marking 957 so8 FF1148 PCN #95013
Abstract: solderable surface on the sides and do not require a toe (end) fillet. Rework Guidelines After PCB , joint is exposed and any retouch is limited to this area. For rework of defects underneath the package, the whole package needs to be removed. Bake Although the QFNs are small, the removal and rework can be done manually. Removal and rework of QFNs can be a challenge due to their small size and , as a guideline ­ a starting point in developing a successful rework process. It is recommended Xilinx
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XCDAISY XC5VLX330T-1FF1738I jedec so8 Wire bond gap XC3S400AN-4FG400I XC3SD1800A-4CS484LI XC2S50 PQG208
Abstract: solderable surface on the sides and do not require a toe (end) fillet. Rework Guidelines After PCB , joint is exposed and any retouch is limited to this area. For rework of defects underneath the package, the whole package needs to be removed. Bake Although the QFNs are small, the removal and rework can be done manually. Removal and rework of QFNs can be a challenge due to their small size and , as a guideline ­ a starting point in developing a successful rework process. It is recommended Vishay Siliconix
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IPC-9701 IPC-A-610D ekra e5 SAC387 tamura tlf tamura solder paste AN610
Abstract: variable in size as determined by design. 3. Properly wetted fillet shall be evident. Rework Guidelines , side-fillet solder joint is exposed and any retouch is limited to this area. For rework of defects underneath , removal and rework can be done manually. Removal and rework of QFNs can be a challenge due to their , steps are provided as a guideline ­ a starting point in developing a successful rework process. It , (see Figure 5 and Figure 6). 4 Before rework, bake the PCB assembly at 125°C for at least 24 Integrated Device Technology
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MO-220 qfn 32 land pattern MO-220 5x5mm hakko vqfn 44 land pattern jedec package MO-220 vkkd 199707558G
Abstract: (end) fillet. Rework Guidelines After PCB assembly, the package should be inspected in , . For rework of defects underneath the package, the whole package needs to be removed. Bake Although the QFNs are small, the removal and rework can be done manually. Removal and rework of QFNs can , successful rework process. It is recommended that the board be heated from the bottom side using , above the hot plate can be used (see Figure 5 and Figure 6). 5 Before rework, bake the PCB Freescale Semiconductor
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AN3241 LGA rework AN2920 cte table flip chip substrate Service Manual smd rework station reflow profile FOR LGA COMPONENTS LGA voiding MC1320 MC1321
Abstract: perimeter I/O lands. 3 FIGURE 3. TYPICAL LEAD-TIN SOLDER REFLOW PROFILE Rework Guidelines After , joint is exposed and any retouch is limited to this area. For rework of defects underneath the package, the whole package needs to be removed. Removal and rework of MLFPs can be a challenge due to their , successful rework process. Bake Before rework, bake the PCB assembly at 125oC for at least 4 hours to Intersil
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TB389 J-STD-005 land pattern for DFN qfn 10mm land pattern two tinned touch pads qfn Substrate design guidelines nozzle heater ISO9000
Abstract: the components to the heat of the rework process. Products being removed from boards that have been , for pad size, vias and routing. It is important to implement a keep-out zone around BGAs for rework purposes. The keep-out zone distance is determined by the type of rework equipment to be used. See Section , and rescreen of the PCB. Any deviation can turn into a defect downstream requiring rework and repair , cracking may occur. Rework of BGA Packages SMT yields of BGA packages are very high, but there may Intersil
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IPC-SM-782 Technical Brief TB389 XQFN
Abstract: meant to represent good soldering practices that yield high quality assemblies with minimum rework Intersil
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paste profile solder joint MARK RAY QFN J-STD-001C
Abstract: and routing. It is important to implement a keep-out zone around BGAs for rework purposes. The keep-out zone distance is determined by the type of rework equipment to be used. See Section 14.9.8 for , and rescreen of the PCB. Any deviation can turn into a defect downstream requiring rework and repair , cracking may occur. Rework of BGA Packages SMT yields of BGA packages are very high, but there may still be a possible need for rework of components. Component defects, SMT defects, or other functional Intersil
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j-std-001d
Abstract: completed boards must be accompliished before subjecting the components to the heat of the rework process , , vias and routing. It is important to implement a keep-out zone around BGAs for rework purposes. The keep-out zone distance is determined by the type of rework equipment to be used. See Section 14.9.8 for , and rescreen of the PCB. Any deviation can turn into a defect downstream requiring rework and repair , package delamination or cracking may occur. Rework of BGA Packages SMT yields of BGA packages are Intersil
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thermal pcb guidelines pitch 0.4mm BGA JEDEC J-STD-005 intersil land pattern Intersil cross reference fine BGA thermal profile
Abstract: require a toe (end) fillet. Rework Guidelines After PCB assembly, the package should be inspected in , rework of defects underneath the package, the whole package needs to be removed. Removal and rework of HDAs should be done on a rework station with thermal profile control (see Figure 5). The following steps are provided as a guideline â'" a starting point in developing a successful rework process. Bake Before rework, bake the PCB assembly at +125°C for at least 24 hours to remove any residual Intel
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Intel reflow soldering profile BGA A5832 JEDEC bga 63 tray Intel BGA A4470-01 Lead Free reflow soldering profile BGA
Abstract: sides and do not require a toe (end) fillet. Rework Guidelines Bake After PCB assembly, the , and any retouch is limited to this area. For rework of defects underneath the package, the whole package needs to be removed. Before rework, bake the PCB assembly at +125°C for at least 24 hours to remove any residual moisture. Although the QFNs are small, the removal and rework can be done manually. Removal and rework of QFNs can be a challenge due to their small size and since they are Freescale Semiconductor
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EB635 Solder Paste, Indium, Type 3 reflow soldering profile BGA 5SN3 Soldering guidelines Indalloy 181
Abstract: quality assemblies with minimum rework. It is important to provide a solder reflow profile that matches , . 4.7 Rework and Repair See the Freescale Land Grid Array Package Rework Applications Note , Applications Note (document number: AN2920) Land Grid Array Package Rework Applications Note (document number Intel
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pcb warpage in ipc standard a5764 corner relief carrier tape BGA PROFILING leaded bga 196 land pattern
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