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"AND LOGIC"

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Abstract: Altera's MAX+PLUS II development system, which uses advanced logic synthesis techniques and a heuristic , Array Blocks (LABs). Each logic cell has a register and a programmable-AND/fixed-OR array that is used to build combinatorial logic. The following features increase the flexibility and capacity of MAX , be used and shared by logic cells to implement complex logic functions with maximum flexibility , performance and density from complex programmable logic devices (CPLDs) and field-programmable gate arrays ... Altera
Original
datasheet

14 pages,
107.04 Kb

MAX PLUS II 3 bit design conclusion of programmable array logic 8 bit adder 74684 74157 Multiplexer 74157 application data sheet 74157 21mux TEXT
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Abstract: Altera's MAX+PLUS II development system, which uses advanced logic synthesis techniques and a heuristic , Array Blocks (LABs). Each logic cell has a register and a programmable-AND/fixed-OR array that is used to build combinatorial logic. The following features increase the flexibility and capacity of MAX , be used and shared by logic cells to implement complex logic functions with maximum flexibility , expect varying levels of performance and density from complex programmable logic devices (CPLDs) and ... Altera
Original
datasheet

14 pages,
173.84 Kb

74157 74684 21MUX TEXT
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Abstract: -100% routable and pin-out maintainable High Performance, Flexible Logic Cell -High performance , MHz. Internal logic cell delays are under 2 ns and total input to output combinatorial logic delays , , and discrete logic solutions. A wide range of additional family features complement the pASIC 2 , software solution from design entry, to logic synthesis, to place and route, to simulation. QuickWorks includes VHDL, Verilog, schematic, boolean, and mixed-mode entry with fast and efficient logic synthesis ... Original
datasheet

14 pages,
376.94 Kb

QL2009 QL2007 QL2005 QL2003 schematic of TTL XOR Gates pASIC 2 FPGA FAMILY TEXT
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Abstract: of internal signals using an external logic analyzer and using a minimal number of FPGA I/O pins , ' includes both logic analyzers and oscilloscopes equipped with digital channels, commonly referred to as , shows the Logic Analyzer Interface and the hardware setup. Figure 14­1. Logic Analyzer Interface and , the File menu, click New. The New dialog box opens. Click the Other Files tab and select Logic , Interface File is on the File Menu, click Open, and select the Logic Analyzer Interface File you want to ... Altera
Original
datasheet

18 pages,
361.33 Kb

QII53016-7 mixed signal fpga datasheet free circuit logic analyzer combinational logic circuit project logic analyzer TEXT
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Abstract: White Paper Stratix II Performance and Logic Efficiency Analysis Introduction Pursuing higher , . Research conducted by E. Ahmed and J. Rose concluded that FPGA logic fabric with wider look-up tables , view of the relative performance and logic efficiency comparisons of FPGA logic fabrics with different , less logic to be realized. The native construct of wide LUTs with up to seven inputs and the adaptive nature of the Stratix II logic structure enable high performance and logic efficiency. Therefore, the ... Altera
Original
datasheet

20 pages,
1110.1 Kb

bc 339 2-bit half adder TEXT
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Abstract: Programming and Logic Analysis Tutorial Lattice Semiconductor Corporation 5555 NE Moore Court , the Programming and Logic Analysis Tutorial ii latest version of the relevant information to , Logic Analysis Tutorial iii Programming and Logic Analysis Tutorial iv Contents Programming and Logic Analysis Tutorial 1 Introduction 1 Learning Objectives 1 Time to Complete This , Project Summary Glossary 45 45 Recommended Reference Materials Programming and Logic Analysis ... Original
datasheet

54 pages,
783.49 Kb

Supercool BOX-27 MachXO sysIO Usage Guide LFEC20E-5F484C LFEC20 isplever starter user guide gal programming timing chart GAL programming Guide EC20 tutorial TEXT
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Abstract: -3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an , tracks the -ACK input pin, When INTSEL is a logic 0 and interrupts are enabled by bit-4 in the control , through B. A logic 0 on this pin(s) indicates that the 452/452PS 452/452PS is powered-on and ready. This pin can , transmitter has data ready and waiting to send for the given channel(s). Writing a logic 1 in the modem , information between an external CPU and the 452/452PS 452/452PS package. A logic 0 on chip select pins -CSA or -CSB ... Exar
Original
datasheet

30 pages,
160.05 Kb

TL16C452 ST16C452PS ST16C452 ST16C450 16C450 ns16c450 TEXT
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Abstract: combinatorial logic array. This guaran tees easy interconnection of and uniform performance from all nodes. Sum terms, which are easy to use blocks of gates, provide combinatorial AND/OR logic blocks. Sum terms can , possible in the past through the use of innovative architecture and logic cell design. A logic cell with many possible configu rations gives a finer logic granularity and maximizes logic resource usage , . Logic Cell Architecture In the H-Series, each logic cell has eight product terms and gen erates one ... OCR Scan
datasheet

4 pages,
191.93 Kb

TEXT
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Abstract: -3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an , tracks the -ACK input pin, When INTSEL is a logic 0 and interrupts are enabled by bit-4 in the control , I Master Reset (active low) - a logic 0 on this pin will reset the internal registers and all , through B. A logic 0 on this pin(s) indicates the modem or data set is powered-on and is ready for data , channels, A through B. A logic 0 on this pin(s) indicates that the 452/452PS 452/452PS is powered-on and ready ... Original
datasheet

31 pages,
299.83 Kb

TL16C452 ST16C452PS ST16C452CJ68 ST16C452 ST16C450 NS16C450 16C450 TEXT
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Abstract: connected printer. This pin basically tracks the -ACK input pin, When INTSEL is a logic 0 and interrupts , UART channels, A through B. A logic 0 on the -RTS pin(s) indicates the transmitter has data ready and , package. A logic 0 on chip select pins -CSA or -CSB allows the user to configure, send data, and/or , port. A logic 0 on chip select pin -CSP allows the user to configure, send data, and/or receive data , is a logic 0 and LCR bit-7 is a logic 1. Note 3*: Printer Port Register set is accessible only when ... Exar
Original
datasheet

30 pages,
385.41 Kb

TL16C452 T40S ST16C452PS ST16C452 ST16C450 NS16C450 Code T6S 16C450 TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
Timing and Logic Products Timing and Logic Products IDT is a leading supplier of high-performance digital logic, bus switch logic and clock management products. IDT provides logic solutions for network Show me all the Timing and Logic job opportunities at IDT.   Support/Contacts E-mail Timing and Logic
/datasheets/files/idt/docs/rp00000/rp000a1.htm
IDT 06/10/2000 49.83 Kb HTM rp000a1.htm
generalizations of the common logic primitives: AND, INVERT, NAND, NOR, OR, XNOR, and XOR. Except for the INVERT gate : O = A 0 • A 1 • ... • A (n-1) Figure 4.33 Type 1 AND Gate: Symbol and Logic AND Gate: Symbol and Logic Diagram Type 3 AND gate : O n = A n • B n Figure 4.35 Type 3 AND Gate: Symbol and Logic Diagram You can use the inversions of gate : O n = !A n Figure 4.36 INVERT gate: Symbol and Logic Diagram
/datasheets/files/xilinx/docs/wcd00045/wcd0458e.htm
Xilinx 16/02/1999 6.28 Kb HTM wcd0458e.htm
of logic and various memory types. A typical example is a Smartcard IC combining ROM, EEPROM, SRAM and logic/MCU. Microcomputer products also are available today : Flash primary memory, Flash or EEPROM secondary (boot) memory, SRAM, Logic and CPLD in a second block of Flash memory, microcomputer interface logic and memory mapping, and a Development trends in technology, especially the technologies for non-volatile memories, SRAM and
/datasheets/files/stmicroelectronics/stonline/prodpres/memory/mem_sys/msys_idx.htm
STMicroelectronics 20/10/2000 11.5 Kb HTM msys_idx.htm
App Note Abstract: THERMAL CHARACTERISTICS OF LINEAR AND LOGIC > Applications > Application Report Abstract THERMAL CHARACTERISTICS OF LINEAR AND LOGIC package thermal resistance from junction to ambient (theta sub JA), and package thermal resistance from junction-to-case (theta sub JC). Recent data generated by Texas Instruments (TI) linear and logic package designers includes theta sub JA and theta sub JC measured, or modeled, on both a JEDEC low-thermal-conductivity (low
/datasheets/files/texas-instruments/data/www.ti.com/sc/docs/psheets/abstract/apps/szza017a.htm
Texas Instruments 19/01/2000 7.84 Kb HTM szza017a.htm
of logic and various memory types. A typical example is a Smartcard IC combining ROM, EEPROM, SRAM and logic/MCU. Microcomputer products also are available today : Flash primary memory, Flash or EEPROM secondary (boot) memory, SRAM, Logic and CPLD in Development trends in technology, especially the technologies for non-volatile memories, SRAM and logic, are moving towards the integration of combinations of these circuit blocks on to one
/datasheets/files/stmicroelectronics/stonline/prodpres/memory/mem_sys/msys_idx-v1.htm
STMicroelectronics 27/11/2000 11.23 Kb HTM msys_idx-v1.htm
App Note Abstract: THERMAL CHARACTERISTICS OF LINEAR AND LOGIC > Applications > Application Report Abstract THERMAL CHARACTERISTICS OF LINEAR AND LOGIC package thermal resistance from junction to ambient (theta sub JA), and package thermal resistance from junction-to-case (theta sub JC). Recent data generated by Texas Instruments (TI) linear and logic package designers includes theta sub JA and theta sub JC measured, or modeled, on both a JEDEC low-thermal-conductivity (low
/datasheets/files/texas-instruments/data/wwwti~1.com/sc/docs/psheets/abstract/apps/szza017a.htm
Texas Instruments 19/01/2000 7.84 Kb HTM szza017a.htm
ST | IN-SYSTEM PROGRAMMABLE (ISP) MULTIPLE-MEMORY AND LOGIC FLASH+PSD SYSTEMS FOR MCUS Datasheet IN-SYSTEM PROGRAMMABLE (ISP) MULTIPLE-MEMORY AND LOGIC FLASH+PSD SYSTEMS FOR MCUS M8913F1W M8913F1W M8913F1Y M8913F1Y M8913F2W M8913F2W M8913F2Y M8913F2Y M8934F2W M8934F2W M8934F2Y M8934F2Y Document Format Size Document Number Date Update Pages Portable Document Format 7084 07/06/2000 7 Raw Text Format
/datasheets/files/stmicroelectronics/books/all/7084.htm
STMicroelectronics 16/06/2000 2.91 Kb HTM 7084.htm
Timing and Logic Digital Logic Timing and Logic Digital Logic
/datasheets/files/idt/docs/rp00000/rp0006d.htm
IDT 06/10/2000 45.6 Kb HTM rp0006d.htm
, circuit and logic verification, product characterization, layout supervision, tape out documentation, and experience with HSPICE and Verilog, schematic capture, logic verification, LVS, and DRC tools required. The ideal candidate will have experience in CMOS circuit and logic design. Requires strong written design written and verbal communication skills are a must. Clear Logic Homepage [ Frames resume (ascii text only, please) to jobs@clear-logic.com , or contact : Clear Logic, Inc. 2972
/datasheets/files/scantec/clogic/clogic-cd/index(3).html
Scantec 06/06/1998 3.02 Kb HTML index(3).html
internal memory with mapping capabilities, 64K hardware breakpoints, 32K real-time trace memory and logic "On The Fly" and Logic Analyzer 64K Hardware and Conditional Breakpoints DOS and MS-Windows family of microcontrollers. It is serially linked to PC or compatible systems and carries out a complete voltage and frequency range specified by Intel. DS-51 DS-51 also supports the new low-power and low-voltage 8051 microcontrollers and derivatives and can emulate the microcontrollers using either the
/datasheets/files/intel/products two & tools/design/usb/devtools/7ed361ae.htm
Intel 12/05/1999 5.36 Kb HTM 7ed361ae.htm