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Abstract: Altera's MAX+PLUS II development system, which uses advanced logic synthesis techniques and a heuristic , Array Blocks (LABs). Each logic cell has a register and a programmable-AND/fixed-OR array that is used to build combinatorial logic. The following features increase the flexibility and capacity of MAX , be used and shared by logic cells to implement complex logic functions with maximum flexibility , performance and density from complex programmable logic devices (CPLDs) and field-programmable gate arrays Altera
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21mux data sheet 74157 Multiplexer 74157 application 74157 74684 8 bit adder
Abstract: Altera's MAX+PLUS II development system, which uses advanced logic synthesis techniques and a heuristic , Array Blocks (LABs). Each logic cell has a register and a programmable-AND/fixed-OR array that is used to build combinatorial logic. The following features increase the flexibility and capacity of MAX , be used and shared by logic cells to implement complex logic functions with maximum flexibility , expect varying levels of performance and density from complex programmable logic devices (CPLDs) and Altera
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Abstract: -100% routable and pin-out maintainable High Performance, Flexible Logic Cell -High performance , MHz. Internal logic cell delays are under 2 ns and total input to output combinatorial logic delays , , and discrete logic solutions. A wide range of additional family features complement the pASIC 2 , software solution from design entry, to logic synthesis, to place and route, to simulation. QuickWorks includes VHDL, Verilog, schematic, boolean, and mixed-mode entry with fast and efficient logic synthesis -
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pASIC 2 FPGA FAMILY schematic of TTL XOR Gates QL2003 QL2005 QL2007 QL2009
Abstract: of internal signals using an external logic analyzer and using a minimal number of FPGA I/O pins , ' includes both logic analyzers and oscilloscopes equipped with digital channels, commonly referred to as , shows the Logic Analyzer Interface and the hardware setup. Figure 14­1. Logic Analyzer Interface and , the File menu, click New. The New dialog box opens. Click the Other Files tab and select Logic , Interface File is on the File Menu, click Open, and select the Logic Analyzer Interface File you want to Altera
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QII53016-7 logic analyzer combinational logic circuit project free circuit logic analyzer mixed signal fpga datasheet
Abstract: White Paper Stratix II Performance and Logic Efficiency Analysis Introduction Pursuing higher , . Research conducted by E. Ahmed and J. Rose concluded that FPGA logic fabric with wider look-up tables , view of the relative performance and logic efficiency comparisons of FPGA logic fabrics with different , less logic to be realized. The native construct of wide LUTs with up to seven inputs and the adaptive nature of the Stratix II logic structure enable high performance and logic efficiency. Therefore, the Altera
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2-bit half adder bc 339
Abstract: Programming and Logic Analysis Tutorial Lattice Semiconductor Corporation 5555 NE Moore Court , the Programming and Logic Analysis Tutorial ii latest version of the relevant information to , Logic Analysis Tutorial iii Programming and Logic Analysis Tutorial iv Contents Programming and Logic Analysis Tutorial 1 Introduction 1 Learning Objectives 1 Time to Complete This , Project Summary Glossary 45 45 Recommended Reference Materials Programming and Logic Analysis -
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tutorial EC20 GAL programming Guide gal programming timing chart isplever starter user guide LFEC20
Abstract: -3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an , tracks the -ACK input pin, When INTSEL is a logic 0 and interrupts are enabled by bit-4 in the control , through B. A logic 0 on this pin(s) indicates that the 452/452PS is powered-on and ready. This pin can , transmitter has data ready and waiting to send for the given channel(s). Writing a logic 1 in the modem , information between an external CPU and the 452/452PS package. A logic 0 on chip select pins -CSA or -CSB Exar
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ST16C452 ST16C452PS 16C450 ns16c450 ST16C450 TL16C452 ST16C452/ST16C452PS 452PS
Abstract: combinatorial logic array. This guaran tees easy interconnection of and uniform performance from all nodes. Sum terms, which are easy to use blocks of gates, provide combinatorial AND/OR logic blocks. Sum terms can , possible in the past through the use of innovative architecture and logic cell design. A logic cell with many possible configu rations gives a finer logic granularity and maximizes logic resource usage , . Logic Cell Architecture In the H-Series, each logic cell has eight product terms and gen erates one -
OCR Scan
Abstract: -3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an , tracks the -ACK input pin, When INTSEL is a logic 0 and interrupts are enabled by bit-4 in the control , I Master Reset (active low) - a logic 0 on this pin will reset the internal registers and all , through B. A logic 0 on this pin(s) indicates the modem or data set is powered-on and is ready for data , channels, A through B. A logic 0 on this pin(s) indicates that the 452/452PS is powered-on and ready -
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ST16C452CJ68
Abstract: connected printer. This pin basically tracks the -ACK input pin, When INTSEL is a logic 0 and interrupts , UART channels, A through B. A logic 0 on the -RTS pin(s) indicates the transmitter has data ready and , package. A logic 0 on chip select pins -CSA or -CSB allows the user to configure, send data, and/or , port. A logic 0 on chip select pin -CSP allows the user to configure, send data, and/or receive data , is a logic 0 and LCR bit-7 is a logic 1. Note 3*: Printer Port Register set is accessible only when Exar
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Code T6S T40S
Abstract: logic 0. During the STD mode a logic 1 transition on -AS latches the state of the chip selects and the , interrupts are enabled in the interrupt enable register (IER) - MCR bit-3 is set to a logic 1, and - an , WIRE-OR'ed. This is accomplished by setting MCR bit-5 to a logic 1 and connecting a 500 to 1K ohms resistor between this pin and ground to provide an acceptable logic 0 level. IRQB/-RXRDY 29 32 29 O , -RXRDY Reset. (active high) - A logic 1 on this pin will reset the internal registers and all the Exar
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ST16C650A ST16C550 ST16C650 16C550 ST16C650ACP40 ST16C650ACJ44 32-BYTE ST16C450/550/650 RS485
Abstract: to allocate logic to the Macrocells, and the timing model of the device. Interconnect Early in , , and Macrocell feedbacks to a number of logic blocks. As a small, simple switching mechanism, it , performance. In addition, the logic blocks themselves are kept relatively small, and as a result their , place these signals onto muxes 1 and 2 so that they will both route into the logic block. Later in the , input signals. The XPLA Logic Blocks feature 36 inputs, which allow complex state machines and 32 bit Xilinx
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82S100 application of programmable array logic 22V10 complete details pla macrocells signetics 82s100
Abstract: of simple logic modules used to implement the required logic gates and storage elements. These logic , , and logic modules. Each Actel FPGA family has a slightly different mix of these resources, optimized , , efficiency, and ease of design required to implement the application. If the logic module provides , very efficient, but random logic and sequential logic functions are also efficient. These options , Logic Module. Notice that latches can be implemented in a single logic module per bit and that Actel
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ACTEL A32100DX A32400DX
Abstract: .28 Enabling and Disabling the Em bedded Logic Analyzer M egafunction , software and is used with APEXTM 20K program m able logic devices (PLDs), allows you to analyze and verify , display waveforms. You can also use data retrieved by the Em bedded Logic Analyzer to debug and verify your design. This m anual explains how to use the Em bedded Logic Analyzer megafunction, and gives detailed, step-by-step procedures on how to set up and run the Em bedded Logic Analyzer. Quartus -
OCR Scan
EP20K100 demo P25-04733-01 EP20K100
Abstract: of simple logic modules used to implement the required logic gates and storage elements. These logic , , and logic modules. Each Actel FPGA family has a slightly different mix of these resources, optimized , , efficiency, and ease of design required to implement the application. If the logic module provides , very efficient, but random logic and sequential logic functions are also efficient. These options , Logic Module. Notice that latches can be implemented in a single logic module per bit and that Actel
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AC165 actel fpga
Abstract: RESET 21 I Reset. (active high) - A logic 1 on this pin will reset the internal registers and , one location is empty and available in the FIFO or THR. This pin goes to a logic 1 when there are no , UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is , individual UART channels, A through B. A logic 0 on this pin indicates that the 2552 is powered-on and ready , through B. A logic 0 on the -RTS pin indicates the transmitter has data ready and waiting to send Exar
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ST16C2552 16-BYTE NS16C552 ST16C2552IJ44 ST16C2552CJ44 NS16C550
Abstract: .29 Enabling and Disabling the Embedded Logic Analyzer Megafunction , provided with the QuartusTM software and is used with APEXTM 20K programmable logic devices (PLDs), allows , , configure memory, and display waveforms. You can also use data retrieved by the Embedded Logic Analyzer to debug and verify your design. This manual explains how to use the Embedded Logic Analyzer megafunction, and gives detailed, step-by-step procedures on how to set up and run the Embedded Logic Analyzer Altera
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embedded c programming examples specification of logic analyser embedded system projects free circuit usb logic analyzer C 828 Transistor tms 980
Abstract: STD mode a logic 1 transition on -AS latches the state of the chip selects and the register select , interrupt enable register (IER) - MCR bit-3 is set to a logic 1, and - an interrupt condition exists , accomplished by setting MCR bit-5 to a logic 1 and connecting a 500 to 1K ohms resistor between this pin and , . (active high) - A logic 1 on this pin will reset the internal registers and all the outputs. (See , 0 (GND) on this pin and STD mode is selected when this pin is a logic 1 (left open or tied to VCC). Exar
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HDR2X4
Abstract: Integrator motherboard May 2004 B Extension to logic tiles on top of Versatile/PB926EJ-S and logic , , pre-built FPGA configuration images and test software for the peripherals in the logic tile. This , : · · A typical Versatile system, with a Versatile/PB926EJ-S baseboard and a logic tile · , /HDRB stack and an Integrator/IM-LT1 interface module plus a logic tile on the EXPA/EXPB stack A motherboard-less Integrator system, consisting of a core module, an Integrator/IM-LT1 and a logic tile stacked ARM
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AN119 ahb apb bridge vhd verilog code for ahb bus matrix verilog code ahb-apb bridge VPB926ejs ahb arbiter AMBA AHB bus arbiter 0119E ARM926EJ-S
Abstract: placement and die size information © LSI Logic Corporation 1999, 2000 06-00 2.10 10 Avant , bus naming style · Provide net names for netlist 1'b0 and 1'b1 connections © LSI Logic , lsidesmgr Creating a Library and adding References © LSI Logic Corporation 1999, 2000 06-00 2.26 , VDD/VSS · Set Cell Types->Macro true for macrocells (megacells) and Std/Module Cell © LSI Logic , mode · Milkyway is both a database and a tool © LSI Logic Corporation 1999, 2000 06-00 2.30 LSI Logic
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LSI Logic primetime si user guide LSI logic array components G10/G11/G12
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