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HS1-82C85RH-Q Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24
HS9-82C85RH-8 Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24, CERAMIC, DFP-24
HS9-82C85RH-Q Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24, CERAMIC, DFP-24
CP82C84AZ Intersil Corporation 8MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP18, ROHS COMPLIANT, PLASTIC, DIP-18
CS82C84AZ96 Intersil Corporation 8MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC20, ROHS COMPLIANT, PLASTIC, LCC-20
HS1-82C85RH-8 Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24, SIDE BRAZED, CERAMIC, DIP-24

"AMBA AHB specification"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: . The Systems IP ARM11 AMBA AHB Extensions Specification defines the ARM11 extensions to the standard , the byte lane strobe functionality that the Systems IP ARM11 AMBA AHB Extensions Specification , supports the exclusive access functionality that the Systems IP ARM11 AMBA AHB Extensions Specification , Specification describes ARM11 AHB-Lite signals that the Systems IP ARM11 AMBA AHB Extensions Specification and , PrimeCell Infrastructure AMBA 3 AXI to AMBA 2 AHB Bridges (BP137) ® TM TM TM ARM
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AMBA AHB to APB BUS Bridge verilog code AMBA AXI to APB BUS Bridge verilog code AMBA AXI to AHB BUS Bridge verilog code AMBA AXI verilog code for amba ahb bus verilog code for amba ahb master
Abstract: PrimeCell Infrastructure AMBA 2 AHB to AMBA 3 AXI Bridges (BP136) ® TM TM TM , 0008B PrimeCell Infrastructure AMBA 2 AHB to AMBA 3 AXI Bridges (BP136) Technical Overview , . ARM DTO 0008B Contents PrimeCell Infrastructure AMBA 2 AHB to AMBA 3 AXI Bridges (BP136 , PrimeCell Infrastructure AMBA 2 AHB to AMBA 3 AXI Bridges (BP136) ® TM TM TM This technical , About the AHB to AXI bridges The AMBATM 2 AHBTM to AMBA 3 AXITM bridges enable AHB masters to ARM
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AMBA AXI verilog code AMBA ahb bus protocol AMBA AHB to AHB BUS Bridge verilog code verilog code AMBA AHB verilog code for ahb bus slave amba ahb verilog code
Abstract: generator PCI bus arbiter (up to 7 external bus agents) 32-bit, 33/66MHz PCI AMBA AHB Host Bridge Core Interrupt controller Parity generation and parity error detection. AMBA AHB host interface compliant with AMBA specification revision 2.0 The PCI-HB-AHB core enables data transfers between a host processor , transfers between an AMBA AHB host processor bus system and PCI bus based devices. The bridge is in charge , Data Interface AMBA AHB Master PCI Target FIFO FIFO Data Buffer PCI Master PCI BUS Cast
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AMBA BUS vhdl code amba ahb bus arbitration AMBA AHB memory controller AMBA AHB bus arbiter PCI AHB bridge ahb slave RTL 33/66MH
Abstract: AMBATM Specification (Rev 2.0) ARM IHI 0011A AMBA Specification (Rev 2.0) © Copyright ARM , Advanced Microcontroller Bus Architecture (AMBA) specification. It contains the following sections: · , 1999. All rights reserved. iii About this document This document is the AMBA specification , design modules that conform to the AMBA specification. Organization This document is organized into the , AMBA devices. Chapter 3 AMBA AHB Read this chapter for an introduction to the AMBA Advanced ARM
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AMBA AHB specification ahb arbiter AMBA APB UART
Abstract: AMBA 3 architecture. AMBA 3 (Advanced Microcontroller Bus Architecture) is an open bus specification , modules implement AMBA 3 AHB-Lite specification and AMBA 3 APB specification for system interconnection , based on the AMBA 3 TM ® TM AHB-Lite interconnect and AMBA 3 APB interconnect. Application ° ° , .01) ­ 20 July 2009 Datasheet: General Description AHB-APB Bridge #1 AHB Switch Matrix , system-on-chip is based on the AMBA 3 AHB-Lite interconnect and the AMBA 3 APB interconnect. The SoC EXOR International
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APB to I2C interface spi controller with apb interface AMBA AHB DMA AMBA APB spi design of dma controller using vhdl Cypress FX2 DS0031 AD9882 ITU-656
Abstract: Counters Summary General Registers Summary AMBA Register Summary AHB Master Signals AHBSlave Signals , AMBA peripherals device that can communicate with a host through the AHB bus. The CoreWare IP number , Triple-Speed MAC System Implementation TX FIFO RX FIFO cw101304_ApE1110 GMII/MII AHB Master AMBA , with the AMBA bus and the AHBSlave bus. See the AMBA Specification Rev. 2.0 for details. Required , together as a AMBA peripheral component on the AHB bus. Because various applications and system LSI Logic
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E1110 LSI Rapidchip library verilog code for spi4.2 to fifo LSI LOGIC AMBA 3.0 technical summary ApE1110 DB08-000288-01
Abstract: /Transmitter modes I2S-AHB Eight configurable stereo channels Inter-IC Sound Bus Core for AMBA AHB , : o AMBA, AHB slave unit to interface with the host controller, especially DMA The I2S-AHB core , the AHB bus by any AHB bus master that is able to perform single or burst accesses on the AMBA bus , microprocessor system using the AMBA AHB bus (see block diagram). It is composed of several blocks: I2S - multi channel I2S audio core AHB wrapper - bi-directional wrapper from FIFOs and SFR block to AMBA Cast
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ahb slave verilog code verilog code for i2s bus ahb wrapper verilog code verilog i2s verilog code for ahb master verilog code for transmission line
Abstract: -301) User Guide (ARM DSU 0003) · AMBA AXI Protocol v1.0 Specification (ARM IHI 0022) · AMBA 3 AHB-Lite Protocol v1.0 Specification (ARM IHI 0033) · AMBA 3 APB Protocol v1.0 Specification (ARM IHI , AMBA Network Interconnect (NIC-301) ® Revision: r2p0 Technical Reference Manual Copyright © 2006-2009 ARM. All rights reserved. ARM DDI 0397F (ID110409) AMBA Network Interconnect (NIC , , Unrestricted Access ii Contents AMBA Network Interconnect (NIC-301) Technical Reference Manual ARM
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AMBA AXI designer user guide ADR-301 verilog code for amba apb master ARM DUI 0333 verilog rtl code of Crossbar Switch JEP106
Abstract: buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD panel. In an FPGA, ASIC, or ASSP device, the , AHB Slave Port TFT LCD Panel AHB Master Port AMBA 2.0 AHB Bus SDRAM Controller , Little-endian, big-endian, or Windows CE mode Compliance with AMBA Specification (Rev 2.0) Fully-synchronous , Processor Status & Control Registers AMBA 2.0 AHB Bus DMA Controller AHB Bus Master Interface , 2: DB9000AHB AMBA 2.0 AHB Bus TFT LCD Controller Pin Description In addition to the AMBA 2.0 AHB -
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amba ahb master slave sram controller amba ahb master sram controller sharp lcd panel 20 pin sharp 640x240 lcd pixel vhdl 640x200 sharp DB9000AHB-DS-V1
Abstract: 0003) · AMBA AXI Protocol v1.0 Specification (ARM IHI 0022) · AMBA 3 AHB-Lite Protocol v1.0 Specification (ARM IHI 0033) · AMBA 3 APB Protocol v1.0 Specification (ARM IHI 0024) · ARM DDI 0397G , AMBA Network Interconnect (NIC-301) ® Revision: r2p1 Technical Reference Manual Copyright © 2006-2010 ARM. All rights reserved. ARM DDI 0397G (ID031010) AMBA Network Interconnect (NIC , . Non-Confidential ii Contents AMBA Network Interconnect (NIC-301) Technical Reference Manual Preface ARM
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AMBA APB bus protocol AMBA AXI to APB BUS Bridge ARM DII 0222 AMBA AHB to AXI FD001 User Guide ARM DUI 0333 INCR
Abstract: 0003) · AMBA AXI Protocol v1.0 Specification (ARM IHI 0022) · AMBA 3 AHB-Lite Protocol v1.0 Specification (ARM IHI 0033) · AMBA 3 APB Protocol v1.0 Specification (ARM IHI 0024) · ARM DDI 0397H , issue for r2p2. Changed product name from AMBA® Network Interconnect NIC-301 to CoreLinkTM Network , . Relationship between CoreLink Network Interconnect and AMBA Designer . Product , . 2-5 AXI burst type to AHB burst type mapping ARM
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nic301 NIC 301 tidemark dii 0157 ARM DUI 0333 Supplement 6 ID080710
Abstract: through the FIC. Overview of APB, APB3, AHB, and AHB-Lite The AMBA bus specification is an open , within the AMBA specification. The AMBA AHB is for highperformance, high clock frequency system modules , Microcontroller Bus Architecture (AMBA®) specification defines an on-chip communications standard for designing high-performance embedded microcontrollers. Several distinct buses are defined within the AMBA specification , specification), is a subset of the full AHB specification for use in designs where only a single bus master is Actel
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AC335 verilog code for apb3 KEYPAD verilog verilog code for uart apb verilog code for ahb bus matrix ahb wrapper vhdl code verilog code for amba apb bus
Abstract: ARM architecture: · AMBA 3 APB Protocol Specification (ARM IHI 0024) · AMBA AXI Protocol Specification (ARM IHI 0022) · AMBA 3 AHB-Lite Protocol Specification (ARM IHI 0033) · AMBA Specification , Extension 2.4 Mapping for AMBA 3 buses The control signals mapping for AXI and AHB buses is listed in , . 2-4 AMBA 3 signals mapping . 2-17 Mapping for AMBA 3 buses ARM
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0455D AMBA amba bus architecture the arm modeling Constructors Logos AMBA ARM IHI 0022 ID031910
Abstract: PCI specification 2.3 compliant 66MHz PCI performance 64-bit PCI data path PCI-M64AHB Zero wait states burst mode Full PCI bus master/target func- 64-bit/66MHz PCI PCI to AMBA AHB , PCI-M64AHB Core is to act as a simple bridge between the PCI bus and the AMBA AHB bus. The PCI-M64AHB , Slave AMBA AHB BUS PCI BUS Control Registers Local Bus Access Controller FIFO FIFO , compliant with the PCI Local Bus Specification, Revision 2.3. The PCI-M64AHB core can be used in ASIC and Cast
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PCI AHB DMA AMBA AHB bus DMA with AHB PCI-M64
Abstract: for DMA access to the Endpoint FIFOs, including a DMA controller built into the AMBA AHB interface , INTERFACE SIGNALS (AMBA AHB Slave) AHB_HSEL AHB_HREADYI AHB_HREADYO Input Input Output AHB select , write not read. CPU interrupt. Active low. DMA INTERFACE SIGNALS (AMBA AHB MAster) AHB_HGRANT (etc , Interface Rx Buff CRC Gen/Check Timers Cycle Control Rx Buff IN AHB bus - Slave mode , On-The-Go supplement to the USB 2.0 specification FIFO Decoder Packet Decode compliant) USB1 Mentor Graphics
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UTM RESISTOR MUSBHDRC UTM power RESISTOR verilog code for frame synchronization Mentor 97070 PD-40136 002-FO
Abstract: AMBA Specification (Rev 2.0). The following features are supported by the PrimeCell CLCDC AMBA AHB , the following documents for other relevant information: AMBA Specification (Rev 2.0) (ARM IHI 0011). , (PL110) overview . 2-2 AMBA AHB interface , (PL110) . 1-2 AMBA AHB slave interface signals .A-2 Copyright © ARM Limited 1999, 2000. All rights reserved. ix A.2 A.3 A.4 A.5 AMBA AHB ARM
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0161D
Abstract: arbiter is a synthesizable · 32-bit AMBA AHB Specification, · OPB slave device and PLB4 core with , that supports the · PLB4 slave device and OPB master AMBA AHB Specification, Version 2.0 , of the OPB · Support for clock and Class II power master device · 32-bit AMBA AHB Specification , bridge PLB-to-OPB bridge AHB arbiter OPB arbiter AHB bus AHB master AHB slave 1 OPB bus AHB slave n OPB master Figure 1. Peripheral integration using the CoreConnect bus architecture IBM
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G224-7587-01
Abstract: information on AMBA AHB slave interfaces, refer to the AMBA Specification (Rev 2.0). The following features , Controller (PL110) overview . 2-2 AMBA AHB interface , . 4-4 AMBA AHB Slave interface signals . AMBA AHB Master interface signals . , . 4-5 AMBA AHB Slave interface signals ARM
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LCD 320X200 LCD 640X200 notebook LCD Panel Control Signal STN LCD 0161E
Abstract: Architecture (AMBA) Advanced High-performance Bus (AHB) and the CoreConnectTM Processor Local Bus (PLB). The AHB to PLB Bridge is a slave on the AHB bus and a master on the PLB bus. The bridge also includes a , device · 32-bit AMBA AHB rev 2.0 slave interface · 64-bit CoreConnect PLB master interface · Supports , typical AMBA AHB design may contain one or more bus masters, one or more slaves, an arbiter, and a , Preliminary IBM AHB to PLB Bridge Core Overview Features The AHB to PLB Bridge is a IBM
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rev 1.5 ibm amba ahb ahb bridge ahb2plb ARM966E-S ibm rev 1.5 ARM946E-S PB-00
Abstract: . 4-3 AMBA AHB interface signals . AMBA AHB slave interface signals . AMBA AHB master interface signals . Non-AMBA , . 4-4 Common AMBA AHB signals . A-2 AMBA AHB slave interface signals ARM
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AM29BL802 K6T8016 verilog for SRAM 512k word 16bit 28F3204W30 28F6408W30 28F640K3 PL093 0236B
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