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Part Manufacturer Description PDF & SAMPLES
SN54LS395J Texas Instruments PARALLEL IN PARALLEL OUT SHIFT REGISTER
HCTS299KMSR Intersil Corporation HCT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP20
HCTS299DMSR Intersil Corporation HCT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP20
SN74HC165NSRG4 Texas Instruments 8-Bit Parallel-Load Shift Registers 16-SO -40 to 125
SN74LV165ADGVR Texas Instruments Parallel-Load 8-Bit Shift Registers 16-TVSOP -40 to 125
SN74LV166ADGVRE4 Texas Instruments 8-Bit Parallel-Load Shift Registers 16-TVSOP -40 to 85

"4-bit parallel Shift Register"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: HCT CMOS 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear 8-Bit Parallel-Out , Shift Register 8-Bit Parallel In/Serial Out Shift Register 5 5 MM74C165 MM74HC165 74C CMOS HC , /Storage Register with Common Parallel I/O Pins 3-STATE 8-Bit Universal Shift/Storage Register Octal Serial/Parallel Register with Sign Extend 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common , Serial In/Parallel Out Shift Register with Asynchronous Clear Dual 8-Bit Shift Register 16-Bit Fairchild Semiconductor
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16 bit universal shift register 16-bit universal shift register 74LCX32646 8bit shift DM93L28 DM93L38 74AC299 74VHC164 DM74LS164 MM74C164
Abstract: Bit PIPO Shift Register 4 Bit PIPO Shift Register 8 Bit PIPO Shift Register (3-State) 8 Bit PIPO Shift Register (3-State) 8 Bit Shift Register Latch (3-State) 8 Bit Latch Shift Register 4 Word x 4 Bit Register File (3-State) 8 Bit SIPO Shift Register Latch (3-State) 4034B 4094B LS164 HC164 HCT164 , SELECTION GUIDE REGISTER Type Number M54/74 HC164 HCT164 HC165 HCT165 HC166 HC173 HC194 HC195 HC299 HC323 HC595 HC597 HC670 HC4094 8 8 8 8 8 Bit Bit Bit Bit Bit SIPO PISO PISO PISO PISO Shift Shift -
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LS165 LS173 4021B CMOS 4000B shift register sipo LS166 LS194 LS195 LS299
Abstract: the functions of a high speed sixteen bit shift register and parallel data input latches/flip-flops , . The sixteen bit word will be parallel loaded into the ECL shift register and Bit 0 will appear at the , allows data into the part, the PARALLEL LOAD input loads data into the shift register, and the PIXEL , , hold the last bit of the shift register at a level chosen by the user white allowing the internal bits of the shift register to continue shifting. Another control input, ENABLE, causes the parallel -
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dp8512 DP8515/DP8515-350/ DP8516/DP8516-350 DP8515/DP8515-350/DP8516/DP8516-350 D-8000 AA32096
Abstract: 5.5 TTL TTL 2S Description SN54LS673, SN74LS673 The 'LS673 is a 16-bit shift register and a 16-bit , parallel outputs. The shift register can be parallel loaded with the storage-register data upon commmand. A , . SN54LS674, SN74LS674 The 'LS674 is a 16-bit parallel-in, serial-out shift register. A three-state input , . Features l l 'LS673 ¡ 16-Bit Serial-In, Serial-Out Shift Register with 16-Bit Parallel-Out Storage Register ¡ Performs Serial-to-Parallel Conversion 'LS674 ¡ 16-Bit Parallel-In, Serial-Out Shift Register ¡ Texas Instruments
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16-BIT SDLS195 59628860701KA SN54LS674J SN54LS674JT SNJ54LS674FK
Abstract: high speed sixteen bit shift register and parallel data input latches/flip-flops required in high , transition on the PARALLEL LOAD input loads into the ECL shift register the sixteen bit word present at or , will be parallel loaded into the ECL shift register and Bit 0 will appear at the SO SERIAL OUTPUT , part, the PARALLEL LOAD input loads data into the shift register, and the PIXEL CLOCK input shifts data , shift register. Two other inputs, OUTPUT CONTROL and OUTPUT LEVEL CONTROL, hold the last bit of the -
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DP8515-350V dp8s DP8516-350V DP8516V DP851S SU-10 D0-D15 TL/F/8684-15 D1S-023 DP8515/16 TL/F/8684-19 DP8515/DP8515-350/DP8516/DP8S16-350
Abstract: , and Spartan-II architectures, a four-input LUT can also function as a 16-bit shift register with a single output accessed by the LUT's address lines. This 16-bit shift register function can be accessed , cascadable output (the 16th bit of the shift register.) XAPP220 (v1.1) January 11, 2001 www.xilinx.com , register as the new bit in the sequence. Tap D is the last stage in the shift register and so represents , the shift register taps over multiple cycles enables parallel access to four of the shift register Xilinx
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SRL16 verilog code 16 bit LFSR vhdl code 16 bit LFSR verilog code 8 bit LFSR vhdl code 8 bit LFSR simple LFSR verilog hdl code for parity generator XAPP211 XAPP217
Abstract: 12th bit, the parallel output latch latches the data which has been written to shift register @ and , possible to read serial input data to a shift register while converting parallel data into serial data , immunity by applying silicon CMOS process. Because a 12-bit serial-parallel shift register and a 12-bit , register at the rising edge of shift clock. The shift clock on and after 13th bit is neglected and pin DO , data in order. (4) At the rising edge of CLK, 12-bit serial data is written from DI to shift register Mitsubishi
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20P2N-A M66006P/FP 12-BIT M66006
Abstract: D1 DOUT Shift Register Data Output / Parallel Output Bit 8 D2 DIN Shift Register Data Input / Parallel Output Bit 9 D3 NSL Shift Register Load / Parallel Output Bit 10 D4 INCB Incremental Output B , , high active E1 n.c. E2 PO6 Parallel Output Bit 6 E3 CLK Shift Register Clock Input / Parallel , Input NSIN / Parallel Output Bit 12 Incremental Output Z / Parallel Output Bit 11 Shift Register Load / Parallel Output Bit 10 Shift Register Data Input / Parallel Output Bit 9 Shift Register Data iC-Haus
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INTERPOLATOR SIN COS spi OBGA opto 22 form 703 NSL 32 equivalent INTERPOLATOR 6 BITS SIN COS DATA CLK INTERPOLATOR 6 BITS SIN COS C-SN85 D-55294
Abstract: -tap FIR filter architecture. This filter has eight 8-bit registers arranged in a shift register , /Parallel FIR Filter Schematic See Figure 8 for details. 4×2 Shift Register 4×2 Shift Register 4×2 Shift , performed in parallel using LUTs. The following example uses 2-bit positive integers. h(1) = 01, h(2) = 11 , : Implementing FIR Filters in FLEX Devices Figure 6. Fully Serial FIR Filter Schematic n×1 Shift Register n×1 Shift Register n×1 Shift Register n×1 Shift Register x(n) n×1 Shift Register n×1 Shift Register n Altera
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800-EPLD EPF8820A EPF8452A
Abstract: -tap FIR filter architecture. This filter has eight 8-bit registers arranged in a shift register , /Parallel FIR Filter Schematic See Figure 8 for details. 4×2 Shift Register 4×2 Shift Register 4×2 Shift , performed in parallel using LUTs. The following example uses 2-bit positive integers. h(1) = 01, h(2) = 11 , : Implementing FIR Filters in FLEX Devices Figure 6. Fully Serial FIR Filter Schematic n×1 Shift Register n×1 Shift Register n×1 Shift Register n×1 Shift Register x(n) n×1 Shift Register n×1 Shift Register n Altera
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AHDL adder subtractor 8 bit binary multiplier using adders
Abstract: -tap FIR filter architecture. This filter has eight 8-bit registers arranged in a shift register , . You can implement the shift register in Figure 20 in a FLEX device using one logic cell per bit , Figure 6 performs the same computation as the parallel filter, but it only processes one bit of the , Figure 6. Fully Serial FIR Filter Schematic n×1 Shift Register n×1 Shift Register n×1 Shift Register n×1 Shift Register n×1 Shift Register n×1 Shift Register n×1 Shift Register Altera
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parallel adder using VERILOG
Abstract: independently forms a 16-bit serial input-parallel output shift register and a parallel input-serial output shift register to read serial input data during output of serial data converted from parallel data , serial input-parallel output and parallel input-serial output shift register function. Independent , data to be read into a shift register during output of serial data converted from parallel data. In , ) At a rising edge of CLK, 16-bit serial data is written into shift register @ from DI. (5) CLK of Mitsubishi
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M66008 cmos 16-bit shift register DO15 M66008P/FP
Abstract: 8-tap FIR filter architecture. This filter has eight 8-bit registers arranged in a shift register , . You can implement the shift register in Figure 20 in a FLEX device using one logic cell per bit , filter in Figure 6 performs the same computation as the parallel filter, but it only processes one bit , Filters in FLEX Devices Figure 6. Fully Serial FIR Filter Schematic n×1 Shift Register n×1 Shift Register n×1 Shift Register n×1 Shift Register n×1 Shift Register n×1 Shift Register Altera
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FIR Filters 5 bit binary multiplier using adders Parallel FIR Filter
Abstract: / F / FS, data input is shifted to the 12-bit internal shift register on the rising edge of a clock , circuit 12-bit shift register 16 VDD Control circuit DATA 2 18 VDD 17 OE 12-bit shift , shift register 18 Q11 CLOCK 3 LCK 4 Q0 5 12-bit storage register Output buffer (open drain , internal shift register. However, when the DATA pin is HIGH, the content of the 12-bit shift register is , the BU2092 / F / FV The content of the 12-bit shift register is stored in the 12-bit storage register ROHM
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BU2090 BU2090F BU2090FS BU2092F BU2092FV SSOP-A16 12bit shift register DIP16
Abstract: / F / FS, data input is shifted to the 12-bit internal shift register on the rising edge of a clock , circuit 12-bit shift register 16 VDD Control circuit DATA 2 18 VDD 17 OE 12-bit shift , shift register 18 Q11 CLOCK 3 LCK 4 Q0 5 12-bit storage register Output buffer (open drain , internal shift register. However, when the DATA pin is HIGH, the content of the 12-bit shift register is , the BU2092 / F / FV The content of the 12-bit shift register is stored in the 12-bit storage register ROHM
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DIP18 SSOP-A18
Abstract: , SN74Asa97A 16·BIT PARALLEL/SERIAL BARREL SHIFTERS merge During the shift and merge instruction (M2 with , , SN74AS897A 16·BIT PARALLEL/SERIAL BARREL SHIFTERS SHIFT OPERATION EXAMPLES Examples of ' AS897 A shift , SN54AS897A, SN74AS897A 16·BIT PARALLEL/SERIAL BARREL SHIFTERS circular shift left or right (M2 = = , 16-bit word in the register/counter five positions to the right. CONTROL SIGNALS SHIFT INSTRUCTION , 16·BIT PARALLEL/SERIAL BARREL SHIFTERS Assume 015-00 contains hex 6174 and register/counter Texas Instruments
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SN74AS897 ctr16 ih21 ik91 D2885 1985-REVISED 16B/32B 168/32B Y15-YO
Abstract: 4.5 to 5.5 TTL TTL 2S Back to Top l 'LS673 ¡ 16-Bit Serial-In, Serial-Out Shift Register with 16-Bit , The 'LS673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A , storage register is connected in a parallel data loop with the shift register and may be asynchronously , shift-register data to provide shift-register status via the parallel outputs. The shift register can be parallel , a 16-bit parallel-in, serial-out shift register. A three-state input/output (SER/Q15) port provides Texas Instruments
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SDYA009C SN54/74LS123 SDLA006A SDYA010 SDYA012 SZZU001B
Abstract: 8-bit parallel data of the shift register into the data latch. A high level inhibits data , shift register, that converts serial data loaded by the processor into 8-bit parallel data. The rising , shift register. Data Latch This is an 8-bit D-type transparent latch that holds 8-bit parallel data , internal shift register: A data bit on the SI pin is shifted into the MSB of the shift register at the , edge of SC (MB88308/9) shifts a data bit on the SI pin into the MSB of the shift register, each bit of -
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MB88306 MB88307 DI 8306 lt 9306 lt 9306 diode nmos shift register MB88308 MB88309 MBB8307 MB88306/7/8/9
Abstract: or parallel output · Storage register with 3-state outputs · Shift register with direct clear · , Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift . o * * register with , specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state FUNCTION , . Parallel outputs in high-impedance OFF-state logic high level shifted into shift register stage 0. Contents , of the shift register is transferred to the storage register and the parallel output stages. STC P -
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8 bit shift register with 9 V vcc ULA001 74 HCT595N hct595n 74HC/HCT595
Abstract: semiconductor integrated circuit which has 12-bit shift register function to execute serial-parali el conversion and parallel-serial conversion. Because a serial-parallel shift register and a parallel-serial shift register are independently built in this IC, it is possible to read serial input data to a shift register , register at the rising edge of shift clock. The shift clock on and after 13th bit is neglected and pin DO , the rising edge of CLK, 12-bit serial data is written from Dl to shift register I. (5)CLK on and -
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jd11
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