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"3bit correction"

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Abstract: -bit architecture using three individual 3-bit stages with error correction. The article also describes a fast , INPUT RESIDUE SIGNAL + SAMPLE AND HOLD N1-BIT (3-BIT) SADC N1-BIT (3-BIT) SDAC ­ G N2-BIT (3-BIT) SADC SAMPLING CLOCK CONTROL OUTPUT REGISTER N2 LSBs (3) N1 MSBs , sample-and-hold (SHA) is digitized by the first-stage 3-bit sub-ADC (SADC)-a flash converter. The coarse 3-bit MSB conversion is then converted back to an analog signal using a 3-bit sub-DAC (SDAC). The SDAC ... Original
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14 pages,
1005.95 Kb

tunnel diode GaAs 12bit ADC BiCMOS AD9235 AD9481 AM687 12 bit adc BiCMOS GaAs tunnel diode MC1650 MOD-815 MT-021 SCHINDLER detail of half adder ic TUNNEL DIODE esaki Diode MT-024 MT-024 MT-024 TEXT
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Abstract: , block diagram, component accuracy, digital error correction, archecture comparison, ADCs, converters , performance characteristics such as architecture, latency, digital error correction, component accuracy, and , ADC with four 3-bit stages (each stage resolves two bits). In this schematic, the analog input, VIN , quantizes it to three bits. The 3-bit output is then fed to a 3-bit DAC (accurate to about 12 bits), and , latency in a pipelined ADC. Digital Error Correction Most modern pipelined ADCs employ a technique ... Maxim Integrated Products
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8 pages,
63.2 Kb

MAX1205 Flash ADC MAX1200 MAX1201 3bit flash adc MAX1425 MAX1426 MAX1444 MAX1446 Digital Comparator for flash ADC ultrasonic adc dac 2-bit flash adc TEXT
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Abstract: ) D8 D7 D6 3-Bit Flash (MSB) 3-Bit DAC Error Correction Logic Output Latch And , the digital error correction logic and used in calculation of the lower significant bits. THEORY OF OPERATION The SPT7870 SPT7870 is uses a two stage subranging architecture incorporating a 3-bit flash , correction logic combines the results of both stages to produce a 10-bit data conversion digital output. The error correction logic incorporates a proprietary scheme for compensation of any internal offset ... Original
datasheet

8 pages,
65.84 Kb

SPT7870SCU SPT7870SCQ SPT7870SCJ SPT7870 10-BIT TEXT
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Abstract: ) D8 D7 D6 3-Bit Flash (MSB) 3-Bit DAC Error Correction Logic Output Latch And , digital error correction logic and used in calculation of the lower significant bits. THEORY OF OPERATION The SPT7871 SPT7871 is uses a two stage subranging architecture incorporating a 3-bit flash MSB conversion stage followed by an 8-bit interpolating folder conversion stage. Digital error correction logic , correction logic incorporates a proprietary scheme for compensation of any internal offset and gain errors ... Original
datasheet

8 pages,
67.4 Kb

SPT7871SCU SPT7871SCQ SPT7871SCJ SPT7871 10-BIT TEXT
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Abstract: Diagram THEORY OF OPERATION The SPT7870 SPT7870 is uses a two stage subranging architecture incorporating a 3-bit , correction logic combines the results of both stages to produce a 10-bit data conversion digital output. The analog signal is input directly to the 3-bit flash converter which performs a 3-bit conversion and in turn drives an internal DAC used to set the second stage voltage reference level. The 3-bit result from the flash conversion is input to the digital error correction logic and used in calculation of the ... OCR Scan
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5 pages,
180.22 Kb

SPT7870 SPTT870 10-BIT TEXT
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Abstract: architecture incorporating a 3-bit flash MSB conversion stage followed by an 8-bit interpolating folder conversion stage. Digital error correction logic combines the results of both stages to produce a 10-bit data conversion digital output. The analog signal Is input directly to the 3-bit flash converter which performs a 3-bit conversion and in turn drives an internal DAC used to set the second stage voltage reference level. The 3-bit result from the flash conversion is input to the digital error correction logic and ... OCR Scan
datasheet

5 pages,
181.94 Kb

SPT7871 Vr010 2clg TMS 2370 10-BIT TEXT
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Abstract: subranging architecture incorporating a 3-bit flash MSB conversion stage followed by an 8-bit interpolating folder conversion stage. Digital error correction logic combines the results of both stages to pro , signal is input directly to the 3-bit flash converter which performs a 3-bit conversion and in turn drives an internal DAC used to set the second stage voltage reference level. The 3-bit result from the flash conversion is input to the digital error correction logic and used in calculation of the upper ... OCR Scan
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5 pages,
112.37 Kb

SPT7870 10-BIT TEXT
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Abstract: BW1237X BW1237X FUNCTIONAL BLOCK DIAGRAM VDDA AINT VSSA VBB 3-bit MDAC SAH AINC VDDD VSSD UDF 3-bit MDAC DO[0] (LSB) DO[1] DO[2] 3-bit MDAC 3-bit MDAC 3-bit MDAC DO[3] DO[4] DO[5] CLK 3-bit 3-bit 4-bit DO[6] DO[7] (MSB) STBY Digital , from the rising edge of the external clock, which is fed to the first 3-bit flash ADC, and the first multiplying DAC (MDAC). The first MDAC reconstructs a voltage corresponding to the first 3bit flash ADC ... Samsung Electronics
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13 pages,
198.87 Kb

udf.3 BW1237X Flash-ADC 0.35Um block diagram of ultrasound scanner 3bit flash adc 30MSPS TEXT
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Abstract: and temperature correction. The MAX1457 MAX1457 is a low-cost/high-performance signal conditioner that in addition to temperature correction, it linearizes a sensor output by establishing 120 piecewise-linear , temperature correction. The high-end device (MAX1457 MAX1457) linearizes a sensor output by establishing 120 , drift of these parameters by adding four 12-bit digital-to-analog converters (DACs); one coarse 3-bit , and gain, and one coarse-offset 3-bit DAC (Figure 1). Its analog output can be scaled from 0.5V to ... Maxim Integrated Products
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datasheet

8 pages,
123.37 Kb

93C66 AN695 bridge transducer 4-20ma transmitter capacitive pressure sensor medical disadvantages of microcontroller MAX1450 MAX1452 MAX1458 MAX1460 REF02 AN-695 93C66 national semiconductor strain gauge sensor microcontroller MAX1457 TEXT
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Abstract: level. The 3-bit result from the flash conversion is input to the digital error correction logic and , VIN T/H 8-Bit Folder ADC (LSB) D9 (MSB) D8 D7 3-Bit Flash (MSB) 3-Bit DAC Error Correction Logic Output Latches and Buffers (TTL) D6 D5 D4 D3 D2 Internal +1.0 V , subranging architecture incorporating a 3-bit flash MSB conversion stage followed by an 8-bit interpolating folder conversion stage. Digital error correction logic combines the results of both stages to produce a ... CADEKA Microcircuits
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datasheet

8 pages,
157.86 Kb

SPT7871SIQ SPT7871SCU SPT7871 Ladder 3-bit 10-BIT TEXT
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