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Part : KIT_AK_3PHASES_DRIVE_V1 Supplier : Infineon Technologies Manufacturer : Rochester Electronics Stock : 2 Best Price : - Price Each : -
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"3 phase signal"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Signal Input Signals RFK Input Signal Circuit Output Signals 5-Phase with DC Driver , ) 4 6 (8) (12) Pulse Speed [kHz] 0.35 3 Power Input : DC36VCurrent : 1.2A/Phase (2Phases , 0.35 0.25 3 fs 500 CSK244-BT DC24V 0.30 4 0.10 5-Phase with DC Driver , 5 Phase with AC Driver Current [A] 0.10 Torque [Nm] 3 Pullout Torque 0 Full , : 0.45°/step (1-2 phase excitation) Input Signals Step Command Pulse Signal (CW Direction Command -
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CSD2112-T PK245-01A CSD2120-T PK243-01A PK244-01A PK266-02A B-174 B-177 B-178 B-181 B-184 B-188
Abstract: phase excitation) Half Step : 0.9°/step (1-2 phase excitation) Excitation Mode Input Signal , Windings off Signal Input Signals 5-Phase with DC Driver DC24V10% 1.6A or DC36V10% 1.6A Maximum , ] PMC 0.35 0.25 3 fs 500 0 (0) Power Input : DC24VCurrent : 1.2A/Phase (2Phases ON , excitation) Half Step : 0.45°/step (1-2 phase excitation) Input Signals Step Command Pulse Signal (CW , Pulse Signal) 5-Phase Stepping Motors Pulse Signal (CW Pulse Signal) All Windings Off AUDIN
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PK268-02A csd2112 wiring diagram pk243 csd2109 pk243 CSD2109-T B-190 B-191 B-192 B-173
Abstract: an external signal, a phase shifter is typically used to shift the phase of a high frequency signal , š2 of the maximum signal amplitude (half power). As an example, the 3 dB bandwidth of a low pass , determine the 3 dB modulation bandwidth of the Skyworks PS094-315 voltage variable phase shifter, operating , device Data Sheet (document # 200240). The procedure is to phase modulate the RF signal applied to the , signal is held constant, the 3 dB modulation bandwidth can be determined as the modulating frequency at Skyworks Solutions
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Abstract: 2001 External Connection Signal 1 High-Side Input Signal from CPU (Phase U) 2 High-Side Input Signal from CPU (Phase V) 3 Low-Side Input Signal from CPU (Phase U) 5 Low-Side , High-Side Input Signal from CPU (Phase V) 3 High-Side Input Signal from CPU (Phase W) 4 Low-Side , 1 (J1) High-Side Input Signal from CPU (Phase V) 3 High-Side Input Signal from CPU (Phase , from CPU (Phase U) 2 High-Side Input Signal from CPU (Phase V) 3 High-Side Input Signal Fairchild Semiconductor
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KDS226 ZNR 471 103 2KV pm3a104k 710 opto coupler DA1 7805 16T202DA1 100KF KRC101S 2N2222 KA5H0280R 474/AC275V
Abstract: /N No. Item Input Signal Test Content Vpal Vse Vsync Vfsç 16 EX Burst Phase Difference , center of EX burst and DL signal. 22 SQ DET +V Detection Signal with the phase delayed from Vf$c 1 , the -90° phase shifter, multiplier, LPF (low pass filter) 1 and V/l converter. A signal delayed by , period of 1/2 fH, so the phase of the EX burst changes every 1 H. - 15 - SONY® CXA1203M/N 3. SQ DET (Sequence Detector) Chrominance signal -AW-(17) SO Burst Flag Gate Fig. 3 The SQ DET detects the color -
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CXA1203 CXA1203M CXA1203N CXA1201 E89750-YA S0P-24P-L01 VS0P-24P-L01
Abstract: structures are shown in Figure 3. All three phase comparators share two inputs, Signal In and Comparator , amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal , . Phase Comparator I is an exclusive OR (XOR) gate. It provides a digital error signal that maintains a 90 phase shift between the VCOâ'™s center frequency and the input signal (50% duty cycle input waveforms , performance. Phase comparator II is an edge sensitive digital sequential network. Two signal outputs are Fairchild Semiconductor
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MM74HC4046 CD4046 MO-153 MTC16 MS-001
Abstract: Semiconductor Corporation 3 Rev. A, May 2003 External Connection Signal Interface 1 (J1) High-Side Input Signal from CPU (Phase V) 3 High-Side Input Signal from CPU (Phase W) Low-Side Input Signal from CPU (Phase U) 5 Low-Side Input Signal from CPU (Phase V) 6 Low-Side Input Signal , GND 1 2 3 4 5 6 7 8 9 C7 33uF 35V C9 33uF 35V Phase W GND C13 104 C18 , 2 1 Phase U 15V GND 15V 15V 11 GND 10 9 15V 8 GND 7 6 15V 5 GND 4 3 GND Fairchild Semiconductor
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H11A817B PHOTOCOUPLER SERIES with gnd of capacitor 33uf 35v OF 7805 capacitor 100nF 104 KA78L05A
Abstract: 2.2.4 Daughter Board Connectors J3 and J4 Signal inputs and outputs for interconnection with the 3-phase , logic high turns phase C's bottom switch on. 11 OC Overcurrent signal from the 3-phase bridge , (Continued) Pin # Signal Name Description 12 INT Interrupt signal from the 3-phase bridge , logic 3-phase bridge gate driver enable signal SPI pin chip select pin for the 3-phase bridge driver , a 3-phase BLDC/PMSM Motor Control Drive board, create a single unit for developing BLDC/PMSM Freescale Semiconductor
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MC56F8006 pmsm motor pmsm HDR 2X6 bldc schematic DC MOTOR DRIVE SCHEMATICS MC56F8006DBUM
Abstract: signal. All timing pulses used in the 1C are produced from this triangular wave. - 3 - SONY , Burst Phase Difference ; 0+0 Phase difference between 1 2 2 the center of EX burst and TH signal , Phase difference be-â'" -T18 tween the center of EX burst and DL signal. 22 SQ DET +V Detection Signal with the phase delayed from Vf»e 1 50mVp-, 1 5.625kHz 4.0Vo-p 4.43MHz CW 350mVp-p Test the phase , DEMOD -
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CXA1200 203M pal 007 E89750A8X CXA1203IWN 24PIN
Abstract: source follower and three phase comparators The three phase comparators have a common signal input and , either capacitively coupled to the phase comparators with a small signal or directly coupled with , OR (XOR) gate It provides a digital error signal that maintains a 90 phase shift between the VCO's center frequency and the input signal (50% duty cycle input waveforms) This phase detector is more , digital sequential network Two signal outputs are provided a comparator output and a phase pulse output National Semiconductor
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CD4046 pll application note CD4046 vco CD4046 application note CD4046 application demodulator PLL CD4046 application CD4046 applications 74VHC4046
Abstract: amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal , . Phase Comparator I is an exclusive OR (XOR) gate. It provides a digital error signal that maintains a 90 phase shift between the VCO's center frequency and the input signal (50% duty cycle input waveforms). , . Phase comparator II is an edge sensitive digital sequential network. Two signal outputs are provided, a comparator output and a phase pulse output. The comparator output is a 3-STATE output that provides a Fairchild Semiconductor
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HC4046 HC4046 pll application note MM74HC4046N M16A PLL cd4046 N16E
Abstract: Figure 3 - Phase Slope vs. Time Figure 3 shows the example data plotted as phase slope vs. time of , phase change between the output signal and the "ideal" output signal ± f ± 280 ppm · · · , rate at which the output signal changes phase with respect to an ideal signal. For the MT9042B, the output signal phase slope is a function of three parameters. This includes the frequency difference , and the ideal phase, and the elapsed time from the initial signal, state or reference change, to the Zarlink Semiconductor
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MSAN-163 TR62411
Abstract: Compatible with 3-phase, 3-wire delta and 3-phase, 4-wire Wye configurations Supplies average active power , . 10 Accumulation of 3-Phase Power . 22 , Maximum Signal Levels Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error1, 2 Gain Error , Description LED Control Output. The LED_CTRL signal multiplexes the indication of phase drop, phase sequence , on each phase. Figure 12 illustrates the instantaneous active power signal and shows how the active Analog Devices
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ADE7762 IEC62053-21 MS-013-AE 220v center tap transformer kwh meter 3 phase kwh meter IC iec 62053 62053-21 ADE77621 RW-28 ADE7762ARWZ1
Abstract: Phase comparator 1 is an exclusive OR(XOR)gate. It provides a digital signal that maintains a 90 phase , digital sequential net works. Three signal outputs are provided, two comparator outputs and a phase pulse , locks the VCO output signal to the input signal with 0 phase shift be tween them. These comparators are , ) Resistor to set VCO bandwidth (driven by VCOIN) Phase comparator 1 1output Signal input Output of the VCO , the VCO output. Phase comparator 1, an exclusive OR gate, provides a digital error signal (PH.CP.l -
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SC11346 ic 555 using as a voltage comparator 555 phase shift 74hc xor gate FSK v.23 SC1134 SCU346 11346C 11346CN
Abstract: IEC62053-21 Less than 0.1% error over a dynamic range of 500 to 1 Compatible with 3-phase 3-wire delta and 3-phase 4-wire Wye configurations Supplies average active power on the frequency outputs F1 and , phase. In order to extract the active power component, the dc component, the instantaneous power signal is low-pass filtered on each phase. Figure 16 illustrates the instantaneous active power signal and , signal. This method is used to extract the active power information on each phase of the polyphase Analog Devices
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ADE7762ARWZ ADE7762ARW ADE7762ARWZ-RL1 ADE7762ARW-RL EVAL-ADE7762EB D05757-0-1/06
Abstract: Figure 3 - Phase Slope vs. Time Figure 3 shows the example data plotted as phase slope vs. time of , phase change between the output signal and the "ideal" output signal ± f ± 280 ppm · · · , rate at which the output signal changes phase with respect to an ideal signal. For the MT9042B, the output signal phase slope is a function of three parameters. This includes the frequency difference , and the ideal phase, and the elapsed time from the initial signal, state or reference change, to the Zarlink Semiconductor
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TR-62411
Abstract: Compatible with 3-phase, 3-wire delta and 3-phase, 4-wire Wye configurations Supplies average active power , . 10 Accumulation of 3-Phase Power . 22 , Maximum Signal Levels Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error1, 2 Gain Error , Description LED Control Output. The LED_CTRL signal multiplexes the indication of phase drop, phase sequence , on each phase. Figure 12 illustrates the instantaneous active power signal and shows how the active Analog Devices
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EVAL-ADE7762EBZ1 D05757-0-8/07
Abstract: amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal , . Phase Comparator I is an exclusive OR (XOR) gate. It provides a digital error signal that maintains a 90 phase shift between the VCO's center frequency and the input signal (50% duty cycle input waveforms). , . Phase comparator II is an edge sensitive digital sequential network. Two signal outputs are provided, a comparator output and a phase pulse output. The comparator output is a 3-STATE output that provides a Fairchild Semiconductor
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VHC4046 74HC4046 application note 74hc4046 for 32 khz 74VHC4046MTC 74hc4046 advance information CD4046 equivalent application
Abstract: , Flexible Signal Acquisition Solution The 82A04 Phase Reference Module extends the capability of the , of the phase reference is based on the acquisition of a clock synchronous to the signal under , trigger, the mainframe triggers on the trigger signal and uses the phase reference information from the , characterize the Phase Reference signal. The signal needs to be stable during the characterization and , non-sinewave reference clock signal in the 2 GHz to 8 GHz range, an additional filter*3 typically is required Tektronix
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DSA8200 CSA8200 DSP frequency 10 ghz TDS8200 RS-232-C
Abstract: comparator output and a phase pulse output. The comparator output is a 3-STATE output that provides a signal , COMP III OUT COMPARATOR IN â'" 3 14 â'" SIGNAL IN VCO OUT â'" 4 13 â'" PHASE COMP II OUT INHIBIT â , COMPARATOR IN SIGNAL IN _ Yioj (oij _._ ^-\ PHASE COMP II OUT 0 3-STATE 1 PHASE PULSES 0 1 0 PHASE , amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal or , Comparator I is an exclusive OR (XOR) gate. It provides a digital error signal that maintains a 90 phase -
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CD4046 vco application note DEMODULATOR CD4046 PIN OUT of CD4046 CMOS PLL phase comparator MM74HC4046SJ MM74HC4046MTC
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