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ATL010A0X43-SR GE Critical Power ATL010A0X43-SR Non-Isolated Power Module 12Vdc, Programmable
ATL010A0X43-SRZ GE Critical Power ATL010A0X43-SR Non-Isolated Power Module 12Vdc, Programmable
LM94023BITME/NOPB Texas Instruments ±1.5°C Temperature Sensor with Multiple Gain, Class-AB Analog Output and WCSP 4-DSBGA -50 to 150
LM94023BITMX/NOPB Texas Instruments ±1.5°C Temperature Sensor with Multiple Gain, Class-AB Analog Output and WCSP 4-DSBGA -50 to 150
HCTS164KMSR Intersil Corporation HCT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP14, CERAMIC, DFP-14

"3 Bit Shift Register"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Q15 Q31 Q15 SRLC16E SRLC16E 32-bit Shift Register MUXF6 D 4 A[3:0] CE Q 4 A B C D Q15 SRLC16E MUXF5 D 4 A[3:0] CE Q Q15 Q63 SRLC16E 64-bit Shift Register UG002_C2 , _012_032901 Figure 2-60: 40-bit Static-Length Shift Register UG002 (v1.3) 3 December 2001 Virtex-II Platform FPGA , look-up table (LUT) as a 16-bit shift register without using the flip-flops available in each slice , register is needed. Each CLB resource can be configured using the 8 LUTs as a 128-bit shift register. This Xilinx
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SRL16 verilog code for 8 bit shift register verilog code for 64 32 bit register verilog code for shift register VHDL of 4-BIT LEFT SHIFT REGISTER vhdl code for 8 bit shift register verilog code for 4 bit shift register SRLC16
Abstract: /Storage Register with Common Parallel I/O Pins 3-STATE 8-Bit Universal Shift/Storage Register Octal Serial , Latches and 3-STATE Serial Output 5 5 MM74HC594 74VHC595 HC CMOS VHC 8-Bit Shift Register with , Static Shift Register 8-Stage Static Shift Register 8-Bit Shift Register/Latch with 3-STATE Outputs 8-Bit , Bipolar-TTL Bipolar-TTL FACT Dual 8-Bit Shift Register 8-Bit Multiple Port Register 8-Input Universal Shift , HCT CMOS 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear 8-Bit Parallel-Out Fairchild Semiconductor
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16 bit universal shift register 16-bit universal shift register 74LCX32646 8bit shift DM93L28 DM93L38 74AC299 74VHC164 DM74LS164 MM74C164
Abstract: SRLC16E SRLC16E Q 32-bit Shift Register MUXF6 D 4 Q A[3:0] CE Q15 SRLC16E D 4 MUXF5 Q A[3:0] CE Q63 Q15 SRLC16E 64-bit Shift Register X465_11_051505 Figure 12 , CASCADABLE 16-bit shift register with enable (SRLC16E) - Device: Spartan-3 Generation Family , for the look-up tables where they are used as 16-bit shift registers. Using this Shift Register LUT , the cascading of any number of 16-bit shift registers to create whatever size shift register is Xilinx
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vhdl code 16 bit LFSR VHDL 32-bit pn sequence generator verilog code 16 bit LFSR vhdl code for pn sequence generator fpga cdma by vhdl examples vhdl code for rs232 receiver using fpga XAPP465 SRL16E RS232 DS228
Abstract: B0 C'3 C'2 C'1 C'0 48bit Shift Register 48 bit Time Counter Shift Register Time Counter B0 D0 B1 D1 B3 48 bit Time Counter Shift Register BCD , PD4990A OE Don't use 8 bit B40 to B47 40 bit Shift Register CLK DATA IN N-ch Open Drain , 52 bit Shift Register48 bit Shift Register 52bit Shift Register 52 bit MSB LSB 48 bit , PD4990AShift RegisterLSBB0 48 bit Shift RegisterB40B47 48 bit Shift Register Last Data First NEC
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S12828JJ4V0UM00 TP4096 CI 74ls07 S12828J PD1990 STB-HL PD4990A24 161HCHBCD PD4990AECRPPC 161HCH FAX044548-7900
Abstract: ) register. TEST DATA IN SELECT MUX A 8-BIT JTAG IR INSTRUCTION (SHIFT) REGISTER B MSB 7 , STATUS (SHIFT) REGISTER, OSR 1 BIT 0 LSB 0 LSB 0 LSB 0 LSB TEST DATA OUT , setting the debug request (DR) bit 3. Polling the MMC20xx OnCE status register 4. Reading/writing an , write-back bus register (WBBR). 3. PC = 32-bit address. Program counter normally is set to the PC value , write-back bus register (WBBR). 3 4 Select CPU scan chain register (CPUSCR) for reading. Shift Motorola
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AN1817 MMC2003 M200 motorola application note AN1817/D MMC20 MMX20 MMC2001R
Abstract: A[3:0] CE Q15 Q31 Q15 SRLC16E SRLC16E Q 32-bit Shift Register MUXF6 D 4 A[3:0] CE Q Q15 SRLC16E MUXF5 D 4 A[3:0] CE Q Q15 Q63 SRLC16E 64-bit Shift Register , cascading of any number of 16-bit shift registers to create whatever size shift register is needed. Each CLB resource can be configured using the 8 LUTs as a 128-bit shift register. This section provides generic VHDL , register, and each bit is shifted to the next highest bit position. In a cascadable shift register Xilinx
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RAM16X1S verilog code for 8 bit fifo register vhdl code for 8 bit register vhdl code for 4 bit shift register SRLC32E SRLC64E vhdl code for shift register UG012
Abstract: buffer between the internal data bus and the transmit shift register. Writing a logic 1 to the TE bit in , shift register. A logic 0 start bit automatically goes into the least significant bit position of the shift register, and a logic 1 stop bit goes into the most significant bit position. When the data in the , SBK bit in SCCR2 loads the shift register with a break character. A break character contains all logic , . After software clears the SBK bit, the shift register finishes transmitting the last break character and -
OCR Scan
10 Bit Shift Register MC68HC05C4A
Abstract: mode 3: Shift register, fixed baud rate (fOSC/12) 8-bit UART, variable baud rate 9-bit UART, fixed , start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit , to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags , . One bit time later, DATA is activated, which enables the output bit of the transmit shift register to , shift out to the left. When the start bit arrives at the leftmost position in the shift register Siemens
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SBUF
Abstract: 20 16 16 16 16 Register Register Register Register Register Quad D-Type Register (3-State) 4 Bit PIPO Shift Register 4 Bit PIPO Shift Register 8 Bit PIPO Shift Register (3-State) 8 Bit PIPO Shift Register (3-State) 8 Bit Shift Register Latch (3-State) 8 Bit Latch Shift Register 4 Word x 4 Bit Register File (3-State) 8 Bit SIPO Shift Register Latch (3-State) 4034B 4094B LS164 HC164 HCT164 , HC299 HC323 HC595 HC597 HC670 HC4094 8 8 8 8 8 Bit Bit Bit Bit Bit SIPO PISO PISO PISO PISO Shift Shift -
OCR Scan
HC165 HC166 LS165 LS173 4021B hc173 CMOS 4000B M54/74 HCT165 HC173 HC194
Abstract: universal shift register 4-bit universal shift register 14-stage binary counter Triple 3-input NAND gate 7 , static shift register Dual 4-bit static shift register Quadruple bilateral switches 5-stage Johnson , Programmable timer Dual 1-of-4 decoder/demultiplexer 1-to-64 bit variable length shift register 4-bit magnitude , -stage static shift register 18-stage static shift register Dual Dual Dual 4-bit 4-bit complementary pair and , flip-flop Dual D-type flip-flop Dual D-type flip-flop 8-bit static shift register 8-bit static shift -
OCR Scan
HEC4047BDB hef4071bp HEC4051B HEF4752 7-stage frequency divider HEF4059BP HEF40374BD HEC4001BDB HEC40 HEC4007UBDB HEC40097BDB HEC40098BDB HEC4011BDB
Abstract: Shift Register Start Bit Detect Parity Check Transmitter Shift Register Char Detect , . Port 3 Mode Register (P3M) and Bit-Rate Generation The divide chain that generates the bit rate is , input to the Shift Register and the start bit detection circuitry. (R) RCVR Data Shift Clock , start bit into the Receiver Shift Register at the center of the bit time. Before the shift actually , parity only, that is enabled by setting the Port 3 Mode Register bit 7 to 1 (Figure 9-8). If even ZiLOG
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UM97Z8X0104
Abstract: : Serial mode 1: Serial mode 2: Serial mode 3: Shift register mode, fixed baud rate 8-bit UART , fOSC/32 1 1 3 9-bit UART Variable Figure 7-8 Special Function Register SBUF (Address , bit position of the transmit shift register and tells the TX control block to commence a transmission , later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first , out to the left. When the start bit arrives at the leftmost position in the shift register (which in Siemens
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515S
Abstract: SN74AHC594DR 74AHC594D SN74AHC594PWR 74AHC594PW 8-Bit Shift Register 8-Bit Output Register with 3-state outputs 3-to-8 Line Decoder Demultiplexer TTL compatabile 8-Bit Shift Register 8-Bit Output Register TTL compatabile 8-Bit Shift Register 8-Bit Output Register with 3-state outputs TTL compatabile , 74HC594PW 8-Bit Shift Register 8-Bit Output Register with 3-state outputs 3-to-8 Line Decoder , '§ 594 8 bit shift register with 8 bit storage register ï'§ 595 8 bit shift register with 8 bit Diodes
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74HCT 74AHC 74AHCT SO-16 TSSOP-16 74HC/HCT
Abstract: . CRC16_MSB: Register Output Bit Value 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 CRC16_LSB: Register Output Bit Value 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 CRC16_MSB: Shift Register DR0 Bit Value 7 6 5 4 3 2 1 0 Shift , the input clock shifts each bit, MSB first, of the input data stream through the Shift register , 0 5 1 4 0 3 0 2 0 1 1 0 0 CRC16_LSB: Register Function Bit Value 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 0 CRC16_MSB: Register Input Bit Value 7 0 6 0 5 1 4 1 3 2 Clock 1 0 Clock selects the input clock from one Cypress Semiconductor
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CRC-CCITT 0xFFFF crc generator CRC-16-CCIT CY8C29/27/24/22 CY8C26/25 CRC-16
Abstract: mode 3: Shift register, fixed baud rate (fOSC/12) 8-bit UART, variable baud rate 9-bit UART, fixed , start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit , Function Register BAUD (Address D8H) Bit No. D8H MSB 7 BD 6 ­ 5 ­ 4 3 ­ ­ 2 , register. The "WRITE to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift , shift register to TXD. The first shift pulse occurs one bit time after that. As data bits shift out to Siemens
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Abstract: . 3 1.5 SHIFT REGISTER , 4-2 4-3 4-4 4-5 4-6 5-1 5-2 Title Page 52 bit Shift Register , bit Shift Register Construction , COMMAND Register 48 Bit Shift Register MPX N-ch OPEN DRAIN DATA OUT CLK DATA IN CS C3 C2 C1 C0 , Timing Pulse Register Hold 3 CHAPTER 1 INTRODUCTION 1.5 SHIFT REGISTER The register of NEC
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87AD UPD74HC02 uCOM-87 what is 74LS07 uCOM-75 TTL 74ls07 IEU-1210
Abstract: Register 8-bit PISO Shift Register Quad 3-State D Flip-Flop w/Common Clock & Reset ON Semi Philips , Counter/Register (3-state) (TTL Compatible) 8-Bit Binary Counter/Register (3-state) 8-Bit Shift Register , /Latch (3-state) MC74VHC595 8-Bit Shift Register (TTL Compatible) MC74VHCT595 8 bit Shift Register w/ Input Flip-Flops 8-Bit Shift Register w/ Input Flip-Flops (TTL Compatible) Octal Bus Transceiver (3 , (TTL Compatible) 8-Bit Shift Register 4-Bit Binary Ripple Counter 4-Bit Binary Ripple Counter 4-Bit -
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VHC07 VHC09 vhc165 TTL nand VHC16245 vhc08 toshiba 74VHC540 VHCT237 VHC00 VHCT00 VHC01 VHC02 VHCT02 VHC03
Abstract: 5.5 TTL TTL 2S Description SN54LS673, SN74LS673 The 'LS673 is a 16-bit shift register and a 16-bit , . SN54LS674, SN74LS674 The 'LS674 is a 16-bit parallel-in, serial-out shift register. A three-state input , . Features l l 'LS673 ¡ 16-Bit Serial-In, Serial-Out Shift Register with 16-Bit Parallel-Out Storage Register ¡ Performs Serial-to-Parallel Conversion 'LS674 ¡ 16-Bit Parallel-In, Serial-Out Shift Register ¡ , SN54LS673, SN74LS673 The 'LS673 is a 16-bit shift register and a 16-bit storage register in a single 24 Texas Instruments
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16-BIT SDLS195 59628860701KA SN54LS674J SN54LS674JT SNJ54LS674FK
Abstract: consists of a 34-bit shift register, a 33-bit latch, and a 33-bit VF tube driver. FEATURES â'¢ Complete , Acquisition Terminal 3 Clock Input Clock Terminal 4 Output 1 Output Shift Register 32 5 Output 2 Output Shift Register 21 6 Output 3 Output Shift Register 22 7 Output 4 Output Shift Register 23 8 Otuput 5 , Output Shift Register 29 25 Output 22 Output Shift Register 3 26 Output 23 Output Shift Register 8 27 , bit read-in stored in a shift register #1, the last data bit read-in is stored in a shift register -
OCR Scan
MSM5328 33-BIT DIP40-P-600 QFP44-P-910-VK QFJ44-P-S650 0014S77
Abstract: ssss Shift the contents of the source register Ws one bit to the right and place the result in the , wddd d11k kkkk Logical shift right the contents of the source register Wb by the 5-bit , the same as Wm. The `m' bits select the operand register Wm for the square. The `A' bit selects , instruction. The `m' bits select the operand register Wm for the square. The `A' bit selects the accumulator , bit number will be placed in the destination register Wd. A result of zero indicates the bit was not Microchip Technology
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KY 3162 DS70030A-
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