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Part Manufacturer Description PDF & SAMPLES
SN54LS395J Texas Instruments PARALLEL IN PARALLEL OUT SHIFT REGISTER
HCTS164KMSR Intersil Corporation HCT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP14, CERAMIC, DFP-14
HCTS299DMSR Intersil Corporation HCT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP20
HCTS299KMSR Intersil Corporation HCT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP20
SN74LS295BN Texas Instruments 4-Bit Right-Shift Left-Shift Registers 14-PDIP 0 to 70
SNJ54LS91W Texas Instruments 8-Bit Shift Registers 14-CFP -55 to 125

"256 Shift Register"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: SCLK. While the output of the shift control register is "HIGH", the OUTn [n=1, 2, 3,., 256] is pulled to VGON. If the output of the shift control register is "LOW", OUTn [n=1, 2, 3,., 256] is pushed , register at the rising edge of SCLK. While the output of the shift control register is "HIGH", the OUTn [n=256, 255, 254,., 1] is pulled to VGON. If the output of the shift control register is "LOW", OUTn [n=256 , part includes a 256stage bidirectional shift register with right and left shift I/O for cascading. The Myson-Century Technology
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CS5850 layout diagram of shift register 100KH OUT255 OUT256
Abstract: S/R S/R 001 002 256 Shift Register S/R S/R 255 256 DO/I OE1 Level Shifter OE2 , V · Bi - directional shift register · Logic supply voltage = 2.7 to 5.5 V · TCP , the falling edge of the 256th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation , /O CPV Shift clock input I The shift register operates in synchronization with the rising Samsung Electronics
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KS0649 G003 G250 G252
Abstract: /O S/R S/R 001 002 256 Shift Register S/R S/R 255 256 DO/I OE1 Level Shifter , V · Bi - directional shift register · Logic supply voltage = 2.7 to 5.5 V · TCP , the falling edge of the 256th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation , /O CPV Shift clock input I The shift register operates in synchronization with the rising Samsung Electronics
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S6C0649 GATE DRIVE TFT
Abstract: part includes a 256-stage bidirectional shift register with right and left shift I/O for cascading. The output of the shift register is then level translated to drive the high voltage output buffer , , the OUTn [n=1, 2, 3,., 256] is pulled to VGON. If the output of the shift control register is "LOW" , register is "HIGH", the OUTn [n=256, 255, 254,., 1] is pulled to VGON. If the output of the shift , DIOL DIOR SCLK RL SHIFT CONTROL REGISTER OE1,2,3 XON VDD VLL ENABLE CONTROL VGON Myson-Century Technology
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CS5852
Abstract: PD4990A OE Don't use 8 bit B40 to B47 40 bit Shift Register CLK DATA IN N-ch Open Drain , 52 bit Shift Register48 bit Shift Register 52bit Shift Register 52 bit MSB LSB 48 bit Shift Register DATA IN Command Register 10 1 10 1 10 1 10 1 10 1 DATA OUT B3 B2 B1 B0 C'3 C'2 C'1 C'0 48bit Shift Register 48 bit Time Counter Shift Register Time Counter B0 D0 B1 D1 B3 48 bit Time Counter Shift Register BCD NEC
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S12828JJ4V0UM00 TP4096 CI 74ls07 S12828J PD1990 STB-HL PD4990A24 161HCHBCD PD4990AECRPPC 161HCH FAX044548-7900
Abstract: it possible to view each shift register as though it were made of 256 rising edge D flip-flops , locations in each shift register is written into the 256 columns of the selected row. Note that the data , parallel from the memory array. Every one of the 256 locations in each shift register are written into from , is interfaced to four internal 256-bit dynamic shift registers each organized as four cascaded 64-bit shift register segments which are accessed serially. One, two, three, or four 64-bit shift register -
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TMS34061 K755 TMS4161 TM4161EV4-15 TM4161EV4-20 TM4161EV4 JULY1984
Abstract: . The sequential access port is interfaced to an internal 256-bit dynamic shift register organized as four cascaded 64-bit shift registers which makes the memory look like it is organized as up to 256 , falls low. This enables the sw/itches connecting the 256 elements of the shift register to the 256 bit , . Every one of the 256 locations in the shift register is written into the 256 columns of the selected row , load the shift register in parallel from the memory array. Every one of the 256 locations in the shift -
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TMS4164 Multiport Video Ram tk cqe TMS4161-15 TMS4164A 536-BIT
Abstract: memory array. Every one of the 256 locations in each shift register is written into the 256 columns of , shift register are written into from the 256 columns of the selected row. Note that the data that is , -bit dynamic shift registers each organized as four cascaded 64-bit shift register segments which are accessed serially. One, two, three, or four 64-bit shift register segments can be sequentially read out after a , each shift register (see TMS4161 functional block diagram). The first column section to be shifted out -
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TMS4161FML MM4164 aajf 5101 RAM GE capacitors 19L series DYNAMIC RAM 65536 TEXAS TM4161GW4 TM4161GY4
Abstract: voltage level of the output is VOFF irrespective of the data of the shift register. 12 263 / 256 , panel gate ON voltage = 38 V · Bi - directional shift register · Logic supply voltage = 2.7 , DIAGRAM VDD VLO VOFF SEL U/D CPV DI/O S/R 001 S/R 002 263 Shift Register S/R , generated I/O at the falling edge of the 263th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left Samsung Electronics
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KS0657 G129 G260 G261 LCD gate driver lcd tft driver
Abstract: STV1 STV2 CPV VCOM VL VDD VSS VEE Level Shift Shift Register Output Circuits OUT1 Shift Register Level Shift Circuits Output Circuits OUT2 Shift Register Level Shift Circuits Output Circuits OUT3 Shift Register Level Shift Circuits Output Circuits OUT4 Shift Register Level Shift Circuits Output Circuits OUT5 Shift Register Level Shift Circuits Output Circuits OUT6 Shift Register Level Shift Circuits Output Texas Instruments
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MPT57605 SGLS116 icom sc 1025 256-OUTPUT OUT251 OUT252 OUT253
Abstract: Shift Shift Register Output Circuits OUT1 Shift Register Level Shift Circuits Output Circuits OUT2 Shift Register Level Shift Circuits Output Circuits OUT3 Shift Register Level Shift Circuits Output Circuits OUT4 Shift Register Level Shift Circuits Output Circuits OUT5 Shift Register Level Shift Circuits Output Circuits OUT6 Shift Register Level Shift Circuits Output Circuits OUT254 Shift Register Level Shift Circuits Texas Instruments
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sgls116a SGLS116A
Abstract: S/R S/R 001 002 256 Shift Register S/R S/R 255 256 DO/I OE1 Level Shifter OE2 , V · Bi - directional shift register · Logic supply voltage = 3.0 to 5.5 V · TCP , the falling edge of the 256th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation , /O CPV Shift clock input I The shift register operates in synchronization with the rising Samsung Electronics
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KS0647
Abstract: to the memory array. Every one of the 256 olt on" n each shift register is written into the 256 , registers in parallel from the memory array. Every one of the 256 locations in each shift register are , -column sections which map directly onto the four segments of each shift register (see TMS4161 functional block , 256 elements of the shift registers disconnected from the corresponding 256 bit lines of the memory , /QE low as RAS falls enables the 256 switches that connect the shift registers to the bit lines and -
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TM4161EP5-20 TM4161EP5-15 TMS4416 TM4161EP5 TM4161
Abstract: /O S/R S/R 001 002 256 Shift Register S/R S/R 255 256 DO/I OE1 Level Shifter , V · Bi - directional shift register · Logic supply voltage = 3.0 to 5.5 V · TCP , the falling edge of the 256th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation , /O CPV Shift clock input I The shift register operates in synchronization with the rising Samsung Electronics
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S6C0647
Abstract: panel gate ON voltage = 38 V · Bi - directional shift register · Logic supply voltage = 2.7 , generated I/O at the falling edge of the 263th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left , G263 . G001 DI/O CPV Shift clock input I The shift register operates in , (when U/D = "L"), is synchronized with the rising edge of CPV and stored in the first shift register Samsung Electronics
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S6C0657 cof lcd 256-CHANNEL
Abstract: -bit bidirectional shift register 80-bit bidirectional shift register, mirror image pin assignment version of LC7940 64-bit bidirectional shift register, M SM 5 27 8 compatible 1/64 to 1/256 duty, 68 commons, serial input, 1 M Hz transmit clock, built-in 68-bit bidirectional shift register and 4-level L C D driver 68 , (bidirectional) 80-bit bidirectional shift register, 1/64 to 1/256 duty, 30 V output voltage 1/64 to 1/256 duty , -leirel LCD driver 80-bit bidirectional shift register, 1/64 to 1/256 duty, 30 V output voltage 1/64 to 1/256 -
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3055a LC79431 Bi-directional shift register LC7981, LC7940 LCD 7 segment display with 13 pins 6.8 TFT LCD panel 3026B LC7582B LC7582E LC7583NA LB9051 LB9052
Abstract: SCLK. While the output of the shift control register is "HIGH", the Xn [n=1, 2, 3,., 256] is pulled to VGG. If the output of the shift control register is "LOW", Xn [n=1, 2, 3,., 256] is pushed to , the rising edge of SCLK. While the output of the shift control register is "HIGH", the Xn [n=256, 255, 254,., 1] is pulled to VGG. If the output of the shift control register is "LOW", Xn [n=256, 255 , high voltage CMOS design. The low voltage part includes a 256stage bidirectional shift register with EUREKA Microelectronics
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TDS7309-0 EK7309 top 256 EN X253 256-O
Abstract: - directional shift register to 38 V. It can operate within the logic voltage 2.7 to 3.6 - , LS : LEVER SHIFTER OE SR : SHIFT REGISTER MODE STV2 Taiwan Memory Technology, Inc , FUNCTION The shift register operates in synchronization with the rising edge of this input This input , , CPV. When L/R = H, the shift register does right shifting operation. ( Input = STV1 and output = STV2 ) When L/R = L, the shift register does left shifting operation. ( Input = STV2 and output = Taiwan Memory Technology
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T67H0001A T67H0001A-Y 263CH OUT261 OUT262 OUT263
Abstract: LATCH ANALOG SWITCH ANALOG OUTPUTS/ INPUTS SHIFT REGISTER CELL #256 AD75019 BUSED CLOCK , 256 latches via PCLK. The serial shift register is dynamic, so there is a minimum clock rate of 20 , register 256 clocks ago appears at the SOUT output. Data in the serial shift register transfers into the , control the switches is clocked serially into a 256-bit shift register and then transferred in parallel , . After the shift register is filled with the new 256 bits of control data, PCLK is activated (pulsed low Analog Devices
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AD75019JP P-44A
Abstract: Register 8-Bit Serial-ln Parallel-Out Shift Register 8-Bit Serial-ln Parallel-Out Shift Register 4-Bit Up , -Bit Binary Up/Down Counter 4-Bit Bidirectional Universal Shift Register 4-Bit Bidirectional Universal Shift Register 4-Bit Parallel Access Shift Register Presettable 4-Bit Binary Ripple Counter 8-Bit Bidirectional Universal Shift Register Octal Inverting Buffer, 3-State Octal Inverter Buffer, 3-State Octal Inverter , -Bit Odd/Even Parity Generator/Checker 9-Bit Odd/Even Parity Generator/Checker 4-Bit Shift Register with 3 -
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bipolar PROM S4LS04 plhs18p8 PLHS18 82HS641 8x60 LM119 LM124 LM139 LM139A PLC18V8Z PLC415
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