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QMS-026-01-SL-D-RA-MG Samtec Inc Board Connector, 52 Contact(s), 2 Row(s), Male, Right Angle, 0.025 inch Pitch, Solder Terminal, Guide Pin, Black Insulator, Receptacle, ROHS COMPLIANT
QSS-025-01-L-D-RA-MTI Samtec Inc Board Connector
QMS-026-02-S-D-RA-MG Samtec Inc Board Connector, 52 Contact(s), 2 Row(s), Female, Right Angle, 0.025 inch Pitch, Solder Terminal, Guide Pin, Black Insulator
QMS-078-01-SL-D-RA-MG Samtec Inc Board Connector, 156 Contact(s), 2 Row(s), Male, Right Angle, 0.025 inch Pitch, Solder Terminal, Guide Pin, Black Insulator, ROHS COMPLIANT
QMS-052-01-SL-D-RA-MG-K Samtec Inc Board Connector, 104 Contact(s), 2 Row(s), Male, Right Angle, Surface Mount Terminal, Plug, ROHS COMPLIANT
QSS-025-02-L-D-RA-MTI Samtec Inc Board Connector

"24 pin" DRAM

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: / Access Time IBM0116405PT1D-60 EDO DRAM 16Mb 4M x 4 IBM0116405PT1D-70 EDO DRAM 16Mb , -70 IBM117805PT3D-60 EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM IBM117805PT3D , NOW NOW NOW NOW NOW NOW NOW N/A N/A N/A N/A N/A N/A N/A EDO DRAM 16Mb 2M x 8 , -60 IBM117805BT3D-70 IBM116165PT3D-60 EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM 16Mb 16Mb 16Mb 16Mb , /A N/A IBM116165PT3D-70 EDO DRAM 16Mb 1M x 16 70ns 33 75 3.3V NOW N/A -
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TC59R1809 IBM025161LG5D60 gm72v16821 MD908 KM48S2020 GM72V1682 MB81141621 MB81141622 MB81G8322 MB81116421 16MEG MB81116422
Abstract: > (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). STMicroelectronics
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TDA7500 TQFP100 loudness,bass,treble TDA7501 SPDIF spi converter spdif input sckm 24X24 TQFP100M
Abstract: , DRAM, audio D/A converter, and other components. Features 3. 4. 1. MP3 (MPEG audio , DRAM is used (when data compression is used). â'¢ Supports both compressed and uncompressed, and , external digital filter or D/A converter circuits DRAM interface â'¢ Supports EDO DRAM (1 to 64 Mb, 2 , ) as external memory â'¢ Supports allocation of a DRAM user area during CD-ROM (MP3) playback , LC78684NE Memory Interface EDO DRAM Interface Timing â'¢ Read Cycle T1 RASB T2 T4 T5 T3 SANYO Electric
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ENN7695
Abstract: , DRAM, audio D/A converter, and other components. Features 3. 4. 1. MP3 (MPEG audio , ) · Provides about 180 seconds of anti-shock play when a 64M DRAM is used (when data compression is , (384 fs) output pin for use with external digital filter or D/A converter circuits DRAM interface · Supports EDO DRAM (1 to 64 Mb, 2 CAS, 16-bit data path) or SDRAM (16 or 64 Mb, 16-bit data path, CAS latency: 2, burst length: full) as external memory · Supports allocation of a DRAM user area during SANYO Electric
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76956 LC78684 MADRS10 MADRS11 QFP80
Abstract: SRAM Mode this pin act as the EMI data line 4. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. I STMicroelectronics
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Orpheus SIGMA 226 st micro decoder sync I2C 28 pin OS11 OS10 filter bus master CPU DSP
Abstract: > (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act STMicroelectronics
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Abstract: 8MB 72 PIN FAST PAGE DRAM SIMM With 1Mx16 5VOLT#1; TS2M3660G#1; #1; Description Features , C D 107.95 ± 0.20 B A 1.27 ± 0.10 0.050 ± 0.004 8MB 72 PIN FAST PAGE DRAM , /WE DRAM /HCAS /WE 1Mx1 /WE DRAM /LCAS 1Mx1 /WE DRAM /HCAS /CAS 1Mx1 /WE DRAM 1Mx16 DRAM /CAS /WE 1Mx16 DRAM /CAS /RAS A0~A9 A0~A9 A0~A9 A0~A9 A0~A9 DQ0 DQ0 DQ0~DQ15 DQ0 DQ0 /RAS /RAS /RAS 1Mx1 /WE DRAM /CAS Transcend Information
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DRAM 1Mx1 TS4M3260 5215G
Abstract: 256K x 36, 512K x 18 IC DRAM CARD - " T IC DRAM CARD q 1 MEGABYTE 256K x 36, 512K x 18 NW E FEATURES PIN , megabyte, IC DRAM card organized as a 256K x 36 bit memory array. It may also be configured as a 512K x , BATTERY BACKUP (BBU) cycle refresh; a very low current, data retention mode. Standard component DRAM , , Micron Technology, Inc. â  I DRAM CARD C â'¢ JEIDA, JEDEC and PCMCIA standard 88-pin IC DRAM -
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MT12D88C25636
Abstract: Controller Character Generator OSD Layer DRAM Interface SRAM Interface Applications Specifications Outline , Characteristics MSync Interface Characteristics I2C-Bus Interface Characteristics DRAM Interface Characteristics DRAM Fast Mode Timing DRAM Slow Mode Timing SRAM Interface Characteristics (TPU 3050 only) SRAM Mode , . 6. 7. 8. Title Definitions CPU Memory Mapping I2C-Bus Interface Subaddressing CPU Subaddressing DRAM , connecting the SRAM instead of the DRAM memory. This data sheet describes the full feature set of the TPU Micronas
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micronas frc tpu3050 6251-349-6PD D-79108 D-79008
Abstract: Controller Character Generator OSD Layer DRAM Interface SRAM Interface Applications Specifications Outline , Characteristics MSync Interface Characteristics I2C-Bus Interface Characteristics DRAM Interface Characteristics DRAM Fast Mode Timing DRAM Slow Mode Timing SRAM Interface Characteristics (TPU 3050 only) SRAM Mode , Subaddressing DRAM Subaddressing Command Subaddressing Data Subaddressing Display Memory OSD Layer Character Set , the DRAM memory. This data sheet describes the full feature set of the TPU 3040. Differences between Micronas Intermetall
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6251-349-5PD
Abstract: ASSESS ENCODER CLOCK DECODER CLOCK IDLE PATTERN DRAM CONTROL AND TIMING DIRECT ACCESS , /ECK A2/DCK DRAM ADDRESS LINES A0/ENO (ENCODER OUT) VBIAS VSS A1/ DEI (DECODER IN , ) encoder and decoder. The FX802 may also be used without DRAM (as a "standalone" CVSD Codec), in which , circuitry for up to 4Mbits of external Dynamic Random Access Memory (DRAM). All functions are controlled , contains: When used with external DRAM, the FX802 has four primary functions: q Speech Storage Speech CML Microcircuits
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FX802J FX802LG CVSD encoder HM51256 HM511000-15 TMS4256 HM511000 FX809 FX802LS
Abstract: · · Operating voltage: 5.0V Long delay time ­ 0.8 seconds (SEL=VSS, 256K DRAM) ­ 0.2 seconds (SEL=VDD/open, 64K DRAM) 25KHz sampling rate Continuous variable delay time Echo generators Sound , consists of a built-in pre-amplifier, onchip oscillator, DRAM interface, 10 bit A/D and D/A converters as , sampling rate of 25KHz when combined with an external DRAM (41256/4164). The HT8955A is superior to an , Negative power supply (GND) 11 A6 O CMOS Out It connects to DRAM A6. 12 A7 O Holtek
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LM386 dram 4164 4164 64k dram 4164 dram bbd delay variable delay audio preamplifier 41256 dram 3000P
Abstract: I^ IIC R D N M T12D 88C 25636 256K x 36, 512K x 18 IC DR AM CA R D IC DRAM CARD FEATURES · JEIDA, JEDEC and PCMCIA standard 88-pin IC DRAM card · Polarized receptacle connector · Industry standard DRAM functions and timing · High-performance, CMOS silicon-gate process · All outputs are fully , refresh standard: 512 cycles every 64ms 1 MEGABYTE 256K x 36, 512Kx 18 N E W I I C DRAM CARD PIN , GENERAL DESCRIPTION The MT12D88C25636 is a 1 megabyte, IC DRAM card organized as a 256K x 36 bit memory -
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jeida dram 88 pin C1992
Abstract: M I in P r iM ^ M T16D 88C 232 2 MEG x 32, 4 MEG x 16 IC DRAM CARD IC DRAM CARD FEATURES · JEID A -, JEDEC- and PCMCIA-standard 88-pin IC DRAM card · Polarized receptacle connector · Industry-standard DRAM functions and timing · High-performance CMOS silicon-gate process · All outputs fully , -Pin Card (DF-1) I C DRAM CARD PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SYMBOL , Part Number Example: MT16D88C232-6 GENERAL DESCRIPTION The MT16D88C232 is an 8-megabyte IC DRAM -
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jeida dram card 5v
Abstract: PRELIMINARY t o i f m m iv i M T12D 88C 436 4 MEG x 36, 8 MEG x 18 IC DRAM CARD IC DRAM CARD FEATURES · JE ID A -, JEDEC- and PCMCIA-standard 88-pin IC DRAM card · Polarized receptacle connector · Industry-standard DRAM functions and timing · High-perform ance CM O S silicon-gate process · , x 18 PIN ASSIGNMENT (End View) 88-Pin Card (DF-1) N E W I C DRAM CARD P IN # 1 2 3 4 5 6 7 , MT12D88C436 is a 16-megabyte IC DRAM card organized as a 4 Meg x 36 bit memory array. It may also be -
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dram card 68 pin
Abstract: n & E O D E R D ECO D Sl CLOCK CLO CK t DRAM CONTROL AND TIMING T lC 5 roI i , timing circuitry for up to 4 Mbits of external DRAM. As a member of the DBS 800 series, it also contains interface and control logic for the â'CBUSâ' serial interface. When used with external DRAM , may be digitized by the CVSD encoder. The resulting bit stream is stored in DRAM. This process also , microcon­ troller for pause reduction. â'¢ Speech Playback Digitzed speech may be read from DRAM and -
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MX802 K23456 NC27105-1201
Abstract: PRELIMINARY |U|IC=RON MT8D88C432 4 MEG x 32. 8 MEG x 16 IC DRAM CARD IC DRAM CARD FEATURES · JEID A -, JEDEC- and PCMCIA-standard 88-pin IC DRAM card · Polarized receptacle connector · Industry standard DRAM functions and timing · High-performance CMOS silicon-gate process · All outputs , View) 88-Pin Card (DF-1) N E W I C DRAM CARD P IN * 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 , : MT8D88C432-6 GENERAL DESCRIPTION The MT8D88C432 is a 16-megabyte IC DRAM card orga nized as a 4 Meg x 32 -
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I1993 1X210 MT8068C432
Abstract: and decoder, as well as control and timing circuitry for up to 4 Mbits of external DRAM. As a member , . When used with external DRAM, the MX802 has four primary functions: â'¢ Speech Storage Speech signals , DRAM. This process also provides readings of the speech signal power level. These readings are used by , DRAM and converted back into analog form by the CVSD decoder. â'¢ Data Storage Digital data derived via the C-BUS from the Modem or system data may be stored in DRAM. â'¢ Data Recovery Digital data -
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MX802J MX802LH8 PLCC-28 a2jd HM51256-15 tms*1024 MX809
Abstract: DRAM MODULE M53620412CW0/CB0 M53620412CW0/CB0 with Fast Page Mode 4M x 36 DRAM SIMM using , 4Mx4bits DRAMs in 24-pin SOJ package and one CMOS 4Mx4 bit Quad CAS DRAM in 28-pin SOJ package mounted on , circuit board for each DRAM. The M53620412C is a Single In-line Memory Module with edge connections and , ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. DRAM , DQ35 A0 - A10 W A0-A10 Vcc .1 or .22uF Capacitor for each DRAM Vss To all DRAMs DRAM Samsung Electronics
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c60 equivalent dram 4mx4 M53620412CW0 M53620412CB0 K4F160411C-B K4P160411C-B
Abstract: comparison connect modes. * Serial host interface * Support CD-DA straight in mode * Support SDRAM/DRAM , and so Device Package on. * Support 1M/4M/8M/16Mx16 SDRAM, 1M/4M x16 DRAM SC9821C LQFP , descriptions 1 Addr O SDRAM/DRAM address pin 4 2 Addr O SDRAM/DRAM address pin 5 3 Addr O SDRAM/DRAM address pin 6 4 Addr O SDRAM/DRAM address pin 7 5 Addr O SDRAM/DRAM address pin 8 6 Addr O SDRAM/DRAM address pin 9 7 VDD3 Silan Microelectronics
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msc85 LQPF-64-10 9344MH 1M/4M/8M/16M LQFP-64-10X10-0 MSC83H MSC80H
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