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ISL28230FBZ-T7 Intersil Corporation Dual Micropower, Low Drift, RRIO Operational Amplifier; DFN8, MSOP8, SOIC8; Temp Range: See Datasheet pdf Buy
ISL78211ARZ Intersil Corporation Automotive Single-Phase Core Regulator for IMVP-6™ CPUs; QFN40; Temp Range: -40° to 105°C pdf Buy
ISL12027AIV27Z Intersil Corporation Real Time Clock/Calendar with EEPROM; SOIC8, TSSOP8; Temp Range: -40° to 85°C pdf Buy

"24 pin" DRAM

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: / Access Time IBM0116405PT1D-60 IBM0116405PT1D-60 EDO DRAM 16Mb 4M x 4 IBM0116405PT1D-70 IBM0116405PT1D-70 EDO DRAM 16Mb , -70 IBM117805PT3D-60 IBM117805PT3D-60 EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM IBM117805PT3D IBM117805PT3D , NOW NOW NOW NOW NOW NOW NOW N/A N/A N/A N/A N/A N/A N/A EDO DRAM 16Mb 2M x 8 , -60 IBM117805BT3D-70 IBM117805BT3D-70 IBM116165PT3D-60 IBM116165PT3D-60 EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM 16Mb 16Mb 16Mb 16Mb , /A N/A IBM116165PT3D-70 IBM116165PT3D-70 EDO DRAM 16Mb 1M x 16 70ns 33 75 3.3V NOW N/A ... Original
datasheet

17 pages,
107.21 Kb

HY514264B ibm025160lg5d-70 IBM025161LG5D-60 gm73v samsung edram IBM025161NG5D-60 hy5117404a km4232w259q-60 IBM025170LG5D-60 KM44S4020AT IBM025171LG5D-70 KM416S1120A KM4232W259Q60 TSOP-50 TOSHIBA GM72V1682 TC59R1809 KM48S2020 MD908 gm72v16821 IBM025161LG5D60 TEXT
datasheet frame
Abstract: > (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). ... STMicroelectronics
Original
datasheet

14 pages,
151.45 Kb

TQFP100 Orpheus OS10 OS11 pram phase change memory sckm spdif input SPDIF spi converter TDA7500 TDA7501 loudness,bass,treble TEXT
datasheet frame
Abstract: , DRAM, audio D/A converter, and other components. Features 3. 4. 1. MP3 (MPEG audio , DRAM is used (when data compression is used). • Supports both compressed and uncompressed, and , external digital filter or D/A converter circuits DRAM interface • Supports EDO DRAM (1 to 64 Mb, 2 , ) as external memory • Supports allocation of a DRAM user area during CD-ROM (MP3) playback , LC78684NE LC78684NE Memory Interface EDO DRAM Interface Timing • Read Cycle T1 RASB T2 T4 T5 T3 ... SANYO Electric
Original
datasheet

24 pages,
205.98 Kb

ENN7695 LC78684NE TEXT
datasheet frame
Abstract: , DRAM, audio D/A converter, and other components. Features 3. 4. 1. MP3 (MPEG audio , ) · Provides about 180 seconds of anti-shock play when a 64M DRAM is used (when data compression is , (384 fs) output pin for use with external digital filter or D/A converter circuits DRAM interface · Supports EDO DRAM (1 to 64 Mb, 2 CAS, 16-bit data path) or SDRAM (16 or 64 Mb, 16-bit data path, CAS latency: 2, burst length: full) as external memory · Supports allocation of a DRAM user area during ... SANYO Electric
Original
datasheet

24 pages,
173.28 Kb

QFP80 MADRS11 MADRS10 LC78684NE LC78684 ENN7695 76956 TEXT
datasheet frame
Abstract: SRAM Mode this pin act as the EMI data line 4. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. I ... STMicroelectronics
Original
datasheet

14 pages,
136.94 Kb

TQFP100 filter bus master CPU DSP OS10 OS11 SPDIF spi converter st micro decoder sync I2C 28 pin TDA7500 TDA7501 SIGMA 226 Orpheus loudness,bass,treble spdif input TEXT
datasheet frame
Abstract: > (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act ... STMicroelectronics
Original
datasheet

14 pages,
108.04 Kb

Orpheus TDA7500 TEXT
datasheet frame
Abstract: 8MB 72 PIN FAST PAGE DRAM SIMM With 1Mx16 5VOLT#1; TS2M3660G TS2M3660G#1; #1; Description Features , C D 107.95 ± 0.20 B A 1.27 ± 0.10 0.050 ± 0.004 8MB 72 PIN FAST PAGE DRAM , /WE DRAM /HCAS /WE 1Mx1 /WE DRAM /LCAS 1Mx1 /WE DRAM /HCAS /CAS 1Mx1 /WE DRAM 1Mx16 DRAM /CAS /WE 1Mx16 DRAM /CAS /RAS A0~A9 A0~A9 A0~A9 A0~A9 A0~A9 DQ0 DQ0 DQ0~DQ15 DQ0 DQ0 /RAS /RAS /RAS 1Mx1 /WE DRAM /CAS ... Transcend Information
Original
datasheet

7 pages,
52.24 Kb

DRAM 1Mx1 TS2M3660G TEXT
datasheet frame
Abstract: 256K x 36, 512K x 18 IC DRAM CARD - " T IC DRAM CARD q 1 MEGABYTE 256K x 36, 512K x 18 NW E FEATURES PIN , megabyte, IC DRAM card organized as a 256K x 36 bit memory array. It may also be configured as a 512K x , BATTERY BACKUP (BBU) cycle refresh; a very low current, data retention mode. Standard component DRAM , , Micron Technology, Inc. ■ I DRAM CARD C • JEIDA, JEDEC and PCMCIA standard 88-pin IC DRAM ... OCR Scan
datasheet

14 pages,
468.68 Kb

TEXT
datasheet frame
Abstract: Controller Character Generator OSD Layer DRAM Interface SRAM Interface Applications Specifications Outline , Characteristics MSync Interface Characteristics I2C-Bus Interface Characteristics DRAM Interface Characteristics DRAM Fast Mode Timing DRAM Slow Mode Timing SRAM Interface Characteristics (TPU 3050 only) SRAM Mode , . 6. 7. 8. Title Definitions CPU Memory Mapping I2C-Bus Interface Subaddressing CPU Subaddressing DRAM , connecting the SRAM instead of the DRAM memory. This data sheet describes the full feature set of the TPU ... Micronas
Original
datasheet

72 pages,
340.21 Kb

tpu3050 micronas frc TEXT
datasheet frame
Abstract: Controller Character Generator OSD Layer DRAM Interface SRAM Interface Applications Specifications Outline , Characteristics MSync Interface Characteristics I2C-Bus Interface Characteristics DRAM Interface Characteristics DRAM Fast Mode Timing DRAM Slow Mode Timing SRAM Interface Characteristics (TPU 3050 only) SRAM Mode , Subaddressing DRAM Subaddressing Command Subaddressing Data Subaddressing Display Memory OSD Layer Character Set , the DRAM memory. This data sheet describes the full feature set of the TPU 3040. Differences between ... Micronas Intermetall
Original
datasheet

72 pages,
569.23 Kb

tpu3050 TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
4. 33 DSRA I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. 34 DSRA I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. 35 DSRA I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. 36 DSRA I/O DSP SRAM
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6618.htm
STMicroelectronics 20/10/2000 41.08 Kb HTM 6618.htm
No abstract text available
/download/0000000-1910130ZC/microprocessor-32-bit-transputer.xls
Microprocessor 21/03/1997 86.5 Kb XLS microprocessor-32-bit-transputer.xls
No abstract text available
/download/74120772-169554ZC/stodram.zip ()
Infineon 07/09/2000 112.08 Kb ZIP stodram.zip
No abstract text available
/download/0000000-410130ZC/dram.xls
Memory 21/03/1997 8668.5 Kb XLS dram.xls
Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. 34 DSRA I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. 35 DSRA I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. 36 DSRA I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6618-v2.htm
STMicroelectronics 14/06/1999 37.01 Kb HTM 6618-v2.htm
33 DSRA I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. 34 DSRA I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. 35 DSRA I/O DSP SRAM Data Line (Input/Output)/DSP DRAM Data Line (Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. 36 DSRA I/O DSP SRAM
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6618-v1.htm
STMicroelectronics 25/05/2000 39.73 Kb HTM 6618-v1.htm
DRAM CORDIC co-processor Programmable PLL to suite wide range of ex - ternal crystal oscillation Host Interface 1 Serial Audio Interface Synchronous Audio Interface SRAM/ DRAM Interface SRA_D0/DRD0 I/O I DSP SRAM Multiplexed Address/Data Line 0/DSP DRAM Data Line 0.When in SRAM Mode these pins act as the EMI multiplexed address and data line 0. When in DRAM Mode they act as the EMI data line 0. 48 SRA_D1/DRD1 I/O I DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM Data Line 1.When in
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6721-v1.htm
STMicroelectronics 25/05/2000 49.29 Kb HTM 6721-v1.htm
with 12.5MHz, 512KB 512KB DRAM. CPU-21A CPU-21A Innovative Research Technologies 04/24/2003 25MHz 68030/68882 CPU board with 4MB shared DRAM, 32-bit DMA, 2 FMB channels, 8 Mailbox /Rev.3 220031 25MHz 68030/68882 CPU board with 4MB shared DRAM, 32-bit DMA, 2 FMB channels , VMEPROM CPU-30ZBE/Rev.4 102261 25MHz 68030/68882 CPU board with 4MB shared DRAM , 16 MB DRAM, 4 MB flash, ethernet, SCSI, floppy, 4 serial I/O channels, 32-bit VMEbus interface
/datasheets/files/kytelabs/vme/force/forcecrossreference.html
KyteLabs 29/10/2007 188.52 Kb HTML forcecrossreference.html
Memory Interface to 128Kb SRAM or 1Mb DRAM CORDIC co-processor Programmable PLL to suite wide range of ex Serial Audio Interface Synchronous Audio Interface SRAM/ DRAM Interface XCHG Interface XDB0 XAB0 XDB1 latches transparent. 49 SRA_D0/DRD0 I/O I DSP SRAM Multiplexed Address/Data Line 0/DSP DRAM Data Line 0.When in SRAM Mode these pins act as the EMI multiplexed address and data line 0. When in DRAM Mode they act as the EMI data line 0. 48 SRA_D1/DRD1 I/O I DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6621.htm
STMicroelectronics 14/06/1999 47.47 Kb HTM 6621.htm
inter-processor communications External Memory Interface to 128Kb SRAM or 1Mb DRAM CORDIC co-processor XAB0 MCLK DSP1 CORE Host Interface 1 Serial Audio Interface Synchronous Audio Interface SRAM/ DRAM Address/Data Line 0/DSP DRAM Data Line 0.When in SRAM Mode these pins act as the EMI multiplexed address and data line 0. When in DRAM Mode they act as the EMI data line 0. 48 SRA_D1/DRD1 I/O I DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM Data Line 1.When in SRAM Mode these pins act as the EMI multiplexed
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6721.htm
STMicroelectronics 20/10/2000 51.1 Kb HTM 6721.htm