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CDB48500-USB Cirrus Logic CDB48500-USB Evaluation Kit
CS5361-DZZR Cirrus Logic Converters - Analog to Digital (ADC) IC 24Bit 114dB 192kHz Multi-Bit ADC
CDB5340 Cirrus Logic Evaluation, Design Tools Eval Bd 101dB 192kHz Mult-Bit Aud ADC
CS5361-KSZR Cirrus Logic Converters - Analog to Digital (ADC) IC 24Bit 114dB 192kHz Multi-Bit ADC
CS5351-DZZR Cirrus Logic Converters - Analog to Digital (ADC) IC 24Bit 108dB 192kHz Multi-Bit ADC

"16-Bit serial in parallel out Shift Register"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: HCT CMOS 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear 8-Bit Parallel-Out , Register 5 5 other 5 5 DM74ALS165 DM74LS165 Bipolar-ALS Bipolar-LS 8-Bit Parallel In/Serial Out Shift Register 8-Bit Parallel In/Serial Out Shift Register 5 5 MM74C165 MM74HC165 74C CMOS HC , Serial In/Parallel Out Shift Register with Asynchronous Clear Dual 8-Bit Shift Register 16-Bit , /Storage Register with Common Parallel I/O Pins 3-STATE 8-Bit Universal Shift/Storage Register Octal Serial Fairchild Semiconductor
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16 bit universal shift register 16-bit universal shift register 74LCX32646 8bit shift DM93L28 DM93L38 74AC299 74VHC164 DM74LS164 MM74C164
Abstract: 675A 54F/74F675A 16-Bit Serial-ln, Serial/Parallel-Out Shift Register Description The 'F675A contains a 16-bit serial in/serial out sh ift register and a 16-bit parallel out storage register. Separate , Serfal-to-Parallel Converter 16-Bit Serial I/O Shift Register 16-Bit Parallel Out Storage Register Recirculating , 25/12.5 4-528 675A Functional Description The 16-bit shift register operates in one of four , Data Output (SO) pin. In the Parallel Load mode, data from the storage register outputs enter the shift -
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74F675A 54F/74F
Abstract: 675A 54F/74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register Description The 'F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate , -Blt Serial I/O Shift Register â'¢ 16-Bit Parallel Out Storage Register â'¢ Recirculating Parallel Transfer , Description The 16-bit shift register operates in one of four modes, as determined by the signals applied to , Serial Input (SI) pin and exits from Q15 via the Serial Data Output (SO) pin. In the Parallel Load mode -
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Abstract: the next shift register in an expanded bus system. The first bit shifted out is DO. 40,41 S8, S8 , the functions of a high speed sixteen bit shift register and parallel data input latches/flip-flops , CLOCK input shifts data out of the shift register. In the four word FIFO mode, four write operations may , . Data on pin 31 (DO) will be the first bit shifted out of the shift register. The data on pin 16 (D15) will be the last bit shifted out of the shift register. Data at these inputs must meet the setup time -
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dp8512 DP8515/DP8515-350/ DP8516/DP8516-350 DP8515/DP8515-350/DP8516/DP8516-350 D-8000 AA32096
Abstract: Revised October 2000 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description Features The 74F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer , converter s 16-Bit serial I/O shift register s 16-Bit parallel out storage register s Recirculating , www.fairchildsemi.com 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register April 1988 74F675A Unit Fairchild Semiconductor
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74F675ASC MS-013 74F675APC MS-011 74F675ASPC MS-001 N24A M24B
Abstract: 74F675A 16-Bit Serial-In Serial Parallel-Out Shift Register General Description Features The 'F675A contains a 16-bit serial in serial out shift register and a 16-bit parallel out storage , Y Serial-to-parallel converter 16-Bit serial I O shift register 16-Bit parallel out storage , 74F675A 16-Bit Serial-In Serial Parallel-Out Shift Register August 1995 Logic Symbols (Continued , Package (P) NS Package Number N24A 7 74F675A 16-Bit Serial-In Serial Parallel-Out Shift Register National Semiconductor
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C1995 N24C RRD-B30M105
Abstract: is a semiconductor integrated circuit which has 24-bit shift register function to execute serial in parallel out conversion and parallel in - serial out conversion. Built in two shift registers for serial in - parallel out and parallel in - serial out are constructed independently, This IC is able to read serial input data into a shift register while output the serial data converting from the parallel , and high noise margin. Built in two shift registers for serial in-parallel out (Shift register 2 Renesas Technology
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R8A66151SP PRSP0032DD-A 32P2X-A 32 Bit serial in parallel out REJ03F0258-0100 24-BIT R8A66151 M66010
Abstract: high speed sixteen bit shift register and parallel data input latches/flip-flops required in high , serial data by the ECL shift register. Data on pin 31 (DO) will be the first bit shifted out of the shift , they drive the SERIAL INPUT pins of the next shift register in an expanded bus system. The first bit , will be parallel loaded into the ECL shift register and Bit 0 will appear at the SO SERIAL OUTPUT , out of the shift register. In the four word FIFO mode, four write operations may occur before a shift -
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DP8515-350V dp8s DP8516-350V DP8516V DP851S SU-10 D0-D15 TL/F/8684-15 D1S-023 DP8515/16 TL/F/8684-19 DP8515/DP8515-350/DP8516/DP8S16-350
Abstract: Revised August 1999 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description Features The 74F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer , converter s 16-Bit serial I/O shift register s 16-Bit parallel out storage register s Recirculating , www.fairchildsemi.com 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register April 1988 74F675A Unit Fairchild Semiconductor
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MS-010 MS-100 DS009587
Abstract: 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description The 'F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate , prevents both shifting and parallel loading. n n n n n n 16-Bit serial I/O shift register 16-Bit , DS009587 www.fairchildsemi.com 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register March , CS is LOW. Functional Description The 16-Bit shift register operates in one of four modes, as Fairchild Semiconductor
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74F675 DS009587-1 DS009587-2
Abstract: zeros. In Mode 3, serial data can neither enter nor leave the register; however.the contents shift to , . In MODE 3, serial data can neither enter nor leave the register,regardless of the nature of the , parallel processor, or (c) three 4-bit parallel processors, merely by changes in the modes of each ALÙ are , function. f. IN â'"loads data on parallel-data lines into register. 0. DATA OUT CONTROL - unloads , alters the overflow indicator. In Mode 3, two's complements the contents of the register. Serial data -
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RCA-CD4057A alu schematic circuit with transistor CD4034A transistor s912 cd4057 tfk 2550 ST Z025 CD4057A CD405 CD40S7A
Abstract: DM74ALS165 8-Bit Parallel In/Serial Out Shift Register tm Features General Description , 2 DM74ALS165 8-Bit Parallel In/Serial Out Shift Register Function Table DM74ALS165 8-Bit , In/Serial Out Shift Register Electrical Characteristics DM74ALS165 8-Bit Parallel In/Serial , DM74ALS165 8-Bit Parallel In/Serial Out Shift Register TRADEMARKS Fairchild Semiconductor , Parallel In/Serial Out Shift Register May 2007 Inputs Shift/Load Clock Inhibit Internal Outputs Fairchild Semiconductor
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DM74ALS165M M16A MS-012
Abstract: '™F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register , â'¢ 16-Blt Serial I/O Shift Register â'¢ 16-Bit Parallel Out Storage Register â'¢ Recirculating , of STCP. The 16-bit shift register operates in one of four modes, as determined by the signals , Parallel Load mode, data from the storage register outputs enter the shift register and serial shifting , 675A 54F/74F675A Connection Diagrams T-r 16-Bit Serial-In, Serial/Parallel-Out Shift -
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Abstract: -tap FIR filter architecture. This filter has eight 8-bit registers arranged in a shift register , : Implementing FIR Filters in FLEX Devices Figure 6. Fully Serial FIR Filter Schematic n×1 Shift Register n , Figure 7. Figure 8. 4 × 2 Shift Register Data In Data Out Data In Data Out To implement two , performed in parallel using LUTs. The following example uses 2-bit positive integers. h(1) = 01, h(2) = 11 , + 1. The serial filter in Figure 6 performs the same computation as the parallel filter Altera
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800-EPLD EPF8820A EPF8452A
Abstract: -tap FIR filter architecture. This filter has eight 8-bit registers arranged in a shift register , : Implementing FIR Filters in FLEX Devices Figure 6. Fully Serial FIR Filter Schematic n×1 Shift Register n , Figure 7. Figure 8. 4 × 2 Shift Register Data In Data Out Data In Data Out To implement two , performed in parallel using LUTs. The following example uses 2-bit positive integers. h(1) = 01, h(2) = 11 , + 1. The serial filter in Figure 6 performs the same computation as the parallel filter Altera
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AHDL adder subtractor 8 bit binary multiplier using adders
Abstract: Serial-to-parallel converter 16-Bit serial I/O shift register 16-Bit parallel out storage register Recirculating , Serial Data Output Parallel Data Outputs Functional Description The 16-Bit shift register operates in , 675A National Semiconductor 54F/74F675A 16-Bit Serial-ln, Serial/Parallel-Out Shift Register General Description The 'F675A contains a 16-bit serial in/serial out shift regis ter and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer -
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Abstract: (MAX4820) The serial interface consists of an 8-bit shift register and parallel latch controlled by SCLK , cycles. When shifting the input data, D7 is the first bit in and out of the shift register. While CS is , from low to high. Each data bit in the shift register corresponds to a specific output, allowing , /MICROWIRE-compatible serial interface. Input data is shifted into an 8-bit shift register and latched to the outputs when CS transitions from low to high. Each data bit in the shift register corresponds to a specific Maxim Integrated Products
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MAX4821 takamisawa relay OMRON latching relay driver takamisawa RELAYS FUJITSU TAKAMISAWA VS TAKAMISAWA VS takamisawa relay 12 MAX4820/MAX4821 T2044-3 U20E-1
Abstract: and it must be high. Expand-0 output loads external serial shift register for 16-bit operation , D7 VCC function Expand-0 output supplies serial data to an external shift register for 16-bit operation. Expand-1 output supplies a clock signal to an external serial shift register for 16-bit , serial data and transfers it in parallel to the buffer register. The data outputs from the buffer , out through output E0 to the serial input of an external shift register and data from the external -
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SN74LS463 LS462 LS165 LS377 SN74LS165 SN74LS377 SN74LS462 300-MM LS463
Abstract: Register General Description The 'F675A contains a 16-bit serial in/serial out shift regis ter and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer , Serial-to-parallel converter 16-Bit serial I/O shift register 16-Bit parallel out storage register Recirculating , Output Parallel Data Outputs Functional Description The 16-Bit shift register operates in one of four , Data Output (SO) pin. In the Parallel Load mode, data from the storage register outputs enter the shift -
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Abstract: 8-tap FIR filter architecture. This filter has eight 8-bit registers arranged in a shift register , Filters in FLEX Devices Figure 6. Fully Serial FIR Filter Schematic n×1 Shift Register n×1 Shift , shift registers at the top of Figure 7 are both serial and parallel. The parallelism in this case is , block. For parallel designs, each extra bit of precision requires one additional LUT. In serial designs , . You can implement the shift register in Figure 20 in a FLEX device using one logic cell per bit Altera
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FIR Filters 5 bit binary multiplier using adders Parallel FIR Filter
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