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Part Manufacturer Description PDF & SAMPLES
CS5525-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC 16Bit Delta Sigma Multi-Range ADC
CS5522-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC 2-Chl 16Bit Bffrd Dlt Sgm Mlt-Rng ADC
CS5523-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC 2-Chl 16Bit Bffrd Dlt Sgm Mlt-Rng ADC
CS5521-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC 2-Chl 16Bit Bffrd Dlt Sgm Mlt-Rng ADC
CS495202-DQZ Cirrus Logic Audio DSP IC; Series:CS49500; DSP Type:Floating Point; Package/Case:144-LQFP; Leaded Process Compatible:Yes; MIPS:200; Operating Temp. Max:85 C; Operating Temp. Min:-40 C RoHS Compliant: Yes
CS495002-CQZ Cirrus Logic Audio DSP IC; Series:CS49500; DSP Type:Floating Point; Package/Case:128-LQFP; Leaded Process Compatible:No; MIPS:240; Operating Temp. Max:70 C; Operating Temp. Min:0 C; Peak Reflow Compatible (260 C):No; Supply Voltage Max:2.5V RoHS Compliant: Yes

"16 bit floating point"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Function ; ; FLO24 16 bit integer to 24 bit floating point conversion ; ; Timing: RND , INT24 72 77 77 24 bit floating point to 16 bit integer conversion Timing: RND 0 1 , . ; Routine VERSION 1.14 ; FLO24 ; ; Function 16 bit integer to 24 bit floating point , ; ; ; 1 46 46 SAT ; INT24 ; ; 24 bit floating point to 16 bit integer conversion , carry bit, is employed in this library of floating point routines. Nearest neighbor rounding with one Microchip Technology
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AN575 FLO32 FPA24 FPD32 integer and floating point numbers IEEE754 IEEE-754 PIC16/17 10F-1C
Abstract: -6 Position Control - Point to Point . . . . . . . . . . . . . . . . . B-7 Position Control - Auxiliary . . . , Revision Module's minor firmware revision number Publication 1756-UM522B-EN-P - February 2003 1-6 , Communication protocol. Drive Communication Protocol Drive Communication is a point to point serial link , Communication) Point/Feedback Data Exchange" to transfer data. The Drive Module sends set point data to the , processor have synchronized communications, normal Set Point/Feedback data transfer can begin Allen-Bradley
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1756-DMD30 1756-DMF30 1756-PA75R A 1756-DMAF 1756-DMCF010 ac motor speed control with scr 1756-DMCF003
Abstract: , signed 32­bit fixed point numbers, character strings, memory arrays, and 8 or 16 bit operands. The application designer who needs floating point or signed 32­bit support in a program running on a NEURON CHIP , operations available in the floating point and signed 32­bit fixed point packages are: - - - - - , floating point, 32­bit fixed point, string, memory array or byte packages respectively. #include #include , structure that represents a floating point number in IEEE754 single precision format. This has one sign bit Echelon
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al298 AL299 AL294 Al295 AL284 AL289 EB175
Abstract: floating point number to the corresponding 16-bit integer. The number returned from the function is usually , 16-bit number can be converted to floating point format. A fixed-point format assumes that the decimal point is located after the least significant bit (lsb) of the operand. The floating point , ;* -; Integer to Floating Point Representation conversion routine. ; Parameter A = (A1, A2) - 16 bit , A2 Note: S is sign bit. Figure 2. Byte Representation of the Floating Point Number To ZiLOG
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TN0004 IEEE 754 ieee floating point TN0001 TN000101-0603 TN0002 TN0003
Abstract: , performs conversion of a floating point number to the corresponding 16-bit integer. The number returned , point representation. Any 16-bit number can be converted to floating point format. A fixed-point format , ;* -; Integer to Floating Point Representation conversion routine. ; Parameter A = (A1, A2) - 16 bit , floating point mantissa is at the left of its most significant bit. Conversion is performed by means of , ;* -; Floating Point to Integer conversion routine. ; Parameter A = (AE, A0, A1, A2) - 32 bit float ZiLOG
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ZAP000101-1201 ZAP0002 ZAP0003 ZAP0004
Abstract: Conversion from the 16-bit Integer to Floating Point Function call - void matrix_conv_int16_to_float (int , signed integer matrix A into the single precision floating point matrix B. Algorithm - Each 16-bit , Matrix Conversion from the Floating Point to the . 14 7.14 Matrix Conversion from Floating Point to 32-bit , matrix A into the single precision floating point matrix B. Algorithm - Each 32-bit signed integer , Point to the 16-bit Integer Function call - void matrix_conv_float_to_int16 (float* Aptr, int* Bptr Freescale Semiconductor
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AN3807 MPC5500 3x3 matrix
Abstract: w/built-in PMMU and FPU TBD 1Q91 68881-16 IB 32-Bit Floating Point Coprocessor 68 ZA YC 68881-20 IB 32-Bit Floating Point Coprocessor 68 ZA YC 68882-16 IB Enhanced 16 MHz 32-Bit Floating Point Coprocessor 68 ZA 2Q90 68882-20 IB Enhanced 20 MHz 32-Bit Floating Point Coprocessor 68 ZA 2Q90 68882-25 IB Enhanced 25 MHz 32-Bit Floating Point Coprocessor 68 ZA 2Q90 68882-33 IB Enhanced 33 MHz 32-Bit Floating Point Coprocessor 68 ZA 2Q90 68HC000-8 IB 16-Bit external/32-Bit internal HCMOS MPU 64 XA -
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68A09 68A21 68B21 68A488 68A50 68b50 68b09 Motorola 68A09 motorola 6809 8 bit Instruction set 68hc811e2 32-BIT MIL-STD-883C 68B09
Abstract: FLOATING POINT ARITHMETIC WITH XA SIGN 1-bit This application note is intended to implement Single , . FPSUB Division of two SP floating point numbers. 3. MANTISSA - This is a 23-bit field , 32­bit IEEE Floating Point: 3. Microprocessor System Design Concepts, Nikitas A. Alexandridis , assumed two floating point numbers F1 & F2 are in IEEE format Format : Fn = fpnh (s.e7:0.m22:16) + fpnl , MICROCONTROLLER PRODUCTS AN701 SP floating point math with XA Author: Santanu Roy Philips Philips Semiconductors
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3F80 0M22
Abstract: FLOATING POINT ARITHMETIC WITH XA SIGN 1-bit This application note is intended to implement Single , . FPSUB Division of two SP floating point numbers. 3. MANTISSA - This is a 23-bit field , 32­bit IEEE Floating Point: 3. Microprocessor System Design Concepts, Nikitas A. Alexandridis , assumed two floating point numbers F1 & F2 are in IEEE format Format : Fn = fpnh (s.e7:0.m22:16) + fpnl , MICROCONTROLLER PRODUCTS AN701 SP floating point math with XA Author: Santanu Roy Philips Philips Semiconductors
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ieee 32 bit floating point multiplier
Abstract: . FPSUB Division of two SP floating point numbers. 3. MANTISSA - This is a 23-bit field , ). Normalized Mantissa bits (23), e.g., convert 1.0 to a 32­bit IEEE Floating Point: 3 , assumed two floating point numbers F1 & F2 are in IEEE format Format : Fn = fpnh (s.e7:0.m22:16) + fpnl , Philips Semiconductors Application note SP floating point math with XA AN701 Author: Santanu Roy, MCO Applications Group, Sunnyvale, California IEEE SINGLE PRECISION FLOATING POINT Philips Semiconductors
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EXCESS-127
Abstract: generation · 32/64-bit floating point reciprocal, absolute value, compares, and 1/sqrt operations · 32 to 64-bit floating point conversions M Unit · 16 x 16-bit fixed point multiplies · 24 x 24-bit fixed point multiplies · 32 x 32-bit fixed point multiplies · 32 x 32-bit single precision floating point , arithmetic and compare operations · 32/64-bit floating point arithmetic and compare operations (IEEE single and double precision) · 32-bit fixed point logical operations L Unit (continued) · Fixed/floating Texas Instruments
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C67x Architecture of TMS320C67X Lddw convert 24bit to 40bit architecture tms320c6x Mpy24 TMS320C67 TMS320C6 TMS320C62 MPY24 MPY24H SPRV034
Abstract: integer Convert floating point to unsigned integer with round to zero - Join two 16-bit integers , Floating point absolute value Floating point add Floating point add and subtract Clear floating point register Floating point compare Floating point graphics compare Floating point magnitude compare Floating point copy sign Extract mantissa Extract integer Convert integer to floating point Unsigned integer to floating point Extract integer Floating point multiply Floating point multiply and add Motorola
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DSP96002 DSP96000 DSP96KCC
Abstract: precision ALU data rate (ECL) 100 MIPS integer data rate (ECL) Six data formats 64-bit floating point (DEC and IEEE) 32-bit floating point (DEC and IEEE) 64-bit integer (fixed point) 32-bit integer (fixed , comprise BIT'S family of high performance single-chip floating point processors: The B2130 has a TTL , in test features include scan paths through all registers. 72 V BIT Single-Chip Floating Point , multiplications and integer multiplications for 8-, 16- and 32-bit integers. The DIV/SQRT block performs floating -
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B3130 B4130 B41301 51 ti jbr TI31 I321 B2130/B3130/B41301 B2110A/B2120A B3110A/B3120A
Abstract: ) with 32-Bit Floating Point Unit, Plus four 32-Bit Fixed Point Parallel DSPs (PPs), 50 Kbytes fast , ) KGD 40 MFLOPS, 32-Bit Floating Point DSP, 4K ROM,2-1K word RAM, 64 word Cache, two Serial Ports, two 32-Bit Data Buses (24- and 13-Bit address), Ada Compiler 50 MFLOPS, 32-Bit Floating Point DSP , Floating Point DSP, SGUS017 Boot ROM, two 1K word RAM, 128 word Cache, SGUS017 6 Comm. Ports, two 32-Bit Data Buses, (31-Bit Address), JTAG, Ada Compiler 33 MIPS, 16-Bit Fixed Point DSP, SGUS020 Boot ROM Texas Instruments
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320F240 SCTD002 missile seeker military processors SMJ55161 SMJ44C256 military switch RS-485 54ABTH18 SNJ54ABT16XXX SNJ54LVT16XXX SNJ54ABT32316
Abstract: )|)[!¿ations and integer multiplications for 8-, 16- and 32-bit integers. floating point square root ,   BIT Sing.e Ch.p B2130/B3130/B4130 Floating Point Processors T-/V9-U-05 _ Mode Register 16 â'" 13 , â¡ â¡001,33 â¡ â  BIT T^y?-, B2130/B3130/B4130 Single Chip Floating Point Processors Features , integer data rate (ECL) â  Six data formats 64-bit floating point (DEC and IEEE) 32-bit floating point , Single-Chip Floating Point Processor BIPOLAR INTEGRATED M7E D â  1451454 DODO^ 2 â  BIT Bipolar t -
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uns tread T-49-T2-05 SS2130 equivalent B2110A B2120A Y59 r 130 111111111111111111111111T-
Abstract: .754 and DEC (F&G) formats. â  Four data formats 64-bit floating point 32-bit floating point 64-bit , Absolute value Items within braces are alternative items, one of them must be used 64 bit floating point , Indicates sticky bit 32 bit floating point number Indicates a wrapped number_ This Material Copyrighted , flag always contains the last bit to leave the ALU. Floating point arithmetic operations usually reset , // Bipolar [ Integrated f\ Technology, Inc. B3110/B3120 B2110/B2120 Floating Point Chip -
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B3110 B3T10 PZK 20 B3I10/B3120 B3110- B3120-7 B2110- B2120-7 B3110/B2110
Abstract: Floating Point - 64-Bit Double-Precision Floating Point The SMJ34082 is a high-speed floating point , cycle. A 64-bit double-precision floating point operand is input in two cycles. Transfers to or from the , SM J34082 FLOATING POINT PROCESSOR SEPTEMBER 1969 Military Temperature Range: - 55°C to 125°C Operates as a SMJ34020 Floating Point Graphics Coprocessor or as a Standalone Floating Point Processor , 16-blt sequencer and a three-operand FPU (source A, source B, destination) with twenty-two 64-bit -
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40-MH SMJ34082-40 32-MH SMJ34082-32 145-PIN
Abstract: /TMS320C6712 are general purpose 32-bit, floating point DSPs. Each DSP processor has a total onchip memory of , floating point mac, add, subtract, 2 loads with address pointer updates. It requires atleast six 32-bit , -2116x SHARC DSPs are a second generation family of general purpose 32-bit, floating point DSPs. They are , point data formats. The DSP supports two floating point data formats, single precision 32-bit (24 bit , floating point or 40 bit floating point inputs. For 32 bit fixed point multiplies, you can send the upper Analog Devices
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ADSP-21161 TMS320C6711 TMS320C6712 TMS3206712 tms320c67xx features architecture TMS320C67XX* internal architecture Architecture of TMS320C67xx TMS320C67XX addressing modes of TMS320c67XX internal Architecture of TMS320C67xx ADSP21161 TMS320C6711/TMS32C6712
Abstract: BIT SPARC Floating Point Controller Features Description Fully compatible with the SPARC coprocessor interface definition Supports high performance floating point calculations using the BIT B5110/B5120 Contains an on-chip 4 x 64-bit internal floating point instruction queue Supports a 32 x 36-bit , the BIT SPARC IU Supports separate floating point load/store memory access paths Utilizes the parity , bus 80 MHz operation ECL 10KH compatible interface The BIT SPARCâ"¢ Floating Point Controller is an -
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B5100 B5210 B5110 CA10 instruction set Sun SPARC T6 B5120 12930D MKTG-D011
Abstract: M AN670 Floating Point to ASCII Conversion Authors: Table 2 depicts Microchip's 32-bit floating point register RAM usage. The bit labeled "S" is the sign bit. These registers are collectively , ASCII equivalent. This document shows a specific example of converting a 32-bit floating point number to ASCII. Application note AN575 contains 24-bit and 32-bit floating point routines. A subroutine is , AN575 describes the Microchip format of 24 and 32-bit floating point numbers. We will use the 32-bit Microchip Technology
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FXD3216U 16C74A math16 AN617 INT3232 P16C74a QS-9000
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