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CS495314-CVZR Cirrus Logic Color Signal Decoder, PQFP128, LEAD FREE, LQFP-128
CS49DV8C-CVZR Cirrus Logic Consumer Circuit, PQFP128, LEAD FREE, LQFP-128
CS495314-DVZR Cirrus Logic Color Signal Decoder, PQFP128, LEAD FREE, LQFP-128
CS49DV8C-CVZ Cirrus Logic Consumer Circuit, PQFP128, LEAD FREE, LQFP-128
CS495313-DVZ Cirrus Logic Color Signal Decoder, PQFP128, LEAD FREE, LQFP-128
CS495313-CVZR Cirrus Logic Color Signal Decoder, PQFP128, LEAD FREE, LQFP-128

"128 cam"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 256 16 32 128 256 256 4096 8 8 8 16 16 40 24 16 16 CAM Block (bits) 256 1K 2K , control logic. - - - XCV50 implementation = CAM 32 x 16, (26% of the slices), 86 LUTs, 128 shift registers (or LUTs), and 43 slice registers XCV300 implementation = CAM 128 x 40, (49% of the , , and nine slice registers. XCV300 implementation = CAM 128 x 8 in one column (SelectRAM+ block and , . XCV1000 implementation = CAM 256 x 8 in one column (SelectRAM+ block and adjacent CLB), 226 LUTs, 128 Xilinx
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SRL16 XC4000X XAPP202 XAPP203 XAPP204 RAM16X1 limit switch cam type XAPP201 block selectram overview XCV400
Abstract: words. The MU9C1965A LANCAM MP is a 1024 x 128-bit CMOS contentaddressable memory (CAM) with a 32-bit I , . Techniques are available that split the data word into individual 128-bit CAM words. Each CAM word is , 128 bits CAM, 0 bits RAM, and use Mask Register 1 for compares. The CAMs are also configured for , compares without Mask Register 1). Line 22 configures the CAMs as 128 bits CAM, 0 bits RAM, and invoke no , register: 128 CAM, 0 RAM, MR1, Enhanced Response mode Set Persistent destination to MR1 Segment 0: TAG MUSIC Semiconductors
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AN-N19 TAG 226 0x0000FFFE 0264H 0x02180000
Abstract: bits ENCODE_2_MSB (CAM 64 words), three bits ENCODE_3_MSB (CAM 128 words) and four bits ENCODE , words), two bits DECODE_2 (CAM 64 words), three bits DECODE_3 (CAM 128 words) and four bits DECODE , Author: Jean-Louis Brelet XAPP204 (v1.2) May 2, 2000 Summary CAM (Content Addressable Memory) offers increased data search speed. In various applications based on CAM, there are differing , . Application note XAPP201, "An Overview of Multiple CAM Designs in Virtex Devices", discusses the diverse Xilinx
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vhdl code for 8 bit ram vhdl code for memory in cam 16 bit register VERILOG 16 word 8 bit ram using vhdl 8 bit data bus using vhdl XCV50E
Abstract: · x 128 Synchronous Ternary CAM Architecture x 128 Local Mask Words allow masking of each CAM word on a bit by bit basis. Match Flag times: 25/28 ns CAM Index output (pipeline mode): 14/16 ns , 64 128 1K x 128 CAM Array 64 MUX Comparand Bus CBUS 1K x 128 Mask Array CAM Word , Type field. Reads "001 1001" for 1K x 128 IPCAM-1. This CAM Type field is read only. Reserved. Will , it a Ternary CAM. The Ternary nature of this CAM is useful for storing subnet masks, implementing Netlogic Microsystems
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NL82721R NL82721 nfa 102 ipCAM ethernet module Ternary CAM NLM82721R-33 NLM82721R-25 NLM84721R-25 NLM84721R-33
Abstract: Comparison Note (1) APEX 20KE CAM Virtex-E CAM (2) Dimension of Widest CAM 32 × 5,120 128 × , CAM Virtex CAM 1,024 × 128 256 × 64 512 × 64 2,048 × 64 4,096 × 64 4,096 × 32 CAM , CAM Comparison: APEX 20KE vs. Virtex-E Devices Technical Brief 61 December 1999, ver. 1 , ://www.altera.com https://websupport.altera.com Content-addressable memory (CAM) is a memory technology that searches for data by its content rather than its address. When compared to RAM, CAM significantly reduces Altera
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EP20K200 XCV1000E EP20K200E EP20K200E-1 security cam ternary
Abstract: bits ENCODE_2_MSB (CAM 64 words), three bits ENCODE_3_MSB (CAM 128 words) and four bits ENCODE , DECODE_1 (CAM 32 words), two bits DECODE_2 (CAM 64 words), three bits DECODE_3 (CAM 128 words) and four , 1, 1999 Application Note: Jean-Louis Brelet Summary CAM (Content Addressable Memory) offers increased data search speed. In various applications based on CAM, there are differing requirements for , XAPP201, "An Overview of Multiple CAM Designs in Virtex Family Devices", discusses the diverse solutions Xilinx
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RAM16x1S xapp204.zip XCV100 XCV150 XCV200 XAPP130
Abstract: CAM Virtex-E CAM(2) CAM 32 × 5,120 128 × 160 CAM 5,120 × 32 2,560 × 8 (1 , 20KE CAM Virtex CAM 1,024 × 128 256 × 64 512 × 64 2,048 × 64 4,096 × 64 4,096 × 32 , CAM APEX 20KE vs. Virtex-E Technical Brief 61 December 1999, ver.1 Altera Corporation , ://www.altera.com/japan E-mail: japan@altera.com Content-Addressable MemoryCAM RAM CAM CAM APEXTM 20KE CAM PLD CAM CAM CAM CAM APEX 20KE CAM APEX - IPv4 - CAM APEX 20KE Altera
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EP20K1000E 20KECAM XCV1000E-8 M-TB-061-01/J 48CAM 48CAM96S
Abstract: Performance Read/Write CAMs Figure 2 shows the read mode of a 128-word x 9-bit CAM built on four block , _02_072401 Figure 2: CAM 128-word x 9-bit in Read Mode In a write mode, a 7-bit bus is used as an address for the 128 x 9 CAM. This address bus is composed of a 5-bit bus to each set of CAM32x9 address inputs and a 2-bit bus decoded to select one of the CAM blocks. To write 9-bits of data to one of the 128 , a 64-word CAM requiring seven address lines and a 128-word CAM requiring six address lines Xilinx
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XAPP260 RAM32x1S CAM32x9 verilog code for word recognition XC2V40 XC2V250 CAM32
Abstract: . Features · · · · · · x 128 Synchronous Ternary CAM Architecture x 128 Local Mask Words allow masking of each CAM word on a bit by bit basis. Match Flag times: 25/28 ns CAM Index output (pipeline , 64 128 1K x 128 CAM Array 64 MUX Comparand Bus CBUS 1K x 128 Mask Array CAM Word , 1001" for 1K x 128 IPCAM-1. This CAM Type field is read only. Reserved. Will read `0'. This bit must , it a Ternary CAM. The Ternary nature of this CAM is ideal for enabling policy enforcement and packet Netlogic Microsystems
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NLM83721R-25 NLM83721R-33
Abstract: fits into each LUT. A 32-word by 16-bit CAM would require 128 LUTs. The write operation uses the shift , -word CAM requiring six address lines, or a 128-word CAM requiring seven address lines and onward , bits ENCODE_2_MSB (CAM 64 words), three bits ENCODE_3_MSB (CAM 128 words) and four bits ENCODE , DECODE_2 (CAM 64 words), three bits DECODE_3 (CAM 128 words) and four bits DECODE_4 (CAM 256 words). , Content Addressable Memories (CAM) allow a fast search for specific data in a memory. Each application has Xilinx
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SRL16E vhdl code for 4-bit counter xapp203.zip vhdl code of 4 bit comparator x203 vhdl code download for memory in cam
Abstract: Synchronous Ternary CAM Architecture 1K x 128 Local Mask Words allow masking of each CAM word on a bit by , Comparand Register 1K x 128 CAM Array 64 M UX Comparand Bus CBUS 1K x 128 M ask Array CAM , . Reads "001 1001" for 1K x 128 IPCAM-1R. This CAM Type field is read only. Reserved. Will read `0'. , store a "don't care" state for compare operations (in addition to `0' and `1') making it a Ternary CAM. The Ternary nature of this CAM is useful for storing subnet masks, implementing policy based routing Netlogic Microsystems
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netlogic CAM ternary content addressable memory NetLogic ternary netlogic Content Addressable Memory NL82721R-33 NL82721R-40
Abstract: for each search Yes - CAM 128 x 40-bit in 12 ns No - CAM 128 x 40-bit in 36 ns Yes No , CAM enables accelerated data searches to be performed in a storage array. CAM is well suited for many , application. Smaller CAM applications are configurable in Virtex devices through the use of internal SRL shift registers, True Dual-PortTM block RAM, and distributed RAM. For larger-scale CAM applications , interface to external CAM designs. CAM Definition CAM is designed to enhance data retrieval speed from Xilinx
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VTT001 NetLogic Ternary Content Addressable network search engine netlogic Priority Encoder CAM Sibercore Technologies XAPP242
Abstract: · 1K x 128 Synchronous Ternary CAM Architecture 1K x 128 Local Mask Words allow masking of each , Package 127 0 64 Global M ask Registers 0 & 1 32 128 Status Register CAM W ord , Comparand Register 1K x 128 CAM Array 64 M UX Comparand Bus CBUS 1K x 128 M ask Array CAM , "001 1001" for 1K x 128 IPCAM-1R. This CAM Type field is read only. Reserved. Will read `0'. This bit , store a "don't care" state for compare operations (in addition to `0' and `1') making it a Ternary CAM Netlogic Microsystems
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RBUS12 ipCAM 292-P
Abstract: station manager calls for up to 128 mobile stations; therefore, a 128-word CAM is required. Such CAM , transceiver station typically supports up to 128 cell phones simultaneously, CAM in APEX devices provides an ideal solution: one 128 × 32 CAM requires only four ESBs. By integrating the CAM into the APEX device , White Paper ® Designing Wireless Base Stations with APEX CAM Introduction Content addressable memory (CAM) can be used to run fast searches within a system. When a system supplies the initial Altera
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mobile switching centre GSM Network Station SubSystem visitor location register base station controller IS-95
Abstract: transformed into a CAM memory with 128 entries of 48 bits in width. Each bit can have one of three values: 0 , CAM block. If a single match is found, the 128-bit CAM output word is encoded into an address, which , 128 MFB A 128 MFB B Encoder and Match Logic 9 To increase the depth of the CAM, the , Content Addressable Memory (CAM) Applications for ispXPLD Devices TM July 2002 Application Note AN8071 Introduction Content Addressable Memory (CAM) is a type of memory that compares the Lattice Semiconductor
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Condensed Data Book 1977 computer Network Types diagram computer networking diagram AN-8071 128x48 5000MX 1-800-LATTICE
Abstract: Synchronous Ternary CAM Architecture 1K x 128 Local Mask Words allow masking of each CAM word on a bit by , Validity Bits 64 128 Comparand Register Global M ask Registers 0 & 1 1K x 128 CAM Array 64 M UX Comparand Bus CBUS 1K x 128 M ask Array CAM W ord 0 Local M ask W ord 0 CAM W ord , CAM Type 802.3 802.5 P/FL SRd RSV 001 1001c Hex 0 0 0 0 c 001 1001 indicates a 1K x 128 , b0 C_MAP CAM Type field. Reads "001 1001" for 1K x 128 IPCAMTM. This CAM Type field is read only Netlogic Microsystems
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mcr 72 hpm 06 NFA 222 CBUS63-CBUS0 nfa 223 1kx12 counter up/down
Abstract: This Application Brief covers the use of the MU9C1965A/L content-addressable memory (CAM) in ATM edge switches. The width of this device, 128 bits, makes it possible to use it for translating from 48-bit LAN , of the 128-bit width is a great benefit here: on the next cycle, 32 bits of data are available from the CAM without further table lookups. Hence the ATM virtual path and virtual connection information are available immediately. In the reverse direction, the cell header is used as input to the CAM and MUSIC Semiconductors
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MU9C4320L Music Semiconductors network AB-N12
Abstract: Synchronous Ternary CAM Architecture 1K x 128 Local Mask Words allow masking of each CAM word on a bit by , 64 128 Comparand Register Global M ask Registers 0 & 1 1K x 128 CAM Array 64 M UX Comparand Bus CBUS 1K x 128 M ask Array CAM W ord 0 Local M ask W ord 0 CAM W ord 1023 Local M , CAM Type 802.3 802.5 P/FL SRd RSV 001 1001c Hex 0 0 0 0 c 001 1001 indicates a 1K x 128 , . Reads "001 1001" for 1K x 128 IPCAM. This CAM Type field is read only. When set to `1' this bit enables Netlogic Microsystems
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Select 642 UX NL82721-33 NL82721-40
Abstract: programmable pulse generator designed to replace a mechanical cam. The irst of its kind, the PCS1110 chip , mechanical cam would perform. Unlike a mechanical cam, which can only perform â'˜ixedâ'™ movements, the PCS111 allows the designer to modify the cam proile throughout the motion. Internal RAM permits the operational pattern of the secondary axis to be programmed with up to 128 different points. Also possible is , â'˜slaveâ'™ cam control off of one â'˜masterâ'™ motion proile, an impossibility with a mechanical cam -
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Abstract: the wide Comparand for Virtual LANs, VC translation, or IPV6 address recognition. The 128-bit CAM , , organized in 128-bit data fields. Each data field can be partitioned into a CAM and a RAM subfield on 32 , Register set /RESET Condition Skip = 0, Empty = 1 (empty) Enabled 128 bits CAM, 0 bits RAM Disabled , . The CAM portion of each word may be sized from a full 128 bits down to 32 bits in 32-bit increments , Empty). By default, all words are configured to be 128 CAM cells. However, bits 8­6 of the Control MUSIC Semiconductors
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MU9C1965L 1965L
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