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"128 cam"

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Abstract: 256 16 32 128 256 256 4096 8 8 8 16 16 40 24 16 16 CAM Block (bits) 256 1K 2K , control logic. - - - XCV50 XCV50 implementation = CAM 32 x 16, (26% of the slices), 86 LUTs, 128 shift registers (or LUTs), and 43 slice registers XCV300 XCV300 implementation = CAM 128 x 40, (49% of the , , and nine slice registers. XCV300 XCV300 implementation = CAM 128 x 8 in one column (SelectRAM+ block and , . XCV1000 XCV1000 implementation = CAM 256 x 8 in one column (SelectRAM+ block and adjacent CLB), 226 LUTs, 128 ... Xilinx
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datasheet

6 pages,
39.1 Kb

XCV50 cam memory circuit cam memory circuit design RAM16X1S SRL16 SRL16E XAPP202 XAPP203 XAPP204 XCV400 XCV300 XC4000X block selectram overview XAPP201 limit switch cam type RAM16X1 TEXT
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Abstract: words. The MU9C1965A MU9C1965A LANCAM MP is a 1024 x 128-bit CMOS contentaddressable memory (CAM) with a 32-bit I , . Techniques are available that split the data word into individual 128-bit CAM words. Each CAM word is , 128 bits CAM, 0 bits RAM, and use Mask Register 1 for compares. The CAMs are also configured for , compares without Mask Register 1). Line 22 configures the CAMs as 128 bits CAM, 0 bits RAM, and invoke no , register: 128 CAM, 0 RAM, MR1, Enhanced Response mode Set Persistent destination to MR1 Segment 0: TAG ... MUSIC Semiconductors
Original
datasheet

16 pages,
113.1 Kb

MU9C1965A AN-N19 0x02180000 0264H 0x0000FFFE TAG 226 TEXT
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Abstract: bits ENCODE_2_MSB (CAM 64 words), three bits ENCODE_3_MSB (CAM 128 words) and four bits ENCODE , words), two bits DECODE_2 (CAM 64 words), three bits DECODE_3 (CAM 128 words) and four bits DECODE , Author: Jean-Louis Brelet XAPP204 XAPP204 (v1.2) May 2, 2000 Summary CAM (Content Addressable Memory) offers increased data search speed. In various applications based on CAM, there are differing , . Application note XAPP201 XAPP201, "An Overview of Multiple CAM Designs in Virtex Devices", discusses the diverse ... Xilinx
Original
datasheet

19 pages,
82.68 Kb

verilog code for 16 bit ram vhdl code download for memory in cam XAPP203 16 bit register vhdl xapp204.zip XAPP201 XCV100 XCV150 XCV200 XCV300 XCV400 XCV50 XCV50E 8 bit data bus using vhdl 16 word 8 bit ram using vhdl XAPP204 XCV1000 16 bit register VERILOG vhdl code for memory in cam vhdl code for 8 bit ram TEXT
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Abstract: · x 128 Synchronous Ternary CAM Architecture x 128 Local Mask Words allow masking of each CAM word on a bit by bit basis. Match Flag times: 25/28 ns CAM Index output (pipeline mode): 14/16 ns , 64 128 1K x 128 CAM Array 64 MUX Comparand Bus CBUS 1K x 128 Mask Array CAM Word , Type field. Reads "001 1001" for 1K x 128 IPCAM-1. This CAM Type field is read only. Reserved. Will , it a Ternary CAM. The Ternary nature of this CAM is useful for storing subnet masks, implementing ... Netlogic Microsystems
Original
datasheet

27 pages,
485.95 Kb

ternary content addressable memory ipCAM NL82721 NL82721R NLM82721R-25 NLM82721R-33 Ternary CAM "routing tables" ipCAM ethernet module nfa 102 TEXT
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Abstract: Comparison Note (1) APEX 20KE CAM Virtex-E CAM (2) Dimension of Widest CAM 32 × 5,120 128 × , CAM Virtex CAM 1,024 × 128 256 × 64 512 × 64 2,048 × 64 4,096 × 64 4,096 × 32 CAM , CAM Comparison: APEX 20KE vs. Virtex-E Devices Technical Brief 61 December 1999, ver. 1 , ://www.altera.com https://websupport.altera.com Content-addressable memory (CAM) is a memory technology that searches for data by its content rather than its address. When compared to RAM, CAM significantly reduces ... Altera
Original
datasheet

4 pages,
106.24 Kb

altera 48 fpga EP20K1000E ternary security cam EP20K200 EP20K200E-1 EP20K200E XCV1000E Ternary CAM limit switch cam type TEXT
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Abstract: bits ENCODE_2_MSB (CAM 64 words), three bits ENCODE_3_MSB (CAM 128 words) and four bits ENCODE , DECODE_1 (CAM 32 words), two bits DECODE_2 (CAM 64 words), three bits DECODE_3 (CAM 128 words) and four , 1, 1999 Application Note: Jean-Louis Brelet Summary CAM (Content Addressable Memory) offers increased data search speed. In various applications based on CAM, there are differing requirements for , XAPP201 XAPP201, "An Overview of Multiple CAM Designs in Virtex Family Devices", discusses the diverse solutions ... Xilinx
Original
datasheet

22 pages,
81.78 Kb

16 word 8 bit ram using vhdl 16x8-bit 16x8s vhdl code download for memory in cam vhdl code for 8 bit ram XAPP130 XAPP201 XCV50E XCV400 XCV300 XCV200 XCV150 XCV1000 XCV100 xapp204.zip RAM16x1S vhdl code for memory in cam XAPP204 8 bit data bus using vhdl TEXT
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Abstract: CAM Virtex-E CAM(2) CAM 32 × 5,120 128 × 160 CAM 5,120 × 32 2,560 × 8 (1 , 20KE CAM Virtex CAM 1,024 × 128 256 × 64 512 × 64 2,048 × 64 4,096 × 64 4,096 × 32 , CAM APEX 20KE vs. Virtex-E Technical Brief 61 December 1999, ver.1 Altera Corporation , ://www.altera.com/japan E-mail: japan@altera.com Content-Addressable MemoryCAM RAM CAM CAM APEXTM 20KE CAM PLD CAM CAM CAM CAM APEX 20KE CAM APEX - IPv4 - CAM APEX 20KE ... Altera
Original
datasheet

4 pages,
65.88 Kb

EP20K200E-1 EP20K200E EP20K200 EP20K1000E XCV1000E TEXT
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Abstract: Performance Read/Write CAMs Figure 2 shows the read mode of a 128-word x 9-bit CAM built on four block , _02_072401 Figure 2: CAM 128-word x 9-bit in Read Mode In a write mode, a 7-bit bus is used as an address for the 128 x 9 CAM. This address bus is composed of a 5-bit bus to each set of CAM32x9 address inputs and a 2-bit bus decoded to select one of the CAM blocks. To write 9-bits of data to one of the 128 , a 64-word CAM requiring seven address lines and a 128-word CAM requiring six address lines ... Xilinx
Original
datasheet

12 pages,
110.66 Kb

XC2V80 RAMB16 XAPP204 XC2V1000 XC2V1500 XC2V500 XC2V2000 XC2V250 XC2V40 verilog code for word recognition vhdl code for 8 bit ram CAM32x9 XAPP260 RAM32x1S vhdl code for memory in cam TEXT
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Abstract: . Features · · · · · · x 128 Synchronous Ternary CAM Architecture x 128 Local Mask Words allow masking of each CAM word on a bit by bit basis. Match Flag times: 25/28 ns CAM Index output (pipeline , 64 128 1K x 128 CAM Array 64 MUX Comparand Bus CBUS 1K x 128 Mask Array CAM Word , 1001" for 1K x 128 IPCAM-1. This CAM Type field is read only. Reserved. Will read `0'. This bit must , it a Ternary CAM. The Ternary nature of this CAM is ideal for enabling policy enforcement and packet ... Netlogic Microsystems
Original
datasheet

27 pages,
1365.54 Kb

Ternary CAM NLM82721R-33 NLM82721R-25 NL82721R NL82721 "routing tables" TEXT
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Abstract: fits into each LUT. A 32-word by 16-bit CAM would require 128 LUTs. The write operation uses the shift , -word CAM requiring six address lines, or a 128-word CAM requiring seven address lines and onward , bits ENCODE_2_MSB (CAM 64 words), three bits ENCODE_3_MSB (CAM 128 words) and four bits ENCODE , DECODE_2 (CAM 64 words), three bits DECODE_3 (CAM 128 words) and four bits DECODE_4 (CAM 256 words). , Content Addressable Memories (CAM) allow a fast search for specific data in a memory. Each application has ... Xilinx
Original
datasheet

17 pages,
74.53 Kb

XCV50E vhdl code download for memory in cam x203 XAPP201 XCV1000 SRL16 XCV50 XCV1000E XCV300 vhdl code of 4 bit comparator XAPP203 xapp203.zip vhdl code for 4-bit counter SRL16E vhdl code for memory in cam TEXT
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